Initial revision

From-SVN: r4284

gcc/config/sh/sh.c

+/* Output routines for GCC for Hitachi Super-H
+   Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+
+/* Contributed by Steve Chamberlain (sac@cygnus.com) */
+
+#include <stdio.h>
+#include "assert.h"
+#include "config.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "tree.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "obstack.h"
+#include "expr.h"
+
+
+static int add_constant ();
+static void dump_constants ();
+
+int current_function_anonymous_args;
+extern int current_function_pretend_args_size;
+
+/* Global variables for machine-dependent things. */
+
+/* Saved operands from the last compare to use when we generate an scc
+  or bcc insn. */
+
+rtx sh_compare_op0;
+rtx sh_compare_op1;
+
+/* Provides the class number of the smallest class containing
+   reg number */
+
+int regno_reg_class[FIRST_PSEUDO_REGISTER] =
+{
+  R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, PR_REGS, T_REGS, NO_REGS, MAC_REGS,
+  MAC_REGS,
+};
+
+/* Provide reg_class from a letter such as appears in the machine
+   description. */
+
+enum reg_class reg_class_from_letter[] =
+{
+  /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
+  /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
+  /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
+  /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
+  /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
+  /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ MAC_REGS,
+  /* y */ NO_REGS, /* z */ R0_REGS
+};
+
+
+/* Local label counter, used for constants in the pool and inside
+   pattern branches.  */
+
+static int lf;
+
+/* Used to work out sizes of instructions */
+static int first_pc;
+static int pc;
+
+static int dumpnext;
+
+/* Functions for generating procedure prologue and epilogue code */
+
+/* Adjust the stack and return the number of bytes taken to do it */
+
+static int
+output_stack_adjust (file, direction, size)
+     FILE *file;
+     int direction;
+     int size;
+{
+  int code_size;
+
+  if (size > 127)
+    {
+      fprintf (file, "\tmov.l	LK%d,r13\n",
+	       add_constant (GEN_INT (size * direction), SImode));
+
+      fprintf (file, "\tadd	r13,r15\n");
+      code_size += 4;
+    }
+  else if (size)
+    {
+      fprintf (file, "\tadd	#%d,r15\n", direction * size);
+      code_size += 2;
+    }
+  return code_size;
+}
+
+/* Generate code to push the regs specified in the mask, and return
+   the number of bytes the insns take. */
+
+static int
+push_regs (f, mask)
+     FILE *f;
+     int mask;
+{
+  int i;
+  int size = 0;
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      if (mask & (1 << i))
+	{
+	  fprintf (f, "\tmov.l	r%d,@-r15\n", i);
+	  size += 2;
+	}
+    }
+  return size;
+}
+
+
+/* Working out the right code to use for an epilogue can get quite
+   hairy, since there are only certain insns which can go in the delay
+   slot, and there may or may not be a delay insn provided already.
+
+   We generate a canonical list of the instructions to use to perform
+   the exit, massage that and output from that list */
+
+
+/* The structure of a canonical element. */
+
+typedef struct
+{
+  enum epi_type
+    {
+      STACK_ADJUST,		/* add i to stack pointer 	*/
+      POP,			/* pop into register i 		*/
+      RTS,			/* rts instruction 		*/
+      DELAY,			/* delay slot instruction 	*/
+      NOP,			/* a nop 			*/
+      DELETED,
+    } type;
+  int i;
+}
+
+epilogue_insn;
+
+static epilogue_insn epilogue_vec[20];
+static int epilogue_vec_len;
+
+static void
+set_epilogue_insn (type, l)
+     enum epi_type type;
+     int l;
+{
+  epilogue_vec[epilogue_vec_len].type = type;
+  epilogue_vec[epilogue_vec_len].i = l;
+  epilogue_vec_len++;
+}
+
+/* Delete an insn from the epilogue list. */
+
+static void
+delete_epilogue_insn (n)
+     int n;
+{
+  int j;
+
+  for (j = n; j < epilogue_vec_len; j++)
+    epilogue_vec[j] = epilogue_vec[j + 1];
+
+  epilogue_vec_len--;
+}
+
+/* Run through the epilogue list and optimize it. */
+
+static void
+optimize_epilogue_vec ()
+{
+  int i;
+
+  /* Turn two adds in a row into one add and kill empty adds */
+  for (i = 0; i < epilogue_vec_len - 1; i++)
+    {
+      if (epilogue_vec[i].type == STACK_ADJUST
+	  && epilogue_vec[i + 1].type == STACK_ADJUST)
+	{
+	  epilogue_vec[i].i += epilogue_vec[i + 1].i;
+	  delete_epilogue_insn (i + 1);
+	}
+      if (epilogue_vec[i].type == STACK_ADJUST
+	  && epilogue_vec[i].i == 0)
+	delete_epilogue_insn (i);
+    }
+
+  /* If the instruction after the RTS is a nop, see if it can be
+     changed */
+
+  for (i = 1; i < epilogue_vec_len - 1; i++)
+    {
+      if (epilogue_vec[i].type == RTS
+	  && epilogue_vec[i + 1].type == NOP)
+	{
+	  epilogue_vec[i + 1] = epilogue_vec[i - 1];
+	  delete_epilogue_insn (i - 1);
+	}
+    }
+
+  /* Delete all the instructions after the rts's delay slot */
+  for (i = 0; i < epilogue_vec_len; i++)
+    {
+      if (epilogue_vec[i].type == RTS)
+	{
+	  int j;
+
+	  for (j = i + 2; j < epilogue_vec_len; j++)
+	    epilogue_vec[j].type = DELETED;
+	  return;
+	}
+    }
+}
+
+/* Dump out the insns in epilogue vector. */
+
+static void
+output_epilogue_vec ()
+{
+  int i;
+
+  for (i = 0; i < epilogue_vec_len; i++)
+    {
+      switch (epilogue_vec[i].type)
+	{
+	case STACK_ADJUST:
+	  fprintf (asm_out_file, "\tadd	#%d,r15\n", epilogue_vec[i].i);
+	  break;
+
+	case NOP:
+	  fprintf (asm_out_file, "\tor	r0,r0\n");
+	  break;
+
+	case DELAY:
+	  final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
+			   asm_out_file, 1, 0, 1);
+	  break;
+
+	case DELETED:
+	  fprintf (asm_out_file, "\t!delete_epilogue_insnd\n");
+	  break;
+
+	case RTS:
+	  fprintf (asm_out_file, "\trts\n");
+	  break;
+
+	case POP:
+	  fprintf (asm_out_file, "\tmov.l	@r15+,r%d\n",
+		   epilogue_vec[i].i);
+	  break;
+	}
+    }
+  epilogue_vec_len = 0;
+}
+
+/* Number of bytes pushed for anonymous args */
+
+static int extra_push;
+
+/* Work out the registers which need to be saved, both as a mask and a
+   count */
+
+int
+calc_live_regs (count)
+     int *count;
+{
+  int reg;
+  int live_regs_mask = 0;
+  *count = 0;
+
+  for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
+    {
+      if (regs_ever_live[reg] && !call_used_regs[reg])
+	{
+	  (*count)++;
+	  live_regs_mask |= (1 << reg);
+	}
+    }
+  return live_regs_mask;
+}
+
+/* Generate a procedure prologue.  */
+
+void
+output_prologue (f, frame_size)
+     FILE *f;
+     int frame_size;
+{
+  int live_regs_mask;
+  int d;
+
+  pc = 0;
+
+  /* This only happens when an arg has been split, part in
+     registers, part in memory.  Allocate the stack space so there is
+     somewhere to put the value */
+
+  output_stack_adjust (f, -1, current_function_pretend_args_size);
+
+  live_regs_mask = calc_live_regs (&d);
+
+  extra_push = 0;
+
+  if (current_function_anonymous_args)
+    {
+      /* Push arg regs as if they'd been provided by caller in stack */
+      int i;
+      for (i = 0; i < NPARM_REGS; i++)
+	{
+	  int rn = NPARM_REGS + FIRST_PARM_REG - i - 1;
+	  if (i > NPARM_REGS - current_function_args_info)
+	    break;
+	  fprintf (f, "\tmov.l	r%d,@-r15\n", rn);
+	  extra_push += 4;
+	  pc += 2;
+	}
+    }
+
+  if (frame_pointer_needed)
+    {
+      /* Don't need to push the fp with the rest of the registers. */
+      live_regs_mask &= ~(1 << FRAME_POINTER_REGNUM);
+      pc += push_regs (f, live_regs_mask);
+      if (regs_ever_live[PR_REG])
+	{
+
+	  fprintf (f, "\tsts.l	pr,@-r15\n");
+	  pc += 2;
+	}
+
+      fprintf (f, "\tmov.l	r14,@-r15\n");
+      fprintf (f, "\tmov	r15,r14\n");
+      pc += 4;
+      pc += output_stack_adjust (f, -1, frame_size);
+    }
+  else
+    {
+      pc += push_regs (f, live_regs_mask);
+
+      if (regs_ever_live[PR_REG])
+	{
+
+	  fprintf (f, "\tsts.l	pr,@-r15\n");
+	  pc += 2;
+	}
+      pc += output_stack_adjust (f, -1, frame_size);
+    }
+}
+
+
+/* Generate a procedure epilogue. */
+
+void
+output_epilogue (f, frame_size)
+     FILE *f;
+     int frame_size;
+{
+  int live_regs_mask = 0;
+  int d;
+  int i;
+
+  live_regs_mask = calc_live_regs (&d);
+
+  /* Reclaim the room for the automatics. */
+
+  output_stack_adjust (f, 1, frame_size);
+
+  /* Make the frame pointer. */
+
+  if (frame_pointer_needed)
+    {
+      fprintf (f, "\tmov	r14,r15\n");
+      fprintf (f, "\tmov.l	@r15+,r14\n");
+      live_regs_mask &= ~(1 << FRAME_POINTER_REGNUM);
+    }
+
+  /* Get the PR register if it was clobbered in the function. */
+
+  if (regs_ever_live[PR_REG])
+    fprintf (f, "\tlds.l	@r15+,pr\n");
+
+  /* Pop all the registers */
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      int j = (FIRST_PSEUDO_REGISTER - 1) - i;
+      if (live_regs_mask & (1 << j))
+	{
+	  set_epilogue_insn (POP, j);
+	}
+    }
+
+  /* Need to adjust the stack by some amount of bytes since we've pushed
+     some of the args which normally come in registers */
+
+  set_epilogue_insn (STACK_ADJUST, extra_push);
+
+  /* Need to adjust the stack by some amount of bytes if there
+     an arg has been split part register and part stack */
+
+  set_epilogue_insn (STACK_ADJUST, current_function_pretend_args_size);
+
+  set_epilogue_insn (RTS, 0);
+
+  /* Got here without dumping a register pop into the delay slot */
+  if (current_function_epilogue_delay_list)
+    {
+      set_epilogue_insn (DELAY, 0);
+    }
+  set_epilogue_insn (NOP, 0);
+
+  optimize_epilogue_vec ();
+
+  output_epilogue_vec ();
+
+  dump_constants ();
+  current_function_anonymous_args = 0;
+}
+
+/* Print the operand address in x to the stream */
+
+void
+print_operand_address (stream, x)
+     FILE *stream;
+     rtx x;
+{
+  switch (GET_CODE (x))
+    {
+    case REG:
+      fprintf (stream, "@%s", reg_names[REGNO (x)]);
+      break;
+
+    case PLUS:
+      {
+	rtx base = XEXP (x, 0);
+	rtx index = XEXP (x, 1);
+
+	if (GET_CODE (base) != REG)
+	  {
+	    /* Ensure that BASE is a register (one of them must be). */
+	    rtx temp = base;
+	    base = index;
+	    index = temp;
+	  }
+
+	switch (GET_CODE (index))
+	  {
+	  case CONST_INT:
+	    fprintf (stream, "@(%d,%s)",
+		     INTVAL (index),
+		     reg_names[REGNO (base)]);
+	    break;
+
+	  case REG:
+	    fprintf (stream, "@(%s,%s)",
+		     reg_names[REGNO (base)],
+		     reg_names[REGNO (index)]);
+	    break;
+
+	  default:
+	    abort ();
+	  }
+      }
+
+      break;
+    case PRE_DEC:
+      fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
+      break;
+
+    case POST_INC:
+      fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
+      break;
+
+    default:
+      output_addr_const (stream, x);
+      break;
+    }
+}
+
+/* Print operand x (an rtx) in assembler syntax to file stream
+   according to modifier code.
+
+ '*'  print a local label
+ '^'  increment the local label number
+ '!'  dump the constant table
+ '#'  output a nop if there is nothing to put in the delay slot
+ 'R'  print the next register or memory location along, ie the lsw in
+      a double word value
+ 'I'  put something into the constant pool and print its label */
+
+void
+print_operand (stream, x, code)
+     FILE *stream;
+     rtx x;
+     int code;
+{
+  switch (code)
+    {
+    case '*':
+      fprintf (stream, "LF%d", lf);
+      break;
+    case '!':
+      dump_constants();
+      break;
+    case '^':
+      lf++;
+      break;
+
+    case '#':
+      /* Output a nop if there's nothing in the delay slot */
+      if (dbr_sequence_length () == 0)
+	{
+	  fprintf (stream, "\n\tor	r0,r0\t!wasted slot");
+	}
+      break;
+
+    case 'I':
+      fprintf (asm_out_file, "LK%d", add_constant (x, SImode));
+      break;
+
+    case 'R':
+      /* Next location along in memory or register*/
+      switch (GET_CODE (x))
+	{
+	case REG:
+	  fputs (reg_names[REGNO (x) + 1], (stream));
+	  break;
+	case MEM:
+	  print_operand_address (stream,
+			       XEXP (adj_offsettable_operand (x, 4), 0), 0);
+	  break;
+	}
+      break;
+
+    default:
+      switch (GET_CODE (x))
+	{
+	case REG:
+	  fputs (reg_names[REGNO (x)], (stream));
+	  break;
+	case MEM:
+	  output_address (XEXP (x, 0));
+	  break;
+	default:
+	  fputc ('#', stream);
+	  output_addr_const (stream, x);
+	  break;
+
+	}
+      break;
+    }
+}
+
+
+
+/* Define the offset between two registers, one to be eliminated, and 
+   the other its replacement, at the start of a routine.  */
+
+int
+initial_elimination_offset (from, to)
+{
+  int regs_saved;
+  int d = calc_live_regs (&regs_saved);
+  int total_saved_regs_space = (regs_saved + regs_ever_live[PR_REG]) * 4;
+  int total_auto_space = get_frame_size ();
+
+
+  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
+    {
+      return total_saved_regs_space;
+    }
+
+  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    {
+      return total_saved_regs_space + total_auto_space;
+    }
+
+  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    {
+      return total_auto_space;
+    }
+}
+
+delay_slots_for_epilogue ()
+{
+  /* We need to find something to fill the epilogue if there won't be
+     any instructions to make the stack or pop registers which can be
+     moved into the slot */
+
+  int d;
+  calc_live_regs (&d);
+  return !(get_frame_size () + d);
+}
+
+
+/* Prepare operands for a move define_expand; specifically, one of the
+   operands must be in a register */
+
+void
+prepare_move_operands (operands, mode)
+     rtx operands[];
+     enum machine_mode mode;
+{
+  /* One of the operands has to be a register */
+  if ((!register_operand (operands[0], mode)
+       && !register_operand (operands[1], mode))
+      || GET_CODE(operands[1]) == PLUS)
+    {
+      /* copy the source to a register */
+      operands[1] = copy_to_mode_reg (mode, operands[1]);
+    }
+}
+
+
+/* Prepare the operands for an scc instruction; make sure that the
+   compare has been done.  */
+rtx
+prepare_scc_operands (code)
+{
+  if (GET_CODE(sh_compare_op0) != REG 
+      || REGNO(sh_compare_op0) != T_REG)
+    {
+      /* First need a compare insn */
+      emit_insn (gen_rtx (SET, SImode, 
+			  gen_rtx (REG, SImode, T_REG),
+			  gen_rtx (code, SImode, sh_compare_op0,
+				   sh_compare_op1)));
+    }
+  return gen_rtx(REG, SImode, T_REG);
+}
+
+/* Functions to output assembly */
+
+/* Return a sequence of instructions to perform DI move, taking into
+   account overlapping source and dest registers */
+
+char *
+output_movedouble (operands, mode)
+     rtx operands[];
+     enum machine_mode mode;
+{
+  if (register_operand (operands[0], mode)
+      && register_operand (operands[1], mode))
+    {
+      if (REGNO (operands[1]) == MACH_REG)
+	return "sts	mach,%0\n\tsts	macl,%R0";
+      return "mov	%1,%0\n\tmov	%R1,%R0";
+    }
+
+  if (GET_CODE (operands[1]) == CONST_INT)
+    {
+      if (INTVAL (operands[1]) < 0)
+	return "mov	#-1,%0\n\tmov	%1,%R0";
+      else
+	return "mov	#0,%0\n\tmov	%1,%R0";
+    }
+
+  if (GET_CODE (operands[1]) == MEM)
+    {
+      int idxreg = -1;
+      rtx inside = XEXP (operands[1], 0);
+
+      if (GET_CODE (inside) == REG)
+	idxreg = REGNO (inside);
+      else if (GET_CODE (inside) == PLUS)
+	{
+	  rtx lhs = XEXP (inside, 0);
+	  rtx rhs = XEXP (inside, 1);
+	  if (GET_CODE (lhs) == REG)
+	    idxreg = REGNO (lhs);
+	  else if (GET_CODE (rhs) == REG)
+	    idxreg = REGNO (rhs);
+	  else
+	    abort ();
+	}
+      else
+	abort ();
+
+      if (REGNO (operands[0]) != idxreg)
+	{
+	  /* The dest register is mentioned in the addressing mode,
+	     so print them the other way around */
+	  return "mov.l	%1,%0\n\tmov.l	%R1,%R0 ! one way";
+	}
+      return "mov.l	%R1,%R0\n\tmov.l	%1,%0 ! other way";
+    }
+
+  return "mov.l	%R1,%R0\n\tmov.l	%1,%0";
+}
+
+/* Emit assembly to shift reg by k bits */
+
+char *
+output_shift (string, reg, k)
+     char *string;
+     rtx reg;
+     rtx k;
+{
+  int s = INTVAL (k);
+  while (s)
+    {
+      char *out;
+      int d;
+
+      if (s >= 16)
+	{
+	  d = 16;
+	  out = "16";
+	}
+      else if (s >= 8)
+	{
+	  d = 8;
+	  out = "8";
+	}
+      else if (s >= 2)
+	{
+	  d = 2;
+	  out = "2";
+	}
+      else
+	{
+	  d = 1;
+	  out = "";
+	}
+      fprintf (asm_out_file, "\t%s%s\tr%d\n", string, out, REGNO (reg));
+      s -= d;
+    }
+  return "";
+}
+
+/* Return the text of the branch instruction which matches its length
+   attribute.  */
+
+char *
+output_branch (logic, insn)
+     int logic;
+     rtx *insn;
+{
+  extern rtx recog_operand[];
+  int label = lf++;
+  
+  switch (get_attr_length (insn))
+    {
+    case 2:
+      /* Simple branch in range -200..+200 bytes */
+      return logic ? "bt	%l0" : "bf	%l0";
+
+    case 6:
+      /* Branch in range -4000..+4000 bytes */
+      fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
+      output_asm_insn ("bra	%l0	! 12 bit cond ", recog_operand);
+      fprintf (asm_out_file, "\tor	r0,r0\n");
+      fprintf (asm_out_file, "LF%d:\n", label);
+      lf++;
+      return "";
+
+    case 8:
+      /* Branches a long way away */
+	
+      fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
+      output_asm_insn ("mov.l	%I0,r13", recog_operand);
+      fprintf (asm_out_file, "\tjmp	@r13	! 32 cond \n");
+      fprintf (asm_out_file, "\tor	r0,r0\n");
+      fprintf (asm_out_file, "LF%d:\n", label);
+      return "";
+    }
+  return "bad";
+
+}
+
+/* Predicates used by the templates */
+
+/* Nonzero if OP is a valid source operand for an arithmetic insn.  */
+
+int
+arith_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (register_operand (op, mode))
+    return 1;
+
+  if (GET_CODE (op) == CONST_INT)
+    {
+      if (CONST_OK_FOR_I (INTVAL (op)))
+	return 1;
+    }
+  return 0;
+}
+
+
+/* Nonzero if OP is a valid source operand for a logical operation */
+
+int
+logical_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (register_operand (op, mode))
+    return 1;
+
+  if (GET_CODE (op) == CONST_INT)
+    {
+      if (CONST_OK_FOR_L (INTVAL (op)))
+	return 1;
+    }
+  return 0;
+}
+
+/* Nonzero if p is a valid shift operand for lshr and ashl */
+
+int
+ok_shift_value (p)
+     rtx p;
+{
+  if (GET_CODE (p) == CONST_INT)
+    {
+      switch (INTVAL (p))
+	{
+	case 1:
+	case 2:
+	case 8:
+	case 16:
+	  return 1;
+	default:
+	  if (TARGET_FASTCODE)
+	    return 1;
+	}
+    }
+  return 0;
+}
+
+/* Nonzero if the arg is an immediate which has to be loaded from
+   memory */
+
+int
+hard_immediate_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (immediate_operand (op, mode))
+    {
+      if (GET_CODE (op) == CONST_INT
+	  && INTVAL (op) >= -128 && INTVAL (op) < 127)
+	return 0;
+      return 1;
+    }
+  return 0;
+}
+
+/* The SH cannot load a large constant into a register, constants have to
+   come from a pc relative load.  The reference of a pc relative load
+   instruction must be less than 1k infront of the instruction.  This
+   means that we often have to dump a constant inside a function, and
+   generate code to branch around it.
+
+   It is important to minimize this, since the branches will slow things
+   down and make things bigger.
+
+  Worst case code looks like:
+
+      mov.l L1,rn
+      bra   L2
+      nop
+      align
+L1:   .long value
+L2:
+      ..
+
+      mov.l L3,rn
+      bra   L4
+      nop
+      align
+L3:   .long value
+L4:
+      ..
+
+   During shorten_branches we notice the instructions which can have a
+   constant table in them, if we see two that are close enough
+   together, we move the constants from the first table to the second
+   table and continue.  This process can happen again and again, and
+   in the best case, moves the constant table outside of the function.
+
+   In the above example, we can tell that L3 is within 1k of L1, so
+   the first move can be shrunk from the 3 insn+constant sequence into
+   just 1 insn, and the constant moved to L3 to make:
+
+   mov.l	L1,rn
+   ..
+   mov.l	L3,rn
+   bra		L4
+   nop
+   align
+L3:.long value
+L4:.long value
+
+   Then the second move becomes the target for the shortening process.
+
+   We keep a simple list of all the constants accumulated in the
+   current pool so there are no duplicates in a single table, but
+   they are not factored into the size estimates.
+
+*/
+
+typedef struct
+{
+  rtx value;
+  int number;
+  enum machine_mode mode;
+} pool_node;
+
+/* The maximum number of constants that can fit into one pool, since
+   the pc relative range is 0...1020 bytes and constants are at least 4
+   bytes long */
+
+#define MAX_POOL_SIZE (1020/4)
+static pool_node pool_vector[MAX_POOL_SIZE];
+static int pool_size;
+
+
+/* Add a constant to the pool and return its label number.  */
+
+static int
+add_constant (x, mode)
+     rtx x;
+     enum machine_mode mode;
+{
+  int i;
+
+  /* Start the countdown on the first constant */
+
+  if (!pool_size)
+    {
+      first_pc = pc;
+    }
+
+  /* First see if we've already got it */
+
+  for (i = 0; i < pool_size; i++)
+    {
+
+      if (x->code == pool_vector[i].value->code
+	  && mode == pool_vector[i].mode)
+	{
+	  if (x->code == CODE_LABEL)
+	    {
+	      if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
+		continue;
+	    }
+	}
+
+      if (rtx_equal_p (x, pool_vector[i].value))
+	return pool_vector[i].number;
+    }
+  
+
+  pool_vector[pool_size].value = x;
+  pool_vector[pool_size].mode = mode;
+  pool_vector[pool_size].number = lf;
+  pool_size++;
+
+  return lf++;
+}
+
+/* Nonzero if the insn could take a constant table.  */
+
+static int
+has_constant_table (insn)
+     rtx insn;
+{
+  rtx body;
+
+  if (GET_CODE (insn) == NOTE
+      || GET_CODE (insn) == BARRIER
+      || GET_CODE (insn) == CODE_LABEL)
+    return 0;
+
+  body = PATTERN (insn);
+  if (GET_CODE (body) == SEQUENCE)
+    return 0;
+  if (GET_CODE (body) == ADDR_VEC)
+    return 0;
+  if (GET_CODE (body) == USE)
+    return 0;
+  if (GET_CODE (body) == CLOBBER)
+    return 0;
+  if (get_attr_constneed (insn) == CONSTNEED_YES)
+    return 1;
+
+  if (GET_CODE (body) == UNSPEC_VOLATILE)
+    {
+      return INTVAL (XVECEXP (body, 0, 0)) == 1;
+    }
+  return 0;
+}
+
+/*  Adjust the length of an instruction.
+
+    We'll look at the previous instruction which holds a constant
+    table and see if we can move the table to here instead. */
+
+int target_insn_uid;
+int target_insn_smallest_size;
+
+int target_pc;
+int target_insn_range;
+int current_pc;
+int table_size;
+
+void
+adjust_insn_length (insn, insn_lengths)
+     rtx insn;
+     short *insn_lengths;
+{
+  int uid = INSN_UID (insn);
+
+  current_pc += insn_lengths[uid];
+
+  if (has_constant_table (insn)) 
+    {
+      if (current_pc >= target_insn_range)
+	{
+	  /* This instruction is further away from the referencing
+	     instruction than it can reach, so we'll stop accumulating
+	     from that one and start fresh. */
+	  target_pc = current_pc;
+	  target_insn_range = current_pc + 1000;
+	}
+      else
+	{
+	  /* This instruction is within the reach of the target,
+	     remove the constant table from the target by adjusting
+	     downwards, and increase the size of this one to
+	     compensate.  */
+
+
+	  /* Add the stuff from this insn to what will go in the
+	     growing table. */
+
+	  table_size += get_attr_constantsize (insn);
+
+	  /* The target shinks to its smallest natural size */
+	  insn_lengths[target_insn_uid] = target_insn_smallest_size;
+
+	  /* The current insn grows to be its larger size plust the
+	     table size. */
+
+	  insn_lengths[uid] = get_attr_largestsize (insn) + table_size;
+
+	}
+      /* Current insn becomes the target.  */
+      target_insn_uid = uid;
+      target_insn_smallest_size = get_attr_smallestsize (insn);
+
+    }
+
+}
+
+
+/* Dump out the pending constant pool.  */
+
+static void
+dump_constants ()
+{
+  int i;
+  for (i = 0; i < pool_size; i++)
+    {
+      pool_node *p = pool_vector + i;
+      fprintf (asm_out_file, "\n\t! constants - waited %d\n", pc - first_pc);
+      fprintf (asm_out_file, "\t.align\t2\n");
+      fprintf (asm_out_file, "LK%d:", p->number);
+      switch (GET_MODE_CLASS (p->mode))
+	{
+	case MODE_INT:
+	case MODE_PARTIAL_INT:
+	  assemble_integer (p->value, GET_MODE_SIZE (p->mode), 1);
+	  break;
+	case MODE_FLOAT:
+	  {
+	    union real_extract u;
+	    bcopy (&CONST_DOUBLE_LOW (p->value), &u, sizeof u);
+	    assemble_real (u.d, p->mode);
+	  }
+	}
+
+      fprintf (asm_out_file, "\n");
+    }
+  pool_size = 0;
+  current_pc = 0;
+  target_insn_range = 0;
+}
+
+
+/* Emit the text to load a value from a constant table.  */
+
+char *
+output_movepcrel (insn, operands, mode)
+     rtx insn;
+     rtx operands[];
+     enum machine_mode mode;
+{
+  int len = GET_MODE_SIZE (mode);
+  int rn = REGNO (operands[0]);
+
+  fprintf (asm_out_file, "\tmov.l	LK%d,r%d\n",
+	   add_constant (operands[1], mode), rn);
+
+  if (GET_MODE_SIZE(mode) > 4) 
+    {
+      fprintf (asm_out_file,
+	       "\tmov.l	LK%d+4,r%d\n",
+	       add_constant (operands[1], mode),
+	       rn + 1);
+
+    } 
+  /* If this instruction is as small as it can be, there can be no 
+     constant table attached to it.  */
+  if (get_attr_length (insn) !=  get_attr_smallestsize (insn))
+    {
+      /* This needs a constant table */
+      fprintf (asm_out_file, "\t!constant table start\n");
+      fprintf (asm_out_file, "\tbra	LF%d\n", lf);
+      fprintf (asm_out_file, "\tor	r0,r0 ! wasted slot\n");
+      dump_constants ();
+      fprintf (asm_out_file, "LF%d:\n", lf++);
+      fprintf (asm_out_file, "\t!constant table end\n");
+    }
+  return "";
+}
+
+
+/* Dump out interesting debug info */
+
+void
+final_prescan_insn (insn, opvec, noperands)
+     rtx insn;
+     rtx *opvec;
+     int noperands;
+{
+  register rtx body = PATTERN (insn);
+
+  if (target_flags & ISIZE_BIT)
+    {
+      extern int *insn_addresses;
+
+      fprintf (asm_out_file, "\n!%04x*\n",
+	       insn_addresses[INSN_UID (insn)] + 0x10);
+
+      fprintf (asm_out_file, "\n!%04x %d %04x len=%d\n",
+	       pc, pool_size, first_pc, get_attr_length (insn));
+
+      if (TARGET_DUMP_RTL)
+	print_rtl (asm_out_file, body);
+
+      pc += get_attr_length (insn);
+    }
+}
+

gcc/config/sh/sh.h

+/* Definitions of target machine for GNU compiler, for Hitachi Super-H.
+   Copyright (C) 1993 Free Software Foundation, Inc.
+
+   Contributed by Steve Chamberlain (sac@cygnus.com)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+
+/* Run-time Target Specification.  */
+#define TARGET_SH
+
+#define TARGET_VERSION  \
+  fputs (" (Hitachi SH)", stderr);
+
+/* Generate SDB debugging information.  */
+
+#define SDB_DEBUGGING_INFO  1
+
+#define SDB_DELIM ";"
+
+#define CPP_PREDEFINES "-D__sh__"
+
+
+/* Omitting the frame pointer is a very good idea on the SH */
+
+#define OPTIMIZATION_OPTIONS(OPTIMIZE)  \
+{					\
+  if (OPTIMIZE)				\
+    flag_omit_frame_pointer = 1;	\
+   if (OPTIMIZE==0)OPTIMIZE=1;		\
+}
+
+/* Run-time compilation parameters selecting different hardware subsets. */
+
+extern int target_flags;
+#define ISIZE_BIT  1
+#define FAST_BIT   2
+#define MULSI3_BIT 4
+#define MAC_BIT    8
+#define RTL_BIT    16
+#define DT_BIT     32
+#define DALIGN_BIT 64
+
+/* Nonzero if we should generate code using muls.l insn */
+#define TARGET_HAS_MULSI3 (target_flags & MULSI3_BIT)
+
+/* Nonzero if we should generate faster code rather than smaller code */
+#define TARGET_FASTCODE   (target_flags & FAST_BIT)
+
+/* Nonzero if we should dump out instruction size info */
+#define TARGET_DUMPISIZE  (target_flags & ISIZE_BIT)
+
+/* Nonzero if we should try to generate mac instructions */
+#define TARGET_MAC        (target_flags & MAC_BIT)
+
+/* Nonzero if we should dump the rtl in the assembly file. */
+#define TARGET_DUMP_RTL	  (target_flags & RTL_BIT)
+
+/* Nonzero if the target has a decrement and test instruction .*/
+#define TARGET_HAS_DT     (target_flags & DT_BIT)
+
+/* Nonzero to align doubles on 64 bit boundaries */
+#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
+
+#define TARGET_SWITCHES  	\
+{ {"isize", 	( ISIZE_BIT)  },\
+  {"space", 	(-FAST_BIT)   },\
+  {"hasmulsi",  ( MULSI3_BIT) },\
+  {"hasdt", 	( DT_BIT)     },\
+  {"ac",  	( MAC_BIT)    },\
+  {"dalign",  	( DALIGN_BIT) },\
+  {"",   	TARGET_DEFAULT} \
+}
+
+#define TARGET_DEFAULT  FAST_BIT
+
+
+/* Target machine storage Layout.  */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.  */
+#define BITS_BIG_ENDIAN  0
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is the lowest
+   numbered.  */
+#define WORDS_BIG_ENDIAN 1
+
+/* Number of bits in an addressable storage unit */
+#define BITS_PER_UNIT  8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD  32
+#define MAX_BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD	4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE  32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY  	32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY  32
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY  16
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY  32
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT  (TARGET_ALIGN_DOUBLE ? 64 : 32)
+
+/* The best alignment to use in cases where we have a choice.  */
+#define FASTEST_ALIGNMENT 32
+
+/* Every structures size must be a multiple of 32 bits.  */
+#define STRUCTURE_SIZE_BOUNDARY 32
+
+/* Make strings word-aligned so strcpy from constants will be faster.  */
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
+  ((TREE_CODE (EXP) == STRING_CST	\
+    && (ALIGN) < FASTEST_ALIGNMENT)	\
+   ? FASTEST_ALIGNMENT : (ALIGN))
+
+/* Make arrays of chars word-aligned for the same reasons.  */
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  (TREE_CODE (TYPE) == ARRAY_TYPE		\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+
+/* Set this nonzero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+
+/* Standard register usage.  */
+
+/* Register allocation for our first guess 
+
+	r0-r3		scratch
+	r4-r7		args in and out
+	r8-r11		call saved
+	r12		
+	r13		assembler temp
+	r14		frame pointer
+	r15		stack pointer
+	ap		arg pointer (doesn't really exist, always eliminated)
+	pr		subroutine return address
+	t               t bit
+	mach		multiply/accumulate result
+	macl
+*/
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+
+   SH has 16 integer registers and 4 control registers + the arg
+   pointer */
+
+#define FIRST_PSEUDO_REGISTER 22
+
+#define PR_REG   17
+#define T_REG    18
+#define GBR_REG  19
+#define MACH_REG 20
+#define MACL_REG 21
+
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.  */
+ /*  r0  r1  r2  r3  r4  r5  r6  r7  r8 
+     r9  r10 r11 r12 r13 r14 r15 ap  pr  t   gbr mh   ml */
+#define FIXED_REGISTERS  \
+   { 0,  0,  0,  0,  0,  0,  0,  0,  0, 		\
+     0,  0,  0,  0,  1,  0,  1,  1,  1,  1,  1, 1,   1}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+
+ /*  r0  r1  r2  r3  r4  r5  r6  r7  r8 
+     r9  r10 r11 r12 r13 r14 r15 ap  pr  t   gbr mh  ml */
+#define CALL_USED_REGISTERS \
+   { 1,  1,  1,  1,  1,  1,  1,  1,  0, \
+     0,  0,  0,  1,  1,  0,  1,  1,  1,  1,  1, 1, 1}
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On the SH regs are UNITS_PER_WORD bits wide; */
+#define HARD_REGNO_NREGS(REGNO, MODE)  \
+   (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   We may keep double values in even registers */
+
+#define HARD_REGNO_MODE_OK(REGNO, MODE)  \
+  ((TARGET_ALIGN_DOUBLE && GET_MODE_SIZE(MODE) > 4) ? (((REGNO)&1)==0) : 1)
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+  ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* Define this if the program counter is overloaded on a register.  */
+/* #define PC_REGNUM		15*/
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM	15
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM	14
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms may be accessed
+   via the stack pointer) in functions that seem suitable.  */
+#define FRAME_POINTER_REQUIRED	0
+
+/* Definitions for register eliminations.
+
+   We have two registers that can be eliminated on the m88k.  First, the
+   frame pointer register can often be eliminated in favor of the stack
+   pointer register.  Secondly, the argument pointer register can always be
+   eliminated; it is replaced with either the stack or frame pointer.  */
+
+/* This is an array of structures.  Each structure initializes one pair
+   of eliminable registers.  The "from" register number is given first,
+   followed by "to".  Eliminations of the same "from" register are listed
+   in order of preference.  */
+
+#define ELIMINABLE_REGS				\
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM},}
+
+/* Given FROM and TO register numbers, say whether this elimination
+   is allowed.  */
+#define CAN_ELIMINATE(FROM, TO) \
+  (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
+
+/* Define the offset between two registers, one to be eliminated, and the other
+   its replacement, at the start of a routine.  */
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+  OFFSET = initial_elimination_offset (FROM, TO)
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM	16
+
+/* Register in which the static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM	13
+
+/* If the structure value address is not passed in a register, define
+   this as an expression returning an RTX for the place
+   where the address is passed.  If it returns 0, the address is
+   passed as an "invisible" first argument. */
+
+#define STRUCT_VALUE 0
+
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+
+/* The SH has two sorts of general registers, R0 and the rest.  R0 can 
+   be used as the destination of some of the arithmetic ops. There are
+   also some special purpose registers; the T bit register, the
+   Procedure Return Register and the Multipy Accumulate Registers */
+
+enum reg_class
+{
+  NO_REGS,
+  R0_REGS,
+  GENERAL_REGS,
+  PR_REGS,
+  T_REGS,
+  MAC_REGS,
+  ALL_REGS,
+  LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES  (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+#define REG_CLASS_NAMES  \
+{			\
+  "NO_REGS",		\
+  "R0_REGS",		\
+  "GENERAL_REGS",	\
+  "PR_REGS",		\
+  "T_REGS",		\
+  "MAC_REGS",		\
+  "ALL_REGS",		\
+}
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS      \
+{				\
+  0x000000,  /* NO_REGS      */	\
+  0x000001,  /* R0_REGS      */	\
+  0x01FFFF,  /* GENERAL_REGS */	\
+  0x020000,  /* PR_REGS      */	\
+  0x040000,  /* T_REGS       */	\
+  0x300000,  /* MAC_REGS     */	\
+  0x37FFFF   /* ALL_REGS     */	\
+}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+extern int regno_reg_class[];
+#define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
+
+/* The order in which register should be allocated.  */
+#define REG_ALLOC_ORDER  \
+  { 1,2,3,0,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21}
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS  R0_REGS
+#define BASE_REG_CLASS	 GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine 
+   description. */
+extern enum reg_class reg_class_from_letter[];
+
+#define REG_CLASS_FROM_LETTER(C) \
+   ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
+
+
+/* The letters I, J, K, L and M in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+	I: arithmetic operand -127..128, as used in add, sub, etc
+	L: logical operand 0..255, as used in add, or, etc.
+	M: constant 1
+	K: shift operand 1,2,8 or 16 */
+
+
+#define CONST_OK_FOR_I(VALUE) ((VALUE)>= -128 && (VALUE) <= 127)
+#define CONST_OK_FOR_L(VALUE) ((VALUE)>= 0 && (VALUE) <= 255)
+#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
+#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)     \
+     ((C) == 'I' ? CONST_OK_FOR_I (VALUE)   \
+    : (C) == 'L' ? CONST_OK_FOR_L (VALUE)   \
+    : (C) == 'M' ? CONST_OK_FOR_M (VALUE)   \
+    : (C) == 'K' ? CONST_OK_FOR_K (VALUE)   \
+    : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
+   ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
+	      && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE))  \
+    : 0)
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+
+#define PREFERRED_RELOAD_CLASS(X, CLASS)  (CLASS)
+
+/* Return the register class of a scratch register needed to copy IN into
+   or out of a register in CLASS in MODE.  If it can be done directly,
+   NO_REGS is returned.  */
+
+#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS. 
+
+   On SH this is the size of MODE in words */
+#define CLASS_MAX_NREGS(CLASS, MODE)  \
+     ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define the number of register that can hold parameters.
+   These two macros are used only in other macro definitions below.  */
+#define NPARM_REGS 4
+#define FIRST_PARM_REG 4
+#define FIRST_RET_REG 4
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD  
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD 
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+#define STARTING_FRAME_OFFSET  0
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.  */
+#define PUSH_ROUNDING(NPUSHED)  (((NPUSHED) + 3) & ~3)
+
+/* Offset of first parameter from the argument pointer register value.  */
+#define FIRST_PARM_OFFSET(FNDECL)  0
+
+/* Value is the number of byte of arguments automatically
+   popped when returning from a subroutine call.
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.
+
+   On the SH, the caller does not pop any of its arguments that were passed
+   on the stack.  */
+#define RETURN_POPS_ARGS(FUNTYPE, SIZE)  0
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+#define FUNCTION_VALUE(VALTYPE, FUNC)  \
+    gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+#define LIBCALL_VALUE(MODE)  \
+    gen_rtx (REG, MODE, FIRST_RET_REG)
+
+/* 1 if N is a possible register number for a function value.
+   On the SH, only r4 can return results.  */
+#define FUNCTION_VALUE_REGNO_P(REGNO)  \
+	  ((REGNO) == FIRST_RET_REG)
+
+/* 1 if N is a possible register number for function argument passing.*/
+
+#define FUNCTION_ARG_REGNO_P(REGNO)  \
+  ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
+
+
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On SH, this is a single integer, which is a number of words
+   of arguments scanned so far (including the invisible argument,
+   if any, which holds the structure-value-address).
+   Thus NARGREGS or more means all following args should go on the stack.  */
+
+#define CUMULATIVE_ARGS  int
+
+#define ROUND_ADVANCE(SIZE)	\
+  ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Round a register number up to a proper boundary for an arg of mode 
+   MODE. 
+   
+   We round to an even reg for things larger than a word */
+
+#define ROUND_REG(X, MODE) 					\
+  ((TARGET_ALIGN_DOUBLE 					\
+   && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) 		\
+   ? ((X) + ((X) & 1)) : (X))
+
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On SH, the offset always starts at 0: the first parm reg is always
+   the same reg.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME)  \
+  ((CUM) = 0)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be
+   available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) = (ROUND_REG ((CUM), (MODE))			\
+	   + ((MODE) != BLKmode				\
+	      ? ROUND_ADVANCE (GET_MODE_SIZE (MODE))	\
+	      : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).
+
+   On SH the first args are normally in registers
+   and the rest are pushed.  Any arg that starts within the first
+   NPARM_REGS words is at least partially passed in a register unless
+   its data type forbids.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)			\
+  (NAMED && ROUND_REG ((CUM), (MODE)) < NPARM_REGS		\
+   && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE)))		\
+   && ((TYPE)==0 || (MODE) != BLKmode				\
+       || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0))		\
+   ? gen_rtx (REG, (MODE),					\
+  	    (FIRST_PARM_REG + ROUND_REG ((CUM), (MODE))))	\
+   : 0)
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.
+   Any arg that starts in the first NPARM_REGS regs but won't entirely
+   fit in them needs partial registers on the SH.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 		\
+  ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS				\
+    && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE)))			\
+    && ((TYPE)==0 || (MODE) != BLKmode					\
+	|| (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0))			\
+    && (ROUND_REG ((CUM), (MODE))					\
+	+ ((MODE) == BLKmode						\
+	   ? ROUND_ADVANCE (int_size_in_bytes (TYPE))			\
+	   : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0)	\
+   ? (NPARM_REGS - ROUND_REG ((CUM), (MODE)))				\
+   : 0)
+
+extern int current_function_anonymous_args;
+
+/* Perform any needed actions needed for a function that is receiving a
+   variable number of arguments. */
+
+#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
+  current_function_anonymous_args = 1;
+
+
+/* Generate assembly output for the start of a function.  */
+
+#define FUNCTION_PROLOGUE(STREAM, SIZE)  \
+  output_prologue ((STREAM), (SIZE))
+
+/* Call the function profiler with a given profile label. */
+
+#define FUNCTION_PROFILER(STREAM,LABELNO)  		\
+{							\
+    fprintf(STREAM, "\tsts.l	pr,@-r15\n");		\
+    fprintf(STREAM, "\tjsr\tmcount\n");			\
+    fprintf(STREAM, "\tor	r0,r0\n");		\
+    fprintf(STREAM, "\t.long\tLP%d\n", (LABELNO));	\
+}
+
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 0
+
+/* Generate the assembly code for function exit. */
+
+#define FUNCTION_EPILOGUE(STREAM, SIZE)  \
+  output_epilogue ((STREAM), (SIZE))
+
+#define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
+  (get_attr_in_delay_slot(INSN) == IN_DELAY_SLOT_YES)  
+
+#define DELAY_SLOTS_FOR_EPILOGUE \
+  delay_slots_for_epilogue();
+
+/* Output assembler code for a block containing the constant parts
+   of a trampoline, leaving space for the variable parts.
+
+   On the SH, the trapoline looks like
+   1 0000 D301     		mov.l	l1,r3
+   2 0002 DD02     	   	mov.l	l2,r13
+   3 0004 4D2B     		jmp	@r13
+   4 0006 200B     		or	r0,r0
+   5 0008 00000000 	l1:  	.long   function
+   6 000c 00000000 	l2:	.long   area	
+*/
+#define TRAMPOLINE_TEMPLATE(FILE)  		\
+{						\
+  fprintf ((FILE), "	.word	0xd301\n");	\
+  fprintf ((FILE), "	.word	0xdd02\n");	\
+  fprintf ((FILE), "	.word	0x4d2b\n");        \
+  fprintf ((FILE), "	.word	0x200b\n");	\
+  fprintf ((FILE), "	.long	0\n");		\
+  fprintf ((FILE), "	.long	0\n");		\
+}
+
+/* Length in units of the trampoline for entering a nested function.  */
+#define TRAMPOLINE_SIZE  16
+
+/* Alignment required for a trampoline in units.  */
+#define TRAMPOLINE_ALIGN  4
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.  */
+
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)  \
+{									\
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)),	\
+		  (CXT));						\
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)),	\
+		  (FNADDR));						\
+}
+
+
+/* Addressing modes, and classification of registers for them.  */
+
+/*#define HAVE_POST_INCREMENT  1*/
+/*#define HAVE_PRE_INCREMENT   1*/
+/*#define HAVE_POST_DECREMENT  1*/
+/*#define HAVE_PRE_DECREMENT   1*/
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.
+
+*/
+#define REGNO_OK_FOR_BASE_P(REGNO)  \
+  ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
+
+#define REGNO_OK_FOR_INDEX_P(REGNO)   ((REGNO)==0)
+
+/* Maximum number of registers that can appear in a valid memory 
+   address. */
+
+#define MAX_REGS_PER_ADDRESS 1
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X) 	\
+  (GET_CODE (X) == LABEL_REF)
+#if 0
+
+   || GET_CODE (X) == SYMBOL_REF	\
+   || GET_CODE (X) == CONST_INT 	\
+   || GET_CODE (X) == CONST)
+
+#endif
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+
+   On the SH, allow any thing but a double */
+
+#define LEGITIMATE_CONSTANT_P(X) \
+  (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.  */
+
+#ifndef REG_OK_STRICT
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) \
+  (REGNO(X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) \
+    (REGNO(X)==0||REGNO(X)>=FIRST_PSEUDO_REGISTER)
+#define REG_OK_FOR_PRE_POST_P(X) (REGNO(X) <= 16)
+#else
+
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X)  REGNO_OK_FOR_BASE_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X)  REGNO_OK_FOR_INDEX_P (REGNO (X))
+#define REG_OK_FOR_PRE_POST_P(X)  \
+	 (REGNO (X) <= 16 || (unsigned) reg_renumber[REGNO (X)] <=16)
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
+#define BASE_REGISTER_RTX_P(X)  \
+  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
+
+#define INDEX_REGISTER_RTX_P(X)  \
+  (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
+
+
+/* Jump to LABEL if X is a valid address RTX.  This must also take
+   REG_OK_STRICT into account when deciding about valid registers, but it uses
+   the above macros so we are in luck.  
+ 
+   Allow  REG
+	  REG+disp
+	  REG+r0
+	  REG++
+	  --REG
+*/
+
+/* A legitimate index for a QI or HI is 0, SI and above can be any 
+   number 0..64 */
+
+#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL)  \
+  do {							\
+    if (GET_CODE (OP) == CONST_INT) 			\
+      {							\
+	if (GET_MODE_SIZE (MODE) < 4 && INTVAL(OP) == 0)\
+	  goto LABEL;					\
+	if (GET_MODE_SIZE (MODE) >=4 			\
+	    && ((unsigned)INTVAL(OP)) < 64)		\
+	  goto LABEL;					\
+      }							\
+  } while(0)
+
+
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
+{									\
+  if (BASE_REGISTER_RTX_P (X))						\
+    goto LABEL;								\
+  else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC)	\
+	   && GET_CODE (XEXP (X, 0)) == REG				\
+	   && REG_OK_FOR_PRE_POST_P (XEXP (X, 0)))			\
+    goto LABEL;								\
+  else if (GET_CODE (X) == PLUS)					\
+    {									\
+      rtx xop0 = XEXP(X,0);						\
+      rtx xop1 = XEXP(X,1);						\
+      if (BASE_REGISTER_RTX_P (xop0))					\
+	GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL);	\
+      else if (BASE_REGISTER_RTX_P (xop1))				\
+	GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL);	\
+    }									\
+  else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC)	\
+	   && GET_CODE (XEXP (X, 0)) == REG				\
+	   && REG_OK_FOR_PRE_POST_P (XEXP (X, 0)))			\
+    goto LABEL;								\
+}
+
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   On the SH we don't try anything */
+
+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)  ;
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.  */
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  \
+{									\
+  if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC		\
+      || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC)	\
+    goto LABEL;								\
+}
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE SImode
+
+/* Define this if the tablejump instruction expects the table
+   to contain offsets from the address of the table.
+   Do not define this if the table should contain absolute addresses.  */
+/* #define CASE_VECTOR_PC_RELATIVE */
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR  FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR  TRUNC_DIV_EXPR
+
+/* 'char' is signed by default */
+#define DEFAULT_SIGNED_CHAR  1
+
+/* The type of size_t unsigned int.  */
+#define SIZE_TYPE "unsigned int"
+
+/* Don't cse the address of the function being compiled.  */
+#define NO_RECURSIVE_FUNCTION_CSE 1
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Define if normal loads of shorter-than-word items from sign extends
+   the rest of the bigs in the register. */
+#define BYTE_LOADS_SIGN_EXTEND  1
+
+/* Define this if zero-extension is slow (more than one real instruction).
+   On the SH, it's only one instruction */
+/* #define SLOW_ZERO_EXTEND */
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 0
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true.  */
+
+#define STORE_FLAG_VALUE 1
+
+/* Immediate shift counts are truncated by the output routines (or was it
+   the assembler?).  Shift counts in a register are truncated by ARM.  Note
+   that the native compiler puts too large (> 32) immediate shift counts
+   into a register and shifts by the register, letting the ARM decide what
+   to do instead of doing that itself.  */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* We have the vprintf function.  */
+#define HAVE_VPRINTF 1
+
+/* All integers have the same format so truncation is easy.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC)  1
+
+/* Define this if addresses of constant functions
+   shouldn't be put through pseudo regs where they can be cse'd.
+   Desirable on machines where ordinary constants are expensive
+   but a CALL with constant address is cheap.  */
+/*#define NO_FUNCTION_CSE 1*/
+
+/* Chars and shorts should be passed as ints.  */
+#define PROMOTE_PROTOTYPES 1
+
+/* The machine modes of pointers and functions */
+#define Pmode  SImode
+#define FUNCTION_MODE  Pmode
+
+/* The structure type of the machine dependent info field of insns
+   No uses for this yet.  */
+/* #define INSN_MACHINE_INFO  struct machine_info  */
+
+/* The relative costs of various types of constants.  Note that cse.c defines
+   REG = 1, SUBREG = 2, any node = (2 + sum of subnodes).  */
+
+#define CONST_COSTS(RTX, CODE, OUTER_CODE)      \
+  case CONST_INT:				\
+    if (CONST_OK_FOR_I (INTVAL(RTX)))           \
+      return 1;					\
+    else					\
+      return 5;					\
+  case CONST: 					\
+  case LABEL_REF:				\
+  case SYMBOL_REF:				\
+    return 6;					\
+  case CONST_DOUBLE:				\
+      return 10;
+
+#define RTX_COSTS(X, CODE, OUTER_CODE)			\
+  case MULT:						\
+    return COSTS_N_INSNS (TARGET_HAS_MULSI3 ? 2 : 20); 	\
+  case DIV:						\
+  case UDIV:						\
+  case MOD:						\
+  case UMOD:						\
+    return COSTS_N_INSNS (100);				\
+  case FLOAT:						\
+  case FIX:						\
+    return 100;
+
+/* Compute extra cost of moving data between one register class
+   and another.  
+
+   On the SH it is hard to move into the T reg, but simple to load
+   from it.
+*/
+
+#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS)  \
+    ((DSTCLASS ==T_REGS) ? 10 : 2)
+
+/* Assembler output control */
+
+/* The text to go at the start of the assembler file */
+#define ASM_FILE_START(STREAM) \
+  fprintf (STREAM,"! GCC for the Hitachi Super-H\n");  	\
+  output_file_directive (STREAM, main_input_filename);
+
+#define ASM_APP_ON  ""
+#define ASM_APP_OFF  ""
+
+#define FILE_ASM_OP "\t.file\n"
+#define IDENT_ASM_OP "\t.ident\n"
+
+
+/* Switch to the text or data segment.  */
+#define TEXT_SECTION_ASM_OP  ".text"
+#define DATA_SECTION_ASM_OP  ".data"
+
+/* The assembler's names for the registers.  RFP need not always be used as
+   the Real framepointer; it can also be used as a normal general register.
+   Note that the name `fp' is horribly misleading since `fp' is in fact only
+   the argument-and-return-context pointer.  */
+#define REGISTER_NAMES  				\
+{				                   	\
+  "r0", "r1", "r2",  "r3",  "r4",  "r5",  "r6",  "r7", 	\
+  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",	\
+  "ap", "pr", "t",  "gbr", "mach","macl" 		\
+}
+
+/* DBX register number for a given compiler register number */
+#define DBX_REGISTER_NUMBER(REGNO)  (REGNO)
+
+/* Output a label definition.  */
+#define ASM_OUTPUT_LABEL(FILE,NAME)  \
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %d\n", LOG)
+
+/* Output a function label definition.  */
+#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
+    ASM_OUTPUT_LABEL(STREAM, NAME)
+
+/* Output a globalising directive for a label.  */
+#define ASM_GLOBALIZE_LABEL(STREAM,NAME)  \
+  (fprintf (STREAM, "\t.global\t"),	  \
+   assemble_name (STREAM, NAME),	  \
+   fputc ('\n',STREAM))                   \
+
+/* Output a reference to a label.  */
+#define ASM_OUTPUT_LABELREF(STREAM,NAME)  \
+  fprintf (STREAM, "_%s", NAME)
+
+/* Make an internal label into a string.  */
+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM)  \
+  sprintf (STRING, "*%s%d", PREFIX, NUM)
+
+/* Output an internal label definition.  */
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* Nothing special is done about jump tables */
+/* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE)   */
+/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE)	    */
+
+/* Construct a private name.  */
+#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER)  \
+  ((OUTVAR) = (char *) alloca (strlen (NAME) + 10),  \
+   sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
+
+/* Output a relative address. Not needed since jump tables are absolute
+   but we must define it anyway.  */
+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL)  \
+  fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
+
+/* Output an element of a dispatch table.  */
+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE)  \
+    fprintf (STREAM, "\t.long\tL%d\n", VALUE)
+
+/* Output various types of constants.  */
+
+
+/* This is how to output an assembler line defining a `double' */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
+      {									\
+	long t[2];							\
+	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
+	fprintf (FILE, "\t.long\t0x%lx\n\t.long\t0x%lx\n",		\
+		  t[0], t[1]);						\
+      }									\
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
+  {									\
+	long t;								\
+	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
+	fprintf (FILE, "\t.long\t0x%lx\n", t);				\
+  }									\
+
+#define ASM_OUTPUT_INT(STREAM, EXP)  	\
+  (fprintf (STREAM, "\t.long\t"),      	\
+   output_addr_const (STREAM, (EXP)),  	\
+   fputc ('\n', STREAM))		
+
+#define ASM_OUTPUT_SHORT(STREAM, EXP)  \
+  (fprintf (STREAM, "\t.short\t"),     \
+   output_addr_const (STREAM, (EXP)),  \
+   fputc ('\n', STREAM))		
+
+#define ASM_OUTPUT_CHAR(STREAM, EXP)  	\
+  (fprintf (STREAM, "\t.byte\t"),      	\
+   output_addr_const (STREAM, (EXP)),  	\
+   fputc ('\n', STREAM))
+
+#define ASM_OUTPUT_BYTE(STREAM, VALUE)  	\
+  fprintf (STREAM, "\t.byte\t%d\n", VALUE)  	\
+
+/* This is how to output an assembler line
+   that says to advance the location counter by SIZE bytes.  */
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t.space %d\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( fputs ("\t.comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
+( fputs ("\t.lcomm ", (FILE)),				\
+  assemble_name ((FILE), (NAME)),			\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+
+/* The assembler's parentheses characters.  */
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Target characters.  */
+#define TARGET_BELL	007
+#define TARGET_BS	010
+#define TARGET_TAB	011
+#define TARGET_NEWLINE	012
+#define TARGET_VT	013
+#define TARGET_FF	014
+#define TARGET_CR	015
+
+
+/* Only perform branch elimination (by making instructions conditional) if
+   we're optimising.  Otherwise it's of no use anyway.  */
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)  \
+    final_prescan_insn (INSN, OPVEC, NOPERANDS)
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
+
+#define PRINT_OPERAND(STREAM, X, CODE)  print_operand (STREAM, X, CODE)
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+#define PRINT_OPERAND_ADDRESS(STREAM,X)  print_operand_address (STREAM, X)
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
+  ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!')
+
+
+/* Define the information needed to generate branch insns.  This is stored
+   from the compare operation.  Note that we can't use "rtx" here since it
+   hasn't been defined!  */
+
+extern struct rtx_def *sh_compare_op0;
+extern struct rtx_def *sh_compare_op1;
+extern struct rtx_def *prepare_scc_operands();
+
+
+
+/* Declare functions defined in sh.c and used in templates. */
+
+extern char *output_branch();
+extern char *output_shift();
+extern char *output_movedouble();
+extern char *output_movepcrel();
+
+
+#define ADJUST_INSN_LENGTH(insn, length) \
+  adjust_insn_length (insn, insn_lengths)

gcc/config/sh/sh.md

+;;- Machine description the Hitachi SH
+;;  Copyright (C) 1993 Free Software Foundation, Inc.
+;;  Contributed by Steve Chamberlain (sac@cygnus.com)
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+
+
+;; -------------------------------------------------------------------------
+;; Attributes
+;; -------------------------------------------------------------------------
+
+(define_attr "type" "cbranch,ctable,jump,arith,other"
+  (const_string "other"))
+
+; If a conditional branch destination is within -100..100 bytes away 
+; from the instruction it can be 2 bytes long.  Something in the
+; range -4000..4000 bytes can be 6 bytes long, all other conditional
+; branches are 8 bytes long.
+
+; An unconditional jump which can reach forward or back 4k can be 
+; 6 bytes long (including the delay slot).  If it is too big, it
+; must be 8 bytes long.
+
+; All other instructions are two bytes long by default.
+
+(define_attr "length" "" 
+  (cond [(eq_attr "type" "cbranch")
+	  (if_then_else (and (ge (minus (pc) (match_dup 0))
+				 (const_int -100))
+			     (le (minus (pc) (match_dup 0))
+				 (const_int 100)))
+			(const_int 2)
+			(if_then_else (and (ge (minus (pc) (match_dup 0))
+					       (const_int -4000))
+					   (le (minus (pc) (match_dup 0))
+					       (const_int 4000)))
+				      (const_int 6)
+				      (const_int 8)))
+
+	 (eq_attr "type" "jump")
+			(if_then_else (and (ge (minus (pc) (match_dup 0))
+					       (const_int -4000))
+					   (le (minus (pc) (match_dup 0))
+					       (const_int 4000)))
+				      (const_int 4)
+				      (const_int 6))
+	 ] (const_int 2)))
+				      
+
+(define_attr "needs_delay_slot" "yes,no"
+  (cond [(eq_attr "type" "jump") (const_string "yes")]
+	(const_string "no")))
+
+(define_attr "dump" "yes,no,must" (const_string "no"))
+(define_attr "constneed" "yes,no" (const_string "no"))
+(define_attr "smallestsize" "" (const_int 2))
+(define_attr "largestsize" "" (const_int 8))
+(define_attr "constantsize" "" (const_int 4))
+
+(define_attr "in_delay_slot" "maybe,yes,no" 
+  (cond [(eq_attr "type" "cbranch") (const_string "no")
+	 (eq_attr "type" "jump") (const_string "no")
+	 (eq_attr "length" "2") (const_string "yes")
+	 (eq_attr "length" "4,6,8,10,12") (const_string "no")
+	 ] (const_string "yes")))
+
+
+(define_delay (eq_attr "needs_delay_slot" "yes")
+  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
+
+
+
+;; -------------------------------------------------------------------------
+;; SImode signed integer comparisons
+;; -------------------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(eq:SI (reg:SI 18)
+	       (const_int 1)))]
+  ""
+  "movt	%0 !movt1")
+  
+(define_insn ""
+  [(set (reg:SI 18) (gt (match_operand:SI 0 "register_operand" "r")
+		  (const_int 0)))]
+  ""
+  "cmp/pl	%0")
+
+(define_insn ""
+  [(set (reg:SI 18) (ge (match_operand:SI 0 "register_operand" "r")
+		  (const_int 0)))]
+  ""
+  "cmp/pz	%0")
+
+(define_insn "cmpeqsi_t"
+  [(set (reg:SI 18) (eq (match_operand:SI 0 "register_operand" "r,z")
+		  (match_operand:SI 1 "arith_operand" "r,I")))]
+  ""
+  "cmp/eq	%1,%0")
+
+
+(define_insn "cmpgtsi_t"
+  [(set (reg:SI 18) (gt (match_operand:SI 0 "register_operand" "r")
+		  (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/gt	%1,%0")
+
+(define_insn "cmpgesi_t"
+  [(set (reg:SI 18) (ge (match_operand:SI 0 "register_operand" "r")
+		  (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/ge	%1,%0")
+
+(define_insn "cmpltsi_t"
+  [(set (reg:SI 18) (lt (match_operand:SI 0 "register_operand" "r")
+		  (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/gt	%0,%1")
+
+(define_insn "cmplesi_t"
+  [(set (reg:SI 18) (le (match_operand:SI 0 "register_operand" "r")
+		  (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/ge	%0,%1")
+
+
+;; -------------------------------------------------------------------------
+;; SImode unsigned integer comparisons
+;; -------------------------------------------------------------------------
+
+(define_insn "cmpgeusi_t"
+  [(set (reg:SI 18) (geu (match_operand:SI 0 "register_operand" "r")
+		   (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/hs	%1,%0")
+
+(define_insn "cmpgtusi_t"
+  [(set (reg:SI 18) (gtu (match_operand:SI 0 "register_operand" "r")
+		   (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/hi	%1,%0")
+
+(define_insn "cmpleusi_t"
+  [(set (reg:SI 18) (leu (match_operand:SI 0 "register_operand" "r")
+		   (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/hs	%0,%1")
+
+(define_insn "cmpltusi_t"
+  [(set (reg:SI 18) (ltu (match_operand:SI 0 "register_operand" "r")
+		   (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "cmp/hi	%0,%1")
+
+;; We save the compare operands in the cmpxx patterns and use them when
+;; we generate the branch.
+
+(define_expand "cmpsi"
+  [(set (reg:SI 18) (compare (match_operand:SI 0 "register_operand" "")
+			     (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "
+{ sh_compare_op0 = operands[0];
+  sh_compare_op1 = operands[1];
+  DONE;
+}")
+
+
+;; -------------------------------------------------------------------------
+;; Addition instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "adddi3"
+  [(set (match_operand:DI 0 "register_operand" "=&r")
+	(plus:DI (match_operand:DI 1 "register_operand" "%0")
+		 (match_operand:DI 2 "register_operand" "r")))
+   (clobber (reg:SI 18))]
+  ""
+  "clrt\;addc	%R2,%R0\;addc	%2,%0"
+  [(set_attr "length" "6")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "type" "arith")])
+
+
+(define_insn "addsi3_i"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "arith_operand" "rI")))]
+  ""
+  "add	%2,%0"
+  [(set_attr "length" "2")
+   (set_attr "type" "arith")])
+
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "arith_operand" "rI")))]
+  ""
+  "")
+
+
+;; -------------------------------------------------------------------------
+;; Subtraction instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "register_operand" "=&r")
+	(minus:DI (match_operand:DI 1 "register_operand" "0")
+		  (match_operand:DI 2 "register_operand" "r")))
+   (clobber (reg:SI 18))]
+  ""
+  "clrt\;subc	%R2,%R0\;subc	%2,%0"
+  [(set_attr "length" "6")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "type" "arith")])
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(minus:SI (match_operand:SI 1 "register_operand" "0")
+		  (match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "sub	%2,%0"
+  [(set_attr "type" "arith")])
+
+
+;; -------------------------------------------------------------------------
+;; Multiplication instructions
+;; -------------------------------------------------------------------------
+
+
+(define_insn ""
+  [(set (reg:SI 21)
+	(mult:SI (zero_extend:SI
+		  (match_operand:HI 1 "register_operand" "r"))
+		 (zero_extend:SI
+		  (match_operand:HI 2 "register_operand" "r"))))]
+  ""
+  "mulu	%2,%1")
+
+(define_insn ""
+  [(set (reg:SI 21)
+	(mult:SI (sign_extend:SI
+		  (match_operand:HI 1 "register_operand" "r"))
+		 (sign_extend:SI
+		  (match_operand:HI 2 "register_operand" "r"))))]
+  ""
+  "muls	%2,%1")
+
+(define_expand "mulhisi3"
+  [(set (reg:SI 21)
+	(mult:SI (sign_extend:SI
+		  (match_operand:HI 1 "register_operand" "r"))
+		 (sign_extend:SI
+		  (match_operand:HI 2 "register_operand" "r"))))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(reg:SI 21))]
+  ""
+  "")
+
+(define_expand "umulhisi3"
+  [(set (reg:SI 21)
+	(mult:SI (zero_extend:SI
+		  (match_operand:HI 1 "register_operand" "r"))
+		 (zero_extend:SI
+		  (match_operand:HI 2 "register_operand" "r"))))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(reg:SI 21))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (reg:SI 21)
+	(mult:SI (match_operand:SI 1 "register_operand" "r")
+		  (match_operand:SI 2 "register_operand" "r")))]
+  "TARGET_HAS_MULSI3"
+  "muls.l	%2,%1")
+
+(define_expand "mulsi3"
+  [(set (reg:SI 21)
+	(mult:SI  (match_operand:SI 1 "register_operand" "r")
+		  (match_operand:SI 2 "register_operand" "r")))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(reg:SI 20))]
+  "TARGET_HAS_MULSI3"
+  "")
+
+(define_insn ""
+  [(set (reg:DI 20)
+	(mult:DI (sign_extend:DI
+		  (match_operand:SI 1 "register_operand" "r"))
+		 (sign_extend:DI
+		  (match_operand:SI 2 "register_operand" "r"))))]
+  "TARGET_HAS_MULSI3"
+  "dmuls.l	%2,%1")
+
+(define_expand "mulsidi3"
+  [(set (reg:DI 20)
+	(mult:DI (sign_extend:DI
+		  (match_operand:SI 1 "register_operand" "r"))
+		 (sign_extend:DI
+		  (match_operand:SI 2 "register_operand" "r"))))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(reg:DI 20))]
+  "TARGET_HAS_MULSI3"
+  "")
+
+(define_insn ""
+  [(set (reg:DI 20)
+	(mult:DI (zero_extend:DI
+		  (match_operand:SI 1 "register_operand" "r"))
+		 (zero_extend:DI
+		  (match_operand:SI 2 "register_operand" "r"))))]
+  "TARGET_HAS_MULSI3"
+  "dmulu.l	%2,%1")
+
+(define_expand "umulsidi3"
+  [(set (reg:DI 20)
+	(mult:DI (zero_extend:DI
+		  (match_operand:SI 1 "register_operand" "r"))
+		 (zero_extend:DI
+		  (match_operand:SI 2 "register_operand" "r"))))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(reg:DI 20))]
+  "TARGET_HAS_MULSI3"
+  "")
+
+;; -------------------------------------------------------------------------
+;; Logical operations
+;; -------------------------------------------------------------------------
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,z")
+	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
+		(match_operand:SI 2 "logical_operand" "r,L")))]
+  ""
+  "and	%2,%0"
+  [(set_attr "type" "arith")])
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,z")
+	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
+		(match_operand:SI 2 "logical_operand" "r,L")))]
+  ""
+  "or	%2,%0")
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,z")
+	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
+		(match_operand:SI 2 "logical_operand" "r,L")))]
+  ""
+  "xor	%2,%0"
+  [(set_attr "type" "arith")])
+
+
+;; -------------------------------------------------------------------------
+;; Shifts and rotates
+;; -------------------------------------------------------------------------
+
+(define_insn "ashlsi3_k"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
+		   (match_operand:SI 2 "immediate_operand" "L,n")))]
+  ""
+  "*return output_shift(\"shll\", operands[0], operands[2]);"
+  [(set_attr "length" "2,12")
+   (set_attr "in_delay_slot" "yes,no")
+   (set_attr "type" "arith")])
+
+(define_expand "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashift:SI (match_operand:SI 1 "register_operand" "")
+		   (match_operand:SI 2 "immediate_operand" "")))]
+  ""
+  "if (!ok_shift_value(operands[2])) FAIL;")
+
+(define_insn "ashrsi3_k"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+		     (const_int 1)))]
+  ""
+  "shar	%0"
+  [(set_attr "type" "arith")])
+
+(define_expand "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+		     (match_operand:SI 2 "nonmemory_operand" "M")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT ||
+      INTVAL (operands[2]) != 1) FAIL;
+}
+")
+
+(define_insn "lshrsi3_k"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
+		     (match_operand:SI 2 "immediate_operand" "L")))]
+  ""
+  "* return output_shift (\"shlr\", operands[0], operands[2]);"
+  [(set_attr "length" "12")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "type" "arith")])
+
+(define_expand "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "if (!ok_shift_value (operands[2])) FAIL; ")
+
+(define_insn "ashldi3_k"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashift:DI (match_operand:DI 1 "register_operand" "0")
+		   (match_operand:DI 2 "immediate_operand" "I")))
+   (clobber (reg:SI 18))]
+  ""
+  "shll	%R0\;rotcl	%0"
+  [(set_attr "length" "4")])
+
+(define_expand "ashldi3"
+  [(parallel[(set (match_operand:DI 0 "register_operand" "")
+		  (ashift:DI (match_operand:DI 1 "register_operand" "")
+			     (match_operand:DI 2 "immediate_operand" "")))
+	     (clobber (reg:SI 18))])]
+	    
+  ""
+  "{ if (GET_CODE (operands[2]) != CONST_INT 	
+	|| INTVAL (operands[2]) != 1) FAIL;} ")
+
+(define_insn "lshrdi3_k"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+		   (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
+			      (match_operand:DI 2 "immediate_operand" "I")))
+      (clobber (reg:SI 18))]
+  ""
+  "shlr	%0\;rotcr	%R0"
+  [(set_attr "length" "4")])
+
+(define_expand "lshrdi3"
+  [(parallel[(set (match_operand:DI 0 "register_operand" "")
+		  (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+			       (match_operand:DI 2 "immediate_operand" "")))
+	     (clobber (reg:SI 18))])]
+  ""
+  "{ if (GET_CODE (operands[2]) != CONST_INT 
+	|| INTVAL (operands[2]) != 1) FAIL;} ")
+
+(define_insn "ashrdi3_k"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
+		     (match_operand:DI 2 "immediate_operand" "")))
+   (clobber (reg:SI 18))]
+  ""
+  "shar	%0\;rotcr	%R0"
+  [(set_attr "length" "4")])
+
+(define_expand "ashrdi3"
+  [(parallel[(set (match_operand:DI 0 "register_operand" "")
+		  (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+			       (match_operand:DI 2 "immediate_operand" "")))
+	     (clobber (reg:SI 18))])]
+  ""
+  "{ if (GET_CODE (operands[2]) != CONST_INT 
+	|| INTVAL (operands[2]) != 1) FAIL; } ")
+
+
+
+;; -------------------------------------------------------------------------
+;; Unary arithmetic
+;; -------------------------------------------------------------------------
+
+(define_insn "negdi2"
+  [(set (match_operand:DI 0 "register_operand" "=&r")
+	(neg:DI (match_operand:DI 1 "register_operand" "0")))
+   (clobber (reg:SI 18))]
+  ""
+  "clrt\;negc	%R1,%R0\;negc	%1,%0"
+  [(set_attr "length" "6")
+   (set_attr "type" "arith")])
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "neg	%1,%0"
+  [(set_attr "type" "arith")])
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "not	%1,%0"
+[  (set_attr "type" "arith")])
+
+
+;; -------------------------------------------------------------------------
+;; Zero extension instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
+  ""
+  "extu.w	%1,%0"
+  [(set_attr "type" "arith")])
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
+  ""
+  "extu.b	%1,%0"
+  [(set_attr "type" "arith")]) 
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
+  ""
+  "extu.b	%1,%0"
+  [(set_attr "type" "arith")]) 
+
+
+;; -------------------------------------------------------------------------
+;; Sign extension instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (match_operand:SI 1 "register_operand" "0")))]
+  ""
+  "mov	%1,%0\;shll	%0\;subc	%0,%0"
+  [(set_attr "length" "6")]) 
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
+  ""
+  "exts.w	%1,%0")
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
+  ""
+  "exts.b	%1,%0")
+
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
+  ""
+  "exts.b	%1,%0")
+
+
+;; -------------------------------------------------------------------------
+;; Move instructions
+;; -------------------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:SI 0 "push_operand" "=<")
+	(match_operand:SI 1 "register_operand" "r"))]
+   ""
+   "mov.l	%1,%0")
+
+(define_insn "movsi_pcrel"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operand:SI 1 "hard_immediate_operand" "i"))]
+  ""
+  "* return output_movepcrel (insn, operands, SImode);"
+  [(set_attr "length" "2")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "constneed" "yes")
+   (set_attr "smallestsize" "2")
+   (set_attr "largestsize" "8")])
+		
+(define_insn "movsi_i"
+  [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,l,r,r,r,t")
+	(match_operand:SI 1 "general_operand"  "r,I,m,r,r,l,t,x,r"))]
+  ""
+  "@
+	mov	%1,%0
+	mov	%1,%0
+	mov.l	%1,%0
+	mov.l	%1,%0
+	mov	%1,%0
+	mov	%1,%0
+        movt	%0
+	sts	%1,%0
+	tst	%1,%1\;bt	T%*\;bra	F%*\;sett\;T%*:clrt\;F%*:%^"
+	[(set_attr "length" "2,2,2,2,2,2,2,2,10")])
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "{ prepare_move_operands(operands, SImode); } ")
+
+(define_insn "movqi_i"
+  [(set (match_operand:QI 0 "general_operand" "=r,r,z,m,r,m,r,r")
+	(match_operand:QI 1 "general_operand"  "r,n,m,z,m,r,x,t"))]
+  ""
+  "@
+	mov	%1,%0
+	mov	%1,%0
+	mov.b	%1,%0 !4
+	mov.b	%1,%0 !5
+	mov.b	%1,%0 !6
+	mov.b	%1,%0 ! 7
+	sts	%1,%0
+	movt	%0")
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand"  ""))]
+  ""
+  "prepare_move_operands(operands, QImode);")
+  
+(define_insn "movhi_pcrel"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(match_operand:HI 1 "hard_immediate_operand" "i"))]
+  ""
+  "* return output_movepcrel (insn, operands, SImode);"
+  [(set_attr "length" "2")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "constneed" "yes")
+   (set_attr "smallestsize" "2")
+   (set_attr "largestsize" "8")])
+
+(define_insn "movhi_i"
+  [(set (match_operand:HI 0 "general_operand" "=r,r,m,z,m,r,r")
+	(match_operand:HI 1 "general_operand"  "rI,m,r,m,z,x,t"))]
+  ""
+  "@
+	mov	%1,%0
+	mov.w	%1,%0
+	mov.w	%1,%0
+	mov.w	%1,%0
+	mov.w	%1,%0
+	sts	%1,%0
+	movt	%0")
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand"  ""))]
+  ""
+  "prepare_move_operands (operands, HImode);")
+  
+(define_insn ""
+  [(set (match_operand:DI 0 "push_operand" "=<")
+	(match_operand:DI 1 "register_operand" "r"))]
+   ""
+   "mov.l	%R1,%0\;mov.l	%1,%0"
+   [(set_attr "length" "4")])
+
+(define_insn "movdi_pcrel"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(match_operand:DI 1 "hard_immediate_operand" "i"))]
+  ""
+  "* return output_movepcrel (insn, operands, DImode);"
+  [(set_attr "length" "4")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "constneed" "yes")
+   (set_attr "smallestsize" "4")
+   (set_attr "constantsize" "8")
+   (set_attr "largestsize" "18")])
+
+(define_insn "movdi_k"
+  [(set (match_operand:DI 0 "general_operand" "=r,r,m,r,r,m,r")
+	(match_operand:DI 1 "general_operand" "r,m,r,I,m,r,x"))]
+  ""
+  "* return output_movedouble(operands, DImode);"
+  [(set_attr "length" "4")])
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "general_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  ""
+  "prepare_move_operands (operands, DImode);")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "push_operand" "=<")
+	(match_operand:DF 1 "register_operand" "r"))]
+   ""
+   "mov.l	%R1,%0\;mov.l	%1,%0"
+   [(set_attr "length" "4")])
+
+(define_insn "movdf_pcrel"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(match_operand:DF 1 "hard_immediate_operand" "i"))]
+  ""
+  "* return output_movepcrel  (insn, operands, DFmode);"
+  [(set_attr "length" "4")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "constneed" "yes")
+   (set_attr "smallestsize" "4")
+   (set_attr "constantsize" "8")
+   (set_attr "largestsize" "18")])
+
+(define_insn "movdf_k"
+  [(set (match_operand:DF 0 "general_operand" "=r,r,m")
+	(match_operand:DF 1 "general_operand" "r,m,r"))]
+  ""
+  "* return output_movedouble(operands, DFmode);"
+  [(set_attr "length" "4")])
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "general_operand" "")
+	(match_operand:DF 1 "general_operand" ""))]
+  ""
+  "prepare_move_operands(operands, DFmode);")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "push_operand" "=<")
+	(match_operand:SF 1 "register_operand" "r"))]
+   ""
+   "mov.l	%1,%0")
+
+(define_insn "movsf_pcrel"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(match_operand:SF 1 "hard_immediate_operand" "i"))]
+  ""
+  "* return output_movepcrel (insn, operands, SFmode);"
+  [(set_attr "length" "2")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "constneed" "yes")
+   (set_attr "smallestsize" "2")
+   (set_attr "largestsize" "8")])
+		
+(define_insn "movsf_i"
+  [(set (match_operand:SF 0 "general_operand" "=r,r,r,m,l,r,m,r")
+	(match_operand:SF 1 "general_operand"  "r,I,m,r,r,l,r,m"))]
+  ""
+  "@
+	mov	%1,%0
+	mov	%1,%0
+	mov.l	%1,%0
+	mov.l	%1,%0
+	mov	%1,%0
+	mov	%1,%0
+	mov	%1,%0
+	mov	%1,%0")
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+	(match_operand:SF 1 "general_operand" ""))]
+  ""
+  "prepare_move_operands(operands, SFmode);")
+
+
+;; ------------------------------------------------------------------------
+;; Define the real conditional branch instructions.
+;; ------------------------------------------------------------------------
+
+(define_insn "branch_true"
+  [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
+			   (label_ref (match_operand 0 "" ""))
+			   (pc)))]
+  ""
+  "* return output_branch (1, insn);"
+  [(set_attr "type" "cbranch")])
+
+(define_insn "branch_false"
+  [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
+			   (label_ref (match_operand 0 "" ""))
+			   (pc)))]
+  ""
+  "* return output_branch (0, insn);"
+  [(set_attr "type" "cbranch")])
+
+(define_insn "inverse_branch_true"
+  [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
+			   (pc)
+			   (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_branch (0, insn);"
+  [(set_attr "type" "cbranch")])
+
+(define_insn "inverse_branch_false"
+  [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
+   			   (pc)
+			   (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_branch (1, insn);"
+  [(set_attr "type" "cbranch")])
+
+
+;; Conditional branch insns
+
+(define_expand "beq"
+  [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+
+; There is no bne compare, so we reverse the branch arms.
+
+(define_expand "bne"
+  [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "bgt"
+  [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "blt"
+  [(set (reg:SI 18) (lt:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "ble"
+  [(set (reg:SI 18) (le:SI (match_dup 1) (match_dup 2)))
+   (set (pc)				
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "bge"
+  [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "bgtu"
+  [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			   (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "bltu"
+  [(set (reg:SI 18) (ltu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			   (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "bgeu"
+  [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			   (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+(define_expand "bleu"
+  [(set (reg:SI 18) (leu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			   (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}")
+
+
+;; ------------------------------------------------------------------------
+;; Jump and linkage insns
+;; ------------------------------------------------------------------------
+
+(define_insn "jump_real"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "*
+{
+  if (get_attr_length(insn) == 6) 
+    {
+      return \"mov.l	%I0,r13\;jmp	@r13%#\";
+    }
+  else
+    {
+      return   \"bra	%l0%#\";
+    }
+}"
+  [(set_attr "type" "jump")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "jump"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ ""
+ "
+{
+  emit_insn(gen_jump_real(operand0));
+  DONE;
+}
+")
+
+(define_insn "calli"
+  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
+	 (match_operand 1 "" ""))
+   (clobber (reg:SI 17))]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "needs_delay_slot" "yes")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "length" "4")])
+
+(define_insn "call_valuei"
+  [(set (match_operand 0 "" "=rf")
+	(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	      (match_operand 2 "" "")))
+   (clobber (reg:SI 17))]
+  ""
+  "jsr	@%1%#"
+  [(set_attr "needs_delay_slot" "yes")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "length" "4")])
+
+(define_expand "call"
+  [(parallel[(call (match_operand 0 "register_operand" "o")
+		   (match_operand 1 "" ""))
+	     (clobber (reg:SI 17))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM) 
+    {
+      operands[0] 
+	= gen_rtx(MEM,GET_MODE (operands[0]),
+		  force_reg (Pmode,
+			    XEXP (operands[0], 0)));
+    }
+}")
+
+(define_expand "call_value"
+  [(parallel[(set (match_operand 0 "" "=rf")
+		  (call (match_operand 1 "register_operand" "o")
+			(match_operand 2 "" "")))
+	     (clobber (reg:SI 17))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) == MEM) 
+    {
+      operands[1] 
+	= gen_rtx (MEM, GET_MODE (operands[1]),
+		   force_reg (Pmode,
+			      XEXP (operands[1], 0)));
+    }
+}")
+
+(define_insn "indirect_jump"
+  [(set (pc)
+	(match_operand:SI 0 "register_operand" "r"))]
+  ""
+  "jmp	@%0"
+  [(set_attr "needs_delay_slot" "yes")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "length" "4")])
+
+
+
+;; ------------------------------------------------------------------------
+;; Misc insns
+;; ------------------------------------------------------------------------
+
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "or	r0,r0")
+
+(define_insn "tablejump"
+  [(set (pc)
+	(match_operand:SI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "!table jump\;jmp	@%0\;or	r0,r0\;.align	4\;%!"
+  [(set_attr "needs_delay_slot" "no")
+   (set_attr "in_delay_slot" "no")
+   (set_attr "type" "jump")
+   (set_attr "dump" "no")])
+
+;; ------------------------------------------------------------------------
+;; Scc instructions
+;; ------------------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(eq (reg:SI 18) (const_int 1)))]
+  ""
+  "movt	%0 ! ")
+
+(define_expand "seq"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (EQ);")
+
+(define_expand "slt"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LT);")
+
+(define_expand "sle"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LE);")
+
+(define_expand "sgt"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GT);")
+
+(define_expand "sge"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GE);")
+
+(define_expand "sgtu"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GTU);")
+
+(define_expand "sltu"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LTU);")
+
+(define_expand "sleu"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LEU);")
+
+(define_expand "sgeu"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GEU);")
+
+(define_expand "sne"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_dup 1))
+   (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))]
+  ""
+  "operands[1] = prepare_scc_operands (EQ);")
+
+(define_insn "anddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI (match_operand:DI 1 "register_operand" "%0")
+		(match_operand:DI 2 "register_operand" "r")))]
+  ""
+  "and	%2,%0\;and	%R2,%R0"
+  [(set_attr "length" "4")])
+
+(define_insn "iordi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ior:DI (match_operand:DI 1 "register_operand" "%0")
+		(match_operand:DI 2 "register_operand" "r")))]
+  ""
+  "or	%2,%0\;or	%R2,%R0"
+  [(set_attr "length" "4")])
+
+(define_insn "xordi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(xor:DI (match_operand:DI 1 "register_operand" "%0")
+		(match_operand:DI 2 "register_operand" "r")))]
+  ""
+  "xor	%2,%0\;xor	%R2,%R0"
+  [(set_attr "length" "4")])
+
+
+;; ------------------------------------------------------------------------
+;; Block move
+;; ------------------------------------------------------------------------
+
+(define_expand "movstrsi"
+  [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
+		   (mem:BLK (match_operand:BLK 1 "general_operand" "")))
+	     (use (match_operand:SI 2 "general_operand" ""))
+	     (use (match_operand:SI 3 "immediate_operand" ""))
+  ])]
+  ""
+  "
+{
+  rtx src_ptr = copy_to_mode_reg(Pmode,XEXP(operands[1], 0));
+  rtx dst_ptr = copy_to_mode_reg(Pmode,XEXP(operands[0], 0));
+
+  enum machine_mode mode = 
+     (INTVAL(operands[3]) >=4)  ? SImode :
+       (INTVAL(operands[3]) >=2) ? HImode :
+	 QImode;
+
+  rtx tmpreg = gen_reg_rtx(mode);
+  rtx increment =  GEN_INT(GET_MODE_SIZE(mode));
+  rtx length = operands[2];
+  rtx label = gen_label_rtx();
+  rtx end_src_ptr = gen_reg_rtx(Pmode);
+
+  /* If done first rtl emmiting stage we can't generate a loop */
+  /*  if    (!rtx_equal_function_value_matters)
+      FAIL;*/
+  
+  if (GET_CODE (length) != CONST_INT)
+    length = convert_to_mode (Pmode, length, 1);
+
+  if (!arith_operand (length, SImode))
+	length = force_reg (SImode, length);
+	
+  emit_insn(gen_rtx(SET,
+		    VOIDmode, 
+		    end_src_ptr,
+		    gen_rtx(PLUS, Pmode, src_ptr, length)));
+
+
+  emit_label(label);
+  emit_move_insn(tmpreg, gen_rtx(MEM, mode, src_ptr));
+
+
+  emit_insn(gen_rtx(SET,
+		    VOIDmode,
+		    src_ptr,
+		    gen_rtx(PLUS, Pmode, src_ptr, increment)));
+
+  emit_move_insn(gen_rtx(MEM, mode, dst_ptr), tmpreg);
+
+  emit_insn(gen_rtx(SET, 
+		    VOIDmode,
+		    dst_ptr,
+		    gen_rtx(PLUS, Pmode, dst_ptr, increment)));
+
+  sh_compare_op0 = src_ptr;
+  sh_compare_op1 = end_src_ptr;
+  
+  emit_insn(gen_cmpeqsi_t(src_ptr, end_src_ptr));
+  emit_jump_insn(gen_bne(label));
+  emit_insn(gen_rtx(SET, VOIDmode, dst_ptr, dst_ptr));
+  
+  DONE;	
+}
+")
+
+
+
+
+   
+;; -------------------------------------------------------------------------
+;; Peepholes
+;; -------------------------------------------------------------------------
+
+
+(define_peephole 
+  [(set (match_operand:QI 0 "register_operand" "")
+	(mem:QI (match_operand:SI 1 "register_operand" "")))
+   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
+  "REGNO(operands[1]) != REGNO(operands[0])"
+  "mov.b	@%1+,%0")
+
+(define_peephole 
+  [(set (match_operand:HI 0 "register_operand" "")
+	(mem:HI (match_operand:SI 1 "register_operand" "")))
+   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))]
+  "REGNO(operands[1]) != REGNO(operands[0])"
+  "mov.w	@%1+,%0")
+
+(define_peephole 
+  [(set (match_operand:SI 0 "register_operand" "")
+	(mem:SI (match_operand:SI 1 "register_operand" "")))
+   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
+  "REGNO(operands[1]) != REGNO(operands[0])"
+  "mov.l	@%1+,%0")

gcc/config/sh/t-sh

+LIBGCC1 = libgcc1.null
+T_CFLAGS = -DDONT_HAVE_STDIO -DDONT_HAVE_SETJMP  -Dinhibit_libc
+LIBGCC2_CFLAGS=-g -fno-omit-frame-pointer -O2 $(GCC_CFLAGS) 
+LANGUAGES=c
+COMPILERS=cc1
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so... [taken from t-ose68k]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+

gcc/config/sh/xm-sh.h

+/* Configuration for GNU C-compiler for Hitachi SH.
+   Copyright (C) 1993 Free Software Foundation, Inc.
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+
+/* If compiled with GNU C, use the built-in alloca.  */
+#ifdef __GNUC__
+#define alloca __builtin_alloca
+#endif
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.  */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
+