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Commit bc02597b by Kazu Hirata Committed by Kazu Hirata
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h8300.md: (stm_h8300s_2): Change the name to stm_h8300s_2_advanced. 

	* config/h8300/h8300.md: (stm_h8300s_2): Change the name to
	stm_h8300s_2_advanced.
	(stm_h8300s_2_normal): New.
	(stm_h8300s_2): Likewise.
	(stm_h8300s_3): Change the name to stm_h8300s_3_advanced.
	(stm_h8300s_3_normal): New.
	(stm_h8300s_3): Likewise.
	(stm_h8300s_4): Change the name to stm_h8300s_4_advanced.
	(stm_h8300s_4_normal): New.
	(stm_h8300s_4): Likewise.
	(ldm_h8300s_2): Change the name to ldm_h8300s_2_advanced.
	(ldm_h8300s_2_normal): New.
	(ldm_h8300s_2): Likewise.
	(ldm_h8300s_3): Change the name to ldm_h8300s_3_advanced.
	(ldm_h8300s_3_normal): New.
	(ldm_h8300s_3): Likewise.
	(ldm_h8300s_4): Change the name to ldm_h8300s_4_advanced.
	(ldm_h8300s_4_normal): New.
	(ldm_h8300s_4): Likewise.
	(two peephole2's): Enable only with !TARGET_NORMAL_MODE.
	(two peephole2's): New.

From-SVN: r73879
parent 3f047028
Showing with 365 additions and 17 deletions
gcc/ChangeLog
2003-11-24 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md: (stm_h8300s_2): Change the name to
stm_h8300s_2_advanced.
(stm_h8300s_2_normal): New.
(stm_h8300s_2): Likewise.
(stm_h8300s_3): Change the name to stm_h8300s_3_advanced.
(stm_h8300s_3_normal): New.
(stm_h8300s_3): Likewise.
(stm_h8300s_4): Change the name to stm_h8300s_4_advanced.
(stm_h8300s_4_normal): New.
(stm_h8300s_4): Likewise.
(ldm_h8300s_2): Change the name to ldm_h8300s_2_advanced.
(ldm_h8300s_2_normal): New.
(ldm_h8300s_2): Likewise.
(ldm_h8300s_3): Change the name to ldm_h8300s_3_advanced.
(ldm_h8300s_3_normal): New.
(ldm_h8300s_3): Likewise.
(ldm_h8300s_4): Change the name to ldm_h8300s_4_advanced.
(ldm_h8300s_4_normal): New.
(ldm_h8300s_4): Likewise.
(two peephole2's): Enable only with !TARGET_NORMAL_MODE.
(two peephole2's): New.
2003-11-24 Zdenek Dvorak <rakdver@atrey.karlin.mff.cuni.cz> 2003-11-24 Zdenek Dvorak <rakdver@atrey.karlin.mff.cuni.cz>
* genattrtab.c (simplify_cond): Update indices correctly. * genattrtab.c (simplify_cond): Update indices correctly.
......
gcc/config/h8300/h8300.md
...@@ -1897,7 +1897,7 @@ ...@@ -1897,7 +1897,7 @@
"TARGET_NORMAL_MODE" "TARGET_NORMAL_MODE"
"") "")
(define_insn "stm_h8300s_2" (define_insn "stm_h8300s_2_advanced"
[(parallel [(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -8))) (plus:SI (reg:SI SP_REG) (const_int -8)))
...@@ -1905,7 +1905,23 @@ ...@@ -1905,7 +1905,23 @@
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" ""))])] (match_operand:SI 1 "register_operand" ""))])]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
"stm.l\\t%S0-%S1,@-er7"
[(set_attr "cc" "none")
(set_attr "length" "4")])
(define_insn "stm_h8300s_2_normal"
[(parallel
[(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -8)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))" || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
...@@ -1913,7 +1929,23 @@ ...@@ -1913,7 +1929,23 @@
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "stm_h8300s_3" (define_expand "stm_h8300s_2"
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
"
{
if (!TARGET_NORMAL_MODE)
emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
else
emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
DONE;
}")
(define_insn "stm_h8300s_3_advanced"
[(parallel [(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -12))) (plus:SI (reg:SI SP_REG) (const_int -12)))
...@@ -1923,7 +1955,28 @@ ...@@ -1923,7 +1955,28 @@
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" ""))])] (match_operand:SI 2 "register_operand" ""))])]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2)
|| (REGNO (operands[0]) == 4
&& REGNO (operands[1]) == 5
&& REGNO (operands[2]) == 6))"
"stm.l\\t%S0-%S2,@-er7"
[(set_attr "cc" "none")
(set_attr "length" "4")])
(define_insn "stm_h8300s_3_normal"
[(parallel
[(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -12)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1 && REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2) && REGNO (operands[2]) == 2)
...@@ -1934,7 +1987,29 @@ ...@@ -1934,7 +1987,29 @@
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "stm_h8300s_4" (define_expand "stm_h8300s_3"
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S
&& ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2)
|| (REGNO (operands[0]) == 4
&& REGNO (operands[1]) == 5
&& REGNO (operands[2]) == 6))"
"
{
if (!TARGET_NORMAL_MODE)
emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
operands[2]));
else
emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
operands[2]));
DONE;
}")
(define_insn "stm_h8300s_4_advanced"
[(parallel [(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int -16))) (plus:SI (reg:SI SP_REG) (const_int -16)))
...@@ -1946,7 +2021,7 @@ ...@@ -1946,7 +2021,7 @@
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16))) (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))])]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0 && REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1 && REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2 && REGNO (operands[2]) == 2
...@@ -1955,7 +2030,49 @@ ...@@ -1955,7 +2030,49 @@
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_2" (define_insn "stm_h8300s_4_normal"
[(parallel
[(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -16)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_operand:SI 1 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
(match_operand:SI 3 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2
&& REGNO (operands[3]) == 3"
"stm.l\\t%S0-%S3,@-er7"
[(set_attr "cc" "none")
(set_attr "length" "4")])
(define_expand "stm_h8300s_4"
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:SI 2 "register_operand" ""))
(use (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S
&& REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2
&& REGNO (operands[3]) == 3"
"
{
if (!TARGET_NORMAL_MODE)
emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
operands[2], operands[3]));
else
emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
operands[2], operands[3]));
DONE;
}")
(define_insn "ldm_h8300s_2_advanced"
[(parallel [(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 8))) (plus:SI (reg:SI SP_REG) (const_int 8)))
...@@ -1963,7 +2080,7 @@ ...@@ -1963,7 +2080,7 @@
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG)) (set (mem:SI (reg:SI SP_REG))
(match_operand:SI 1 "register_operand" ""))])] (match_operand:SI 1 "register_operand" ""))])]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))" || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
...@@ -1971,7 +2088,39 @@ ...@@ -1971,7 +2088,39 @@
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_3" (define_insn "ldm_h8300s_2_normal"
[(parallel
[(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 8)))
(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG))
(match_operand:SI 1 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
"ldm.l\\t@er7+,%S0-%S1"
[(set_attr "cc" "none")
(set_attr "length" "4")])
(define_expand "ldm_h8300s_2"
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
"
{
if (!TARGET_NORMAL_MODE)
emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
else
emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
DONE;
}")
(define_insn "ldm_h8300s_3_advanced"
[(parallel [(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 12))) (plus:SI (reg:SI SP_REG) (const_int 12)))
...@@ -1981,7 +2130,7 @@ ...@@ -1981,7 +2130,7 @@
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG)) (set (mem:SI (reg:SI SP_REG))
(match_operand:SI 2 "register_operand" ""))])] (match_operand:SI 2 "register_operand" ""))])]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1 && REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2) && REGNO (operands[2]) == 2)
...@@ -1992,7 +2141,50 @@ ...@@ -1992,7 +2141,50 @@
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_4" (define_insn "ldm_h8300s_3_normal"
[(parallel
[(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int 12)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
(match_operand:SI 1 "register_operand" ""))
(set (mem:SI (reg:HI SP_REG))
(match_operand:SI 2 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2)
|| (REGNO (operands[0]) == 4
&& REGNO (operands[1]) == 5
&& REGNO (operands[2]) == 6))"
"ldm.l\\t@er7+,%S0-%S2"
[(set_attr "cc" "none")
(set_attr "length" "4")])
(define_expand "ldm_h8300s_3"
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S
&& ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2)
|| (REGNO (operands[0]) == 4
&& REGNO (operands[1]) == 5
&& REGNO (operands[2]) == 6))"
"
{
if (!TARGET_NORMAL_MODE)
emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
operands[2]));
else
emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
operands[2]));
DONE;
}")
(define_insn "ldm_h8300s_4_advanced"
[(parallel [(parallel
[(set (reg:SI SP_REG) [(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG) (const_int 16))) (plus:SI (reg:SI SP_REG) (const_int 16)))
...@@ -2004,7 +2196,7 @@ ...@@ -2004,7 +2196,7 @@
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (reg:SI SP_REG)) (set (mem:SI (reg:SI SP_REG))
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))])]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0 && REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1 && REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2 && REGNO (operands[2]) == 2
...@@ -2013,6 +2205,48 @@ ...@@ -2013,6 +2205,48 @@
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "ldm_h8300s_4_normal"
[(parallel
[(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int 16)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
(match_operand:SI 1 "register_operand" ""))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (reg:HI SP_REG))
(match_operand:SI 3 "register_operand" ""))])]
"TARGET_H8300S && !TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2
&& REGNO (operands[3]) == 3"
"ldm.l\\t@er7+,%S0-%S3"
[(set_attr "cc" "none")
(set_attr "length" "4")])
(define_expand "ldm_h8300s_4"
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:SI 2 "register_operand" ""))
(use (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S && !TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2
&& REGNO (operands[3]) == 3"
"
{
if (!TARGET_NORMAL_MODE)
emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
operands[2], operands[3]));
else
emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
operands[2], operands[3]));
DONE;
}")
(define_expand "return" (define_expand "return"
[(return)] [(return)]
"h8300_can_use_return_insn_p ()" "h8300_can_use_return_insn_p ()"
...@@ -3622,11 +3856,21 @@ ...@@ -3622,11 +3856,21 @@
(plus:SI (reg:SI SP_REG) (const_int -4))) (plus:SI (reg:SI SP_REG) (const_int -4)))
(set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3))) (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
(match_operand:QI 0 "register_operand" ""))])] (match_operand:QI 0 "register_operand" ""))])]
"TARGET_H8300S" "TARGET_H8300S && !TARGET_NORMAL_MODE"
[(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
(match_dup 0))] (match_dup 0))]
"operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_peephole2
[(parallel [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -4)))
(set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
(match_operand:QI 0 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE"
[(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_dup 0))]
"operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
;; Convert a HImode push into an SImode push so that the ;; Convert a HImode push into an SImode push so that the
;; define_peephole2 below can cram multiple pushes into one stm.l. ;; define_peephole2 below can cram multiple pushes into one stm.l.
...@@ -3635,11 +3879,21 @@ ...@@ -3635,11 +3879,21 @@
(plus:SI (reg:SI SP_REG) (const_int -4))) (plus:SI (reg:SI SP_REG) (const_int -4)))
(set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2))) (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
(match_operand:HI 0 "register_operand" ""))])] (match_operand:HI 0 "register_operand" ""))])]
"TARGET_H8300S" "TARGET_H8300S && !TARGET_NORMAL_MODE"
[(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
(match_dup 0))] (match_dup 0))]
"operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_peephole2
[(parallel [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG) (const_int -4)))
(set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
(match_operand:HI 0 "register_operand" ""))])]
"TARGET_H8300S && TARGET_NORMAL_MODE"
[(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_dup 0))]
"operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
;; Cram four pushes into stm.l. ;; Cram four pushes into stm.l.
(define_peephole2 (define_peephole2
...@@ -3651,7 +3905,7 @@ ...@@ -3651,7 +3905,7 @@
(match_operand:SI 2 "register_operand" "")) (match_operand:SI 2 "register_operand" ""))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
(match_operand:SI 3 "register_operand" ""))] (match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0 && REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1 && REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2 && REGNO (operands[2]) == 2
...@@ -3669,6 +3923,33 @@ ...@@ -3669,6 +3923,33 @@
(match_dup 3))])] (match_dup 3))])]
"") "")
(define_peephole2
[(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 1 "register_operand" ""))
(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 2 "register_operand" ""))
(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 3 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2
&& REGNO (operands[3]) == 3"
[(parallel [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG)
(const_int -16)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_dup 0))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_dup 1))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
(match_dup 2))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
(match_dup 3))])]
"")
;; Cram three pushes into stm.l. ;; Cram three pushes into stm.l.
(define_peephole2 (define_peephole2
...@@ -3678,7 +3959,7 @@ ...@@ -3678,7 +3959,7 @@
(match_operand:SI 1 "register_operand" "")) (match_operand:SI 1 "register_operand" ""))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
(match_operand:SI 2 "register_operand" ""))] (match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1 && REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2) && REGNO (operands[2]) == 2)
...@@ -3696,6 +3977,31 @@ ...@@ -3696,6 +3977,31 @@
(match_dup 2))])] (match_dup 2))])]
"") "")
(define_peephole2
[(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 1 "register_operand" ""))
(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 2 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0
&& REGNO (operands[1]) == 1
&& REGNO (operands[2]) == 2)
|| (REGNO (operands[0]) == 4
&& REGNO (operands[1]) == 5
&& REGNO (operands[2]) == 6))"
[(parallel [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG)
(const_int -12)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_dup 0))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_dup 1))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
(match_dup 2))])]
"")
;; Cram two pushes into stm.l. ;; Cram two pushes into stm.l.
(define_peephole2 (define_peephole2
...@@ -3703,7 +4009,7 @@ ...@@ -3703,7 +4009,7 @@
(match_operand:SI 0 "register_operand" "")) (match_operand:SI 0 "register_operand" ""))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
(match_operand:SI 1 "register_operand" ""))] (match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S "TARGET_H8300S && !TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))" || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
...@@ -3716,6 +4022,24 @@ ...@@ -3716,6 +4022,24 @@
(match_dup 1))])] (match_dup 1))])]
"") "")
(define_peephole2
[(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 0 "register_operand" ""))
(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
(match_operand:SI 1 "register_operand" ""))]
"TARGET_H8300S && TARGET_NORMAL_MODE
&& ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
|| (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
|| (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
[(parallel [(set (reg:HI SP_REG)
(plus:HI (reg:HI SP_REG)
(const_int -8)))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
(match_dup 0))
(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
(match_dup 1))])]
"")
;; Turn ;; Turn
;; ;;
;; mov.w #2,r0 ;; mov.w #2,r0
......
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