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riscv-gcc-1
Commit ba2baa55 by Roger Sayle Committed by Roger Sayle
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i386.h (TARGET_USE_FANCY_MATH_387): New macro. 


	* config/i386/i386.h (TARGET_USE_FANCY_MATH_387): New macro.
	* config/i386/i386.c (override_options):  Set MASK_NO_FANCY_MATH_387
	automatically for targets without TARGET_80387.
	* config/i386/i386.md (sqrtsf2, sqrtsf2_1, sqrtsf2_i387, sqrtdf2,
	sqrtdf2_1, sqrtdf2_i387, *sqrtextendsfdf2, sqrtxf2,
	*sqrtextenddfxf2, *sqrtextendsfxf2, fpremxf4, fmodsf3, fmoddf3,
	fmodxf3, fprem1xf4, dremsf3, dremdf3, dremxf3, *sindf2, *sinsf2,
	*sinextendsfdf2, *sinxf2, *cosdf2, *cossf2, *cosextendsfdf2,
	*cosxf2, sincosdf3, sincossf3, *sincosextendsfdf3, sincosxf3,
	*tandf3_1, tandf2, *tansf3_1, tansf2, *tanxf3_1, tanxf2,
	atan2df3_1, atan2df3, atandf2, atan2sf3_1, atan2sf3, atansf2,
	atan2xf3_1, atan2xf3, atanxf2, asindf2, asinsf2, asinxf2,
	acosdf2, acossf2, acosxf2, fyl2x_xf3, logsf2, logdf2, logxf2,
	log10sf2, log10df2, log10xf2, log2sf2, log2df2, log2xf2,
	fyl2xp1_xf3, log1psf2, log1pdf2, log1pxf2, *fxtractxf3, logbsf2,
	logbdf2, logbxf2, ilogbsi2, *f2xm1xf2, *fscalexf4, expsf2,
	expdf2, expxf2, exp10sf2, exp10df2, exp10xf2, exp2sf2, exp2df2,
	exp2xf2, expm1df2, expm1sf2, expm1xf2, frndintxf2, rintdf2,
	rintsf2, rintxf2, frndintxf2_floor, floordf2, floorsf2,
	floorxf2, frndintxf2_ceil, ceildf2, ceilsf2, ceilxf2,
	frndintxf2_trunc, btruncdf2, btruncsf2, btruncxf2,
	frndintxf2_mask_pm, nearbyintdf2, nearbyintsf2, nearbyintxf2):
	Simplify conditionals using TARGET_USE_FANCY_MATH_387.

From-SVN: r91061
parent 5a25e0c5
Showing with 138 additions and 104 deletions
gcc/ChangeLog
2004-11-22 Roger Sayle <roger@eyesopen.com>
* config/i386/i386.h (TARGET_USE_FANCY_MATH_387): New macro.
* config/i386/i386.c (override_options): Set MASK_NO_FANCY_MATH_387
automatically for targets without TARGET_80387.
* config/i386/i386.md (sqrtsf2, sqrtsf2_1, sqrtsf2_i387, sqrtdf2,
sqrtdf2_1, sqrtdf2_i387, *sqrtextendsfdf2, sqrtxf2,
*sqrtextenddfxf2, *sqrtextendsfxf2, fpremxf4, fmodsf3, fmoddf3,
fmodxf3, fprem1xf4, dremsf3, dremdf3, dremxf3, *sindf2, *sinsf2,
*sinextendsfdf2, *sinxf2, *cosdf2, *cossf2, *cosextendsfdf2,
*cosxf2, sincosdf3, sincossf3, *sincosextendsfdf3, sincosxf3,
*tandf3_1, tandf2, *tansf3_1, tansf2, *tanxf3_1, tanxf2,
atan2df3_1, atan2df3, atandf2, atan2sf3_1, atan2sf3, atansf2,
atan2xf3_1, atan2xf3, atanxf2, asindf2, asinsf2, asinxf2,
acosdf2, acossf2, acosxf2, fyl2x_xf3, logsf2, logdf2, logxf2,
log10sf2, log10df2, log10xf2, log2sf2, log2df2, log2xf2,
fyl2xp1_xf3, log1psf2, log1pdf2, log1pxf2, *fxtractxf3, logbsf2,
logbdf2, logbxf2, ilogbsi2, *f2xm1xf2, *fscalexf4, expsf2,
expdf2, expxf2, exp10sf2, exp10df2, exp10xf2, exp2sf2, exp2df2,
exp2xf2, expm1df2, expm1sf2, expm1xf2, frndintxf2, rintdf2,
rintsf2, rintxf2, frndintxf2_floor, floordf2, floorsf2,
floorxf2, frndintxf2_ceil, ceildf2, ceilsf2, ceilxf2,
frndintxf2_trunc, btruncdf2, btruncsf2, btruncxf2,
frndintxf2_mask_pm, nearbyintdf2, nearbyintsf2, nearbyintxf2):
Simplify conditionals using TARGET_USE_FANCY_MATH_387.
2004-11-22 Dale Johannesen <dalej@apple.com> 2004-11-22 Dale Johannesen <dalej@apple.com>
* config/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Conditionalize * config/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Conditionalize
......
gcc/config/i386/i386.c
...@@ -1482,6 +1482,11 @@ override_options (void) ...@@ -1482,6 +1482,11 @@ override_options (void)
if (x86_arch_always_fancy_math_387 & (1 << ix86_arch)) if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
target_flags &= ~MASK_NO_FANCY_MATH_387; target_flags &= ~MASK_NO_FANCY_MATH_387;
/* Likewise, if the target doesn't have a 387, or we've specified
software floating point, don't use 387 inline instrinsics. */
if (!TARGET_80387)
target_flags |= MASK_NO_FANCY_MATH_387;
/* Turn on SSE2 builtins for -msse3. */ /* Turn on SSE2 builtins for -msse3. */
if (TARGET_SSE3) if (TARGET_SSE3)
target_flags |= MASK_SSE2; target_flags |= MASK_SSE2;
......
gcc/config/i386/i386.h
...@@ -177,6 +177,9 @@ extern int target_flags; ...@@ -177,6 +177,9 @@ extern int target_flags;
This is because FreeBSD lacks these in the math-emulator-code */ This is because FreeBSD lacks these in the math-emulator-code */
#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
/* Generate 387 floating point intrinsics for the current target. */
#define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387)
/* Don't create frame pointers for leaf functions */ /* Don't create frame pointers for leaf functions */
#define TARGET_OMIT_LEAF_FRAME_POINTER \ #define TARGET_OMIT_LEAF_FRAME_POINTER \
(target_flags & MASK_OMIT_LEAF_FRAME_POINTER) (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
......
gcc/config/i386/i386.md
...@@ -14844,7 +14844,7 @@ ...@@ -14844,7 +14844,7 @@
(define_expand "sqrtsf2" (define_expand "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))] (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH" "TARGET_USE_FANCY_MATH_387 || TARGET_SSE_MATH"
{ {
if (!TARGET_SSE_MATH) if (!TARGET_SSE_MATH)
operands[1] = force_reg (SFmode, operands[1]); operands[1] = force_reg (SFmode, operands[1]);
...@@ -14853,7 +14853,7 @@ ...@@ -14853,7 +14853,7 @@
(define_insn "sqrtsf2_1" (define_insn "sqrtsf2_1"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f") [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))] (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@ "@
fsqrt fsqrt
...@@ -14874,7 +14874,7 @@ ...@@ -14874,7 +14874,7 @@
(define_insn "sqrtsf2_i387" (define_insn "sqrtsf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))] (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& !TARGET_SSE_MATH" && !TARGET_SSE_MATH"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -14884,7 +14884,7 @@ ...@@ -14884,7 +14884,7 @@
(define_expand "sqrtdf2" (define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))] (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) "TARGET_USE_FANCY_MATH_387
|| (TARGET_SSE2 && TARGET_SSE_MATH)" || (TARGET_SSE2 && TARGET_SSE_MATH)"
{ {
if (!TARGET_SSE2 || !TARGET_SSE_MATH) if (!TARGET_SSE2 || !TARGET_SSE_MATH)
...@@ -14894,7 +14894,7 @@ ...@@ -14894,7 +14894,7 @@
(define_insn "sqrtdf2_1" (define_insn "sqrtdf2_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))] (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@ "@
fsqrt fsqrt
...@@ -14915,7 +14915,7 @@ ...@@ -14915,7 +14915,7 @@
(define_insn "sqrtdf2_i387" (define_insn "sqrtdf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))] (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE2 || !TARGET_SSE_MATH)" && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -14926,7 +14926,7 @@ ...@@ -14926,7 +14926,7 @@
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF (sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))] (match_operand:SF 1 "register_operand" "0"))))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& !(TARGET_SSE2 && TARGET_SSE_MATH)" && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -14936,7 +14936,7 @@ ...@@ -14936,7 +14936,7 @@
(define_insn "sqrtxf2" (define_insn "sqrtxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (match_operand:XF 1 "register_operand" "0")))] (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
"TARGET_80387 && !TARGET_NO_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -14947,7 +14947,7 @@ ...@@ -14947,7 +14947,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF (sqrt:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))] (match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387 && !TARGET_NO_FANCY_MATH_387" "TARGET_USE_FANCY_MATH_387"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF") (set_attr "mode" "XF")
...@@ -14957,7 +14957,7 @@ ...@@ -14957,7 +14957,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF (sqrt:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))] (match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387 && !TARGET_NO_FANCY_MATH_387" "TARGET_USE_FANCY_MATH_387"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF") (set_attr "mode" "XF")
...@@ -14973,7 +14973,7 @@ ...@@ -14973,7 +14973,7 @@
UNSPEC_FPREM_U)) UNSPEC_FPREM_U))
(set (reg:CCFP FPSR_REG) (set (reg:CCFP FPSR_REG)
(unspec:CCFP [(const_int 0)] UNSPEC_NOP))] (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fprem" "fprem"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -14983,7 +14983,7 @@ ...@@ -14983,7 +14983,7 @@
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" "")) (use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))] (use (match_operand:SF 2 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx label = gen_label_rtx (); rtx label = gen_label_rtx ();
...@@ -15007,7 +15007,7 @@ ...@@ -15007,7 +15007,7 @@
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" "")) (use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))] (use (match_operand:DF 2 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx label = gen_label_rtx (); rtx label = gen_label_rtx ();
...@@ -15031,7 +15031,7 @@ ...@@ -15031,7 +15031,7 @@
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))] (use (match_operand:XF 2 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx label = gen_label_rtx (); rtx label = gen_label_rtx ();
...@@ -15056,7 +15056,7 @@ ...@@ -15056,7 +15056,7 @@
UNSPEC_FPREM1_U)) UNSPEC_FPREM1_U))
(set (reg:CCFP FPSR_REG) (set (reg:CCFP FPSR_REG)
(unspec:CCFP [(const_int 0)] UNSPEC_NOP))] (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fprem1" "fprem1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15066,7 +15066,7 @@ ...@@ -15066,7 +15066,7 @@
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" "")) (use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))] (use (match_operand:SF 2 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx label = gen_label_rtx (); rtx label = gen_label_rtx ();
...@@ -15090,7 +15090,7 @@ ...@@ -15090,7 +15090,7 @@
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" "")) (use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))] (use (match_operand:DF 2 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx label = gen_label_rtx (); rtx label = gen_label_rtx ();
...@@ -15114,7 +15114,7 @@ ...@@ -15114,7 +15114,7 @@
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))] (use (match_operand:XF 2 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx label = gen_label_rtx (); rtx label = gen_label_rtx ();
...@@ -15132,7 +15132,7 @@ ...@@ -15132,7 +15132,7 @@
(define_insn "*sindf2" (define_insn "*sindf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))] (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15141,7 +15141,7 @@ ...@@ -15141,7 +15141,7 @@
(define_insn "*sinsf2" (define_insn "*sinsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))] (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15152,7 +15152,7 @@ ...@@ -15152,7 +15152,7 @@
(unspec:DF [(float_extend:DF (unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))] (match_operand:SF 1 "register_operand" "0"))]
UNSPEC_SIN))] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15161,7 +15161,7 @@ ...@@ -15161,7 +15161,7 @@
(define_insn "*sinxf2" (define_insn "*sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))] (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
"TARGET_80387 && !TARGET_NO_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15170,7 +15170,7 @@ ...@@ -15170,7 +15170,7 @@
(define_insn "*cosdf2" (define_insn "*cosdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))] (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15179,7 +15179,7 @@ ...@@ -15179,7 +15179,7 @@
(define_insn "*cossf2" (define_insn "*cossf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))] (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15190,7 +15190,7 @@ ...@@ -15190,7 +15190,7 @@
(unspec:DF [(float_extend:DF (unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))] (match_operand:SF 1 "register_operand" "0"))]
UNSPEC_COS))] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15199,7 +15199,7 @@ ...@@ -15199,7 +15199,7 @@
(define_insn "*cosxf2" (define_insn "*cosxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))] (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15217,7 +15217,7 @@ ...@@ -15217,7 +15217,7 @@
UNSPEC_SINCOS_COS)) UNSPEC_SINCOS_COS))
(set (match_operand:DF 1 "register_operand" "=u") (set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))] (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsincos" "fsincos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15251,7 +15251,7 @@ ...@@ -15251,7 +15251,7 @@
UNSPEC_SINCOS_COS)) UNSPEC_SINCOS_COS))
(set (match_operand:SF 1 "register_operand" "=u") (set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))] (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsincos" "fsincos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15287,7 +15287,7 @@ ...@@ -15287,7 +15287,7 @@
(set (match_operand:DF 1 "register_operand" "=u") (set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(float_extend:DF (unspec:DF [(float_extend:DF
(match_dup 2))] UNSPEC_SINCOS_SIN))] (match_dup 2))] UNSPEC_SINCOS_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsincos" "fsincos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15327,7 +15327,7 @@ ...@@ -15327,7 +15327,7 @@
UNSPEC_SINCOS_COS)) UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand" "=u") (set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsincos" "fsincos"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15361,7 +15361,7 @@ ...@@ -15361,7 +15361,7 @@
UNSPEC_TAN_ONE)) UNSPEC_TAN_ONE))
(set (match_operand:DF 1 "register_operand" "=u") (set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))] (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fptan" "fptan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15391,7 +15391,7 @@ ...@@ -15391,7 +15391,7 @@
UNSPEC_TAN_ONE)) UNSPEC_TAN_ONE))
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])] (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (DFmode); operands[2] = gen_reg_rtx (DFmode);
...@@ -15403,7 +15403,7 @@ ...@@ -15403,7 +15403,7 @@
UNSPEC_TAN_ONE)) UNSPEC_TAN_ONE))
(set (match_operand:SF 1 "register_operand" "=u") (set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))] (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fptan" "fptan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15433,7 +15433,7 @@ ...@@ -15433,7 +15433,7 @@
UNSPEC_TAN_ONE)) UNSPEC_TAN_ONE))
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])] (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (SFmode); operands[2] = gen_reg_rtx (SFmode);
...@@ -15445,7 +15445,7 @@ ...@@ -15445,7 +15445,7 @@
UNSPEC_TAN_ONE)) UNSPEC_TAN_ONE))
(set (match_operand:XF 1 "register_operand" "=u") (set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))] (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fptan" "fptan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15475,7 +15475,7 @@ ...@@ -15475,7 +15475,7 @@
UNSPEC_TAN_ONE)) UNSPEC_TAN_ONE))
(set (match_operand:XF 0 "register_operand" "") (set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])] (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -15487,7 +15487,7 @@ ...@@ -15487,7 +15487,7 @@
(match_operand:DF 1 "register_operand" "u")] (match_operand:DF 1 "register_operand" "u")]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 "=1"))] (clobber (match_scratch:DF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fpatan" "fpatan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15497,7 +15497,7 @@ ...@@ -15497,7 +15497,7 @@
[(use (match_operand:DF 0 "register_operand" "=f")) [(use (match_operand:DF 0 "register_operand" "=f"))
(use (match_operand:DF 2 "register_operand" "0")) (use (match_operand:DF 2 "register_operand" "0"))
(use (match_operand:DF 1 "register_operand" "u"))] (use (match_operand:DF 1 "register_operand" "u"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx copy = gen_reg_rtx (DFmode); rtx copy = gen_reg_rtx (DFmode);
...@@ -15512,7 +15512,7 @@ ...@@ -15512,7 +15512,7 @@
(match_operand:DF 1 "register_operand" "")] (match_operand:DF 1 "register_operand" "")]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 ""))])] (clobber (match_scratch:DF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (DFmode); operands[2] = gen_reg_rtx (DFmode);
...@@ -15525,7 +15525,7 @@ ...@@ -15525,7 +15525,7 @@
(match_operand:SF 1 "register_operand" "u")] (match_operand:SF 1 "register_operand" "u")]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 "=1"))] (clobber (match_scratch:SF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fpatan" "fpatan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15535,7 +15535,7 @@ ...@@ -15535,7 +15535,7 @@
[(use (match_operand:SF 0 "register_operand" "=f")) [(use (match_operand:SF 0 "register_operand" "=f"))
(use (match_operand:SF 2 "register_operand" "0")) (use (match_operand:SF 2 "register_operand" "0"))
(use (match_operand:SF 1 "register_operand" "u"))] (use (match_operand:SF 1 "register_operand" "u"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx copy = gen_reg_rtx (SFmode); rtx copy = gen_reg_rtx (SFmode);
...@@ -15550,7 +15550,7 @@ ...@@ -15550,7 +15550,7 @@
(match_operand:SF 1 "register_operand" "")] (match_operand:SF 1 "register_operand" "")]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 ""))])] (clobber (match_scratch:SF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (SFmode); operands[2] = gen_reg_rtx (SFmode);
...@@ -15563,7 +15563,7 @@ ...@@ -15563,7 +15563,7 @@
(match_operand:XF 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=1"))] (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fpatan" "fpatan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15573,7 +15573,7 @@ ...@@ -15573,7 +15573,7 @@
[(use (match_operand:XF 0 "register_operand" "=f")) [(use (match_operand:XF 0 "register_operand" "=f"))
(use (match_operand:XF 2 "register_operand" "0")) (use (match_operand:XF 2 "register_operand" "0"))
(use (match_operand:XF 1 "register_operand" "u"))] (use (match_operand:XF 1 "register_operand" "u"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx copy = gen_reg_rtx (XFmode); rtx copy = gen_reg_rtx (XFmode);
...@@ -15588,7 +15588,7 @@ ...@@ -15588,7 +15588,7 @@
(match_operand:XF 1 "register_operand" "")] (match_operand:XF 1 "register_operand" "")]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 ""))])] (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -15607,7 +15607,7 @@ ...@@ -15607,7 +15607,7 @@
(clobber (match_scratch:XF 8 ""))]) (clobber (match_scratch:XF 8 ""))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))] (float_truncate:DF (match_dup 7)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -15630,7 +15630,7 @@ ...@@ -15630,7 +15630,7 @@
(clobber (match_scratch:XF 8 ""))]) (clobber (match_scratch:XF 8 ""))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))] (float_truncate:SF (match_dup 7)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -15651,7 +15651,7 @@ ...@@ -15651,7 +15651,7 @@
(unspec:XF [(match_dup 5) (match_dup 1)] (unspec:XF [(match_dup 5) (match_dup 1)]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])] (clobber (match_scratch:XF 6 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -15674,7 +15674,7 @@ ...@@ -15674,7 +15674,7 @@
(clobber (match_scratch:XF 8 ""))]) (clobber (match_scratch:XF 8 ""))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))] (float_truncate:DF (match_dup 7)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -15697,7 +15697,7 @@ ...@@ -15697,7 +15697,7 @@
(clobber (match_scratch:XF 8 ""))]) (clobber (match_scratch:XF 8 ""))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))] (float_truncate:SF (match_dup 7)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -15718,7 +15718,7 @@ ...@@ -15718,7 +15718,7 @@
(unspec:XF [(match_dup 1) (match_dup 5)] (unspec:XF [(match_dup 1) (match_dup 5)]
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])] (clobber (match_scratch:XF 6 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -15735,7 +15735,7 @@ ...@@ -15735,7 +15735,7 @@
(match_operand:XF 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X)) UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 "=1"))] (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fyl2x" "fyl2x"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15750,7 +15750,7 @@ ...@@ -15750,7 +15750,7 @@
(clobber (match_scratch:XF 5 ""))]) (clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))] (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15772,7 +15772,7 @@ ...@@ -15772,7 +15772,7 @@
(clobber (match_scratch:XF 5 ""))]) (clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))] (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15790,7 +15790,7 @@ ...@@ -15790,7 +15790,7 @@
(unspec:XF [(match_operand:XF 1 "register_operand" "") (unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X)) (match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])] (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15809,7 +15809,7 @@ ...@@ -15809,7 +15809,7 @@
(clobber (match_scratch:XF 5 ""))]) (clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))] (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15831,7 +15831,7 @@ ...@@ -15831,7 +15831,7 @@
(clobber (match_scratch:XF 5 ""))]) (clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))] (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15849,7 +15849,7 @@ ...@@ -15849,7 +15849,7 @@
(unspec:XF [(match_operand:XF 1 "register_operand" "") (unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X)) (match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])] (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15868,7 +15868,7 @@ ...@@ -15868,7 +15868,7 @@
(clobber (match_scratch:XF 5 ""))]) (clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))] (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -15887,7 +15887,7 @@ ...@@ -15887,7 +15887,7 @@
(clobber (match_scratch:XF 5 ""))]) (clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))] (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -15902,7 +15902,7 @@ ...@@ -15902,7 +15902,7 @@
(unspec:XF [(match_operand:XF 1 "register_operand" "") (unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X)) (match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])] (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -15915,7 +15915,7 @@ ...@@ -15915,7 +15915,7 @@
(match_operand:XF 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2XP1)) UNSPEC_FYL2XP1))
(clobber (match_scratch:XF 3 "=1"))] (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fyl2xp1" "fyl2xp1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15924,7 +15924,7 @@ ...@@ -15924,7 +15924,7 @@
(define_expand "log1psf2" (define_expand "log1psf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -15939,7 +15939,7 @@ ...@@ -15939,7 +15939,7 @@
(define_expand "log1pdf2" (define_expand "log1pdf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -15954,7 +15954,7 @@ ...@@ -15954,7 +15954,7 @@
(define_expand "log1pxf2" (define_expand "log1pxf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
ix86_emit_i387_log1p (operands[0], operands[1]); ix86_emit_i387_log1p (operands[0], operands[1]);
...@@ -15967,7 +15967,7 @@ ...@@ -15967,7 +15967,7 @@
UNSPEC_XTRACT_FRACT)) UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 1 "register_operand" "=u") (set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))] (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fxtract" "fxtract"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15982,7 +15982,7 @@ ...@@ -15982,7 +15982,7 @@
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]) (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))] (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -15999,7 +15999,7 @@ ...@@ -15999,7 +15999,7 @@
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]) (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))] (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -16013,7 +16013,7 @@ ...@@ -16013,7 +16013,7 @@
UNSPEC_XTRACT_FRACT)) UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 0 "register_operand" "") (set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])] (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -16028,7 +16028,7 @@ ...@@ -16028,7 +16028,7 @@
(parallel [(set (match_operand:SI 0 "register_operand" "") (parallel [(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_dup 3))) (fix:SI (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])] (clobber (reg:CC FLAGS_REG))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
...@@ -16039,7 +16039,7 @@ ...@@ -16039,7 +16039,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_F2XM1))] UNSPEC_F2XM1))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"f2xm1" "f2xm1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -16053,7 +16053,7 @@ ...@@ -16053,7 +16053,7 @@
(set (match_operand:XF 1 "register_operand" "=u") (set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2) (match_dup 3)] (unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FSCALE_EXP))] UNSPEC_FSCALE_EXP))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fscale" "fscale"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -16075,7 +16075,7 @@ ...@@ -16075,7 +16075,7 @@
UNSPEC_FSCALE_EXP))]) UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))] (float_truncate:SF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16104,7 +16104,7 @@ ...@@ -16104,7 +16104,7 @@
UNSPEC_FSCALE_EXP))]) UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))] (float_truncate:DF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16130,7 +16130,7 @@ ...@@ -16130,7 +16130,7 @@
(set (match_dup 9) (set (match_dup 9)
(unspec:XF [(match_dup 8) (match_dup 4)] (unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])] UNSPEC_FSCALE_EXP))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16159,7 +16159,7 @@ ...@@ -16159,7 +16159,7 @@
UNSPEC_FSCALE_EXP))]) UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))] (float_truncate:SF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16188,7 +16188,7 @@ ...@@ -16188,7 +16188,7 @@
UNSPEC_FSCALE_EXP))]) UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))] (float_truncate:DF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16214,7 +16214,7 @@ ...@@ -16214,7 +16214,7 @@
(set (match_dup 9) (set (match_dup 9)
(unspec:XF [(match_dup 8) (match_dup 4)] (unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])] UNSPEC_FSCALE_EXP))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16242,7 +16242,7 @@ ...@@ -16242,7 +16242,7 @@
UNSPEC_FSCALE_EXP))]) UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 8)))] (float_truncate:SF (match_dup 8)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -16267,7 +16267,7 @@ ...@@ -16267,7 +16267,7 @@
UNSPEC_FSCALE_EXP))]) UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 8)))] (float_truncate:DF (match_dup 8)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -16289,7 +16289,7 @@ ...@@ -16289,7 +16289,7 @@
(set (match_dup 8) (set (match_dup 8)
(unspec:XF [(match_dup 7) (match_dup 3)] (unspec:XF [(match_dup 7) (match_dup 3)]
UNSPEC_FSCALE_EXP))])] UNSPEC_FSCALE_EXP))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
int i; int i;
...@@ -16322,7 +16322,7 @@ ...@@ -16322,7 +16322,7 @@
(set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8))) (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 14)))] (float_truncate:DF (match_dup 14)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16358,7 +16358,7 @@ ...@@ -16358,7 +16358,7 @@
(set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8))) (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 14)))] (float_truncate:SF (match_dup 14)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16392,7 +16392,7 @@ ...@@ -16392,7 +16392,7 @@
(set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9))) (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
(set (match_operand:XF 0 "register_operand" "") (set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_dup 12) (match_dup 7)))] (plus:XF (match_dup 12) (match_dup 7)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -16410,7 +16410,7 @@ ...@@ -16410,7 +16410,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT))] UNSPEC_FRNDINT))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"frndint" "frndint"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -16419,7 +16419,7 @@ ...@@ -16419,7 +16419,7 @@
(define_expand "rintdf2" (define_expand "rintdf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))] (use (match_operand:DF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16435,7 +16435,7 @@ ...@@ -16435,7 +16435,7 @@
(define_expand "rintsf2" (define_expand "rintsf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))] (use (match_operand:SF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16451,7 +16451,7 @@ ...@@ -16451,7 +16451,7 @@
(define_expand "rintxf2" (define_expand "rintxf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
emit_insn (gen_frndintxf2 (operands[0], operands[1])); emit_insn (gen_frndintxf2 (operands[0], operands[1]));
...@@ -16464,7 +16464,7 @@ ...@@ -16464,7 +16464,7 @@
UNSPEC_FRNDINT_FLOOR)) UNSPEC_FRNDINT_FLOOR))
(use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))] (use (match_operand:HI 3 "memory_operand" "m"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2" "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint") [(set_attr "type" "frndint")
...@@ -16474,7 +16474,7 @@ ...@@ -16474,7 +16474,7 @@
(define_expand "floordf2" (define_expand "floordf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))] (use (match_operand:DF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16494,7 +16494,7 @@ ...@@ -16494,7 +16494,7 @@
(define_expand "floorsf2" (define_expand "floorsf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))] (use (match_operand:SF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16514,7 +16514,7 @@ ...@@ -16514,7 +16514,7 @@
(define_expand "floorxf2" (define_expand "floorxf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op2 = assign_386_stack_local (HImode, 1); rtx op2 = assign_386_stack_local (HImode, 1);
...@@ -16532,7 +16532,7 @@ ...@@ -16532,7 +16532,7 @@
UNSPEC_FRNDINT_CEIL)) UNSPEC_FRNDINT_CEIL))
(use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))] (use (match_operand:HI 3 "memory_operand" "m"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2" "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint") [(set_attr "type" "frndint")
...@@ -16542,7 +16542,7 @@ ...@@ -16542,7 +16542,7 @@
(define_expand "ceildf2" (define_expand "ceildf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))] (use (match_operand:DF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16562,7 +16562,7 @@ ...@@ -16562,7 +16562,7 @@
(define_expand "ceilsf2" (define_expand "ceilsf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))] (use (match_operand:SF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16582,7 +16582,7 @@ ...@@ -16582,7 +16582,7 @@
(define_expand "ceilxf2" (define_expand "ceilxf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op2 = assign_386_stack_local (HImode, 1); rtx op2 = assign_386_stack_local (HImode, 1);
...@@ -16600,7 +16600,7 @@ ...@@ -16600,7 +16600,7 @@
UNSPEC_FRNDINT_TRUNC)) UNSPEC_FRNDINT_TRUNC))
(use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))] (use (match_operand:HI 3 "memory_operand" "m"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2" "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint") [(set_attr "type" "frndint")
...@@ -16610,7 +16610,7 @@ ...@@ -16610,7 +16610,7 @@
(define_expand "btruncdf2" (define_expand "btruncdf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))] (use (match_operand:DF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16630,7 +16630,7 @@ ...@@ -16630,7 +16630,7 @@
(define_expand "btruncsf2" (define_expand "btruncsf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))] (use (match_operand:SF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16650,7 +16650,7 @@ ...@@ -16650,7 +16650,7 @@
(define_expand "btruncxf2" (define_expand "btruncxf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op2 = assign_386_stack_local (HImode, 1); rtx op2 = assign_386_stack_local (HImode, 1);
...@@ -16668,7 +16668,7 @@ ...@@ -16668,7 +16668,7 @@
UNSPEC_FRNDINT_MASK_PM)) UNSPEC_FRNDINT_MASK_PM))
(use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))] (use (match_operand:HI 3 "memory_operand" "m"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2" "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
[(set_attr "type" "frndint") [(set_attr "type" "frndint")
...@@ -16678,7 +16678,7 @@ ...@@ -16678,7 +16678,7 @@
(define_expand "nearbyintdf2" (define_expand "nearbyintdf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))] (use (match_operand:DF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16698,7 +16698,7 @@ ...@@ -16698,7 +16698,7 @@
(define_expand "nearbyintsf2" (define_expand "nearbyintsf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))] (use (match_operand:SF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
...@@ -16718,7 +16718,7 @@ ...@@ -16718,7 +16718,7 @@
(define_expand "nearbyintxf2" (define_expand "nearbyintxf2"
[(use (match_operand:XF 0 "register_operand" "")) [(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))] (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op2 = assign_386_stack_local (HImode, 1); rtx op2 = assign_386_stack_local (HImode, 1);
......
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