altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.

gcc:

2014-02-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.
	(altivec_vsumsws): Add handling for -maltivec=be with a little
	endian target.
	(altivec_vsumsws_direct): New.
	(reduc_splus_<mode>): Call gen_altivec_vsumsws_direct instead of
	gen_altivec_vsumsws.

gcc/testsuite:

2014-02-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.dg/vmx/vsums.c: New.
	* gcc.dg/vmx/vsums-be-order.c: New.

From-SVN: r207414

gcc/ChangeLog

+2014-02-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.
+	(altivec_vsumsws): Add handling for -maltivec=be with a little
+	endian target.
+	(altivec_vsumsws_direct): New.
+	(reduc_splus_<mode>): Call gen_altivec_vsumsws_direct instead of
+	gen_altivec_vsumsws.
+
 2014-02-02  Jan Hubicka  <jh@suse.cz>
 
 	* ipa-devirt.c (subbinfo_with_vtable_at_offset,

gcc/config/rs6000/altivec.md

@@ -132,6 +132,7 @@
    UNSPEC_VMRGH_DIRECT
    UNSPEC_VMRGL_DIRECT
    UNSPEC_VSPLT_DIRECT
+   UNSPEC_VSUMSWS_DIRECT
 ])
 
 (define_c_enum "unspecv"
@@ -1601,6 +1602,27 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")]
 		     UNSPEC_VSUMSWS))
+   (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+   (clobber (match_scratch:V4SI 3 "=v"))]
+  "TARGET_ALTIVEC"
+{
+  if (BYTES_BIG_ENDIAN || VECTOR_ELT_ORDER_BIG)
+    return "vsumsws %0,%1,%2";
+  else
+    return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvspltw %0,%3,3";
+}
+  [(set_attr "type" "veccomplex")
+   (set (attr "length")
+     (if_then_else
+       (match_test "(BYTES_BIG_ENDIAN || VECTOR_ELT_ORDER_BIG)")
+       (const_string "4")
+       (const_string "12")))])
+
+(define_insn "altivec_vsumsws_direct"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
+                      (match_operand:V4SI 2 "register_operand" "v")]
+		     UNSPEC_VSUMSWS_DIRECT))
    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
   "TARGET_ALTIVEC"
   "vsumsws %0,%1,%2"
@@ -2337,7 +2359,7 @@
 
   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
   emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
-  emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));
+  emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
   DONE;
 })
 

gcc/testsuite/ChangeLog

+2014-02-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* gcc.dg/vmx/vsums.c: New.
+	* gcc.dg/vmx/vsums-be-order.c: New.
+
 2014-02-02  Jan Hubicka  <hubicka@ucw.cz>
 
 	* g++.dg/ipa/devirt-23.C: New testcase.

gcc/testsuite/gcc.dg/vmx/vsums-be-order.c

+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
+
+#include "harness.h"
+
+static void test()
+{
+  vector signed int va = {-7,11,-13,17};
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  vector signed int vb = {128,0,0,0};
+#else
+  vector signed int vb = {0,0,0,128};
+#endif
+
+  vector signed int vd = vec_sums (va, vb);
+  signed int r = vec_extract (vd, 3);
+
+  check (r == 136, "sums");
+}

gcc/testsuite/gcc.dg/vmx/vsums.c

+#include "harness.h"
+
+static void test()
+{
+  vector signed int va = {-7,11,-13,17};
+  vector signed int vb = {0,0,0,128};
+
+  vector signed int vd = vec_sums (va, vb);
+  signed int r = vec_extract (vd, 3);
+
+  check (r == 136, "sums");
+}