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Commit b6875aac by Kugan Vivekanandarajah Committed by Kugan Vivekanandarajah
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aarch-common-protos.h (struct mem_cost_table): Added new fields loadv and storev. 

gcc/ChangeLog:

2015-05-20  Kugan Vivekanandarajah  <kuganv@linaro.org>
	    Jim Wilson  <jim.wilson@linaro.org>

	* config/arm/aarch-common-protos.h (struct mem_cost_table): Added
	new  fields loadv and storev.
	* config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs):
	Initialize loadv and storev.
	* config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise.
	(cortexa53_extra_costs): Likewise.
	(cortexa57_extra_costs): Likewise.
	(xgene1_extra_costs): Likewise.
	* config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector
	rtx_costs.

2015-05-20  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and
	 storev.
	(cortexa8_extra_costs): Likewise.
	(cortexa5_extra_costs): Likewise.
	(cortexa7_extra_costs): Likewise.
	(cortexa12_extra_costs): Likewise.
	(cortexa15_extra_costs): Likewise.
	(v7m_extra_costs): Likewise.


Co-Authored-By: Jim Wilson <jim.wilson@linaro.org>

From-SVN: r223432
parent c725e7f8
Showing with 246 additions and 38 deletions
gcc/ChangeLog
2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org>
Jim Wilson <jim.wilson@linaro.org>
* config/arm/aarch-common-protos.h (struct mem_cost_table): Added
new fields loadv and storev.
* config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs):
Initialize loadv and storev.
* config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise.
(cortexa53_extra_costs): Likewise.
(cortexa57_extra_costs): Likewise.
(xgene1_extra_costs): Likewise.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector
rtx_costs.
2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and
storev.
(cortexa8_extra_costs): Likewise.
(cortexa5_extra_costs): Likewise.
(cortexa7_extra_costs): Likewise.
(cortexa12_extra_costs): Likewise.
(cortexa15_extra_costs): Likewise.
(v7m_extra_costs): Likewise.
2015-05-20 Jeff Law <law@redhat.com> 2015-05-20 Jeff Law <law@redhat.com>
* tree-ssa-threadupdate.c (thread_single_edge): Use delete_jump_thread * tree-ssa-threadupdate.c (thread_single_edge): Use delete_jump_thread
......
gcc/config/aarch64/aarch64-cost-tables.h
...@@ -83,7 +83,9 @@ const struct cpu_cost_table thunderx_extra_costs = ...@@ -83,7 +83,9 @@ const struct cpu_cost_table thunderx_extra_costs =
0, /* N/A: Stm_regs_per_insn_subsequent. */ 0, /* N/A: Stm_regs_per_insn_subsequent. */
0, /* Storef. */ 0, /* Storef. */
0, /* Stored. */ 0, /* Stored. */
COSTS_N_INSNS (1) /* Store_unaligned. */ COSTS_N_INSNS (1), /* Store_unaligned. */
COSTS_N_INSNS (1), /* Loadv. */
COSTS_N_INSNS (1) /* Storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
......
gcc/config/arm/aarch-common-protos.h
...@@ -102,6 +102,8 @@ struct mem_cost_table ...@@ -102,6 +102,8 @@ struct mem_cost_table
const int storef; /* SFmode. */ const int storef; /* SFmode. */
const int stored; /* DFmode. */ const int stored; /* DFmode. */
const int store_unaligned; /* Extra for unaligned stores. */ const int store_unaligned; /* Extra for unaligned stores. */
const int loadv; /* Vector load. */
const int storev; /* Vector store. */
}; };
struct fp_cost_table struct fp_cost_table
......
gcc/config/arm/aarch-cost-tables.h
...@@ -81,7 +81,9 @@ const struct cpu_cost_table generic_extra_costs = ...@@ -81,7 +81,9 @@ const struct cpu_cost_table generic_extra_costs =
1, /* stm_regs_per_insn_subsequent. */ 1, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (3), /* stored. */ COSTS_N_INSNS (3), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -182,7 +184,9 @@ const struct cpu_cost_table cortexa53_extra_costs = ...@@ -182,7 +184,9 @@ const struct cpu_cost_table cortexa53_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -283,7 +287,9 @@ const struct cpu_cost_table cortexa57_extra_costs = ...@@ -283,7 +287,9 @@ const struct cpu_cost_table cortexa57_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -385,6 +391,8 @@ const struct cpu_cost_table xgene1_extra_costs = ...@@ -385,6 +391,8 @@ const struct cpu_cost_table xgene1_extra_costs =
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
0, /* store_unaligned. */ 0, /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
......
gcc/config/arm/arm.c
...@@ -1024,7 +1024,9 @@ const struct cpu_cost_table cortexa9_extra_costs = ...@@ -1024,7 +1024,9 @@ const struct cpu_cost_table cortexa9_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (1), /* storef. */ COSTS_N_INSNS (1), /* storef. */
COSTS_N_INSNS (1), /* stored. */ COSTS_N_INSNS (1), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1125,7 +1127,9 @@ const struct cpu_cost_table cortexa8_extra_costs = ...@@ -1125,7 +1127,9 @@ const struct cpu_cost_table cortexa8_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (1), /* storef. */ COSTS_N_INSNS (1), /* storef. */
COSTS_N_INSNS (1), /* stored. */ COSTS_N_INSNS (1), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1227,7 +1231,9 @@ const struct cpu_cost_table cortexa5_extra_costs = ...@@ -1227,7 +1231,9 @@ const struct cpu_cost_table cortexa5_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (2), /* stored. */ COSTS_N_INSNS (2), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1330,7 +1336,9 @@ const struct cpu_cost_table cortexa7_extra_costs = ...@@ -1330,7 +1336,9 @@ const struct cpu_cost_table cortexa7_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (2), /* stored. */ COSTS_N_INSNS (2), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1431,7 +1439,9 @@ const struct cpu_cost_table cortexa12_extra_costs = ...@@ -1431,7 +1439,9 @@ const struct cpu_cost_table cortexa12_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (2), /* stored. */ COSTS_N_INSNS (2), /* stored. */
0 /* store_unaligned. */ 0, /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1532,7 +1542,9 @@ const struct cpu_cost_table cortexa15_extra_costs = ...@@ -1532,7 +1542,9 @@ const struct cpu_cost_table cortexa15_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
0 /* store_unaligned. */ 0, /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1633,7 +1645,9 @@ const struct cpu_cost_table v7m_extra_costs = ...@@ -1633,7 +1645,9 @@ const struct cpu_cost_table v7m_extra_costs =
1, /* stm_regs_per_insn_subsequent. */ 1, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (3), /* stored. */ COSTS_N_INSNS (3), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
......
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