Skip to content

R
riscv-gcc-1
Commit b6875aac by Kugan Vivekanandarajah Committed by Kugan Vivekanandarajah
Options

aarch-common-protos.h (struct mem_cost_table): Added new fields loadv and storev. 

gcc/ChangeLog:

2015-05-20  Kugan Vivekanandarajah  <kuganv@linaro.org>
	    Jim Wilson  <jim.wilson@linaro.org>

	* config/arm/aarch-common-protos.h (struct mem_cost_table): Added
	new  fields loadv and storev.
	* config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs):
	Initialize loadv and storev.
	* config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise.
	(cortexa53_extra_costs): Likewise.
	(cortexa57_extra_costs): Likewise.
	(xgene1_extra_costs): Likewise.
	* config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector
	rtx_costs.

2015-05-20  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and
	 storev.
	(cortexa8_extra_costs): Likewise.
	(cortexa5_extra_costs): Likewise.
	(cortexa7_extra_costs): Likewise.
	(cortexa12_extra_costs): Likewise.
	(cortexa15_extra_costs): Likewise.
	(v7m_extra_costs): Likewise.


Co-Authored-By: Jim Wilson <jim.wilson@linaro.org>

From-SVN: r223432
parent c725e7f8
Showing with 280 additions and 72 deletions
gcc/ChangeLog
2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org>
Jim Wilson <jim.wilson@linaro.org>
* config/arm/aarch-common-protos.h (struct mem_cost_table): Added
new fields loadv and storev.
* config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs):
Initialize loadv and storev.
* config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise.
(cortexa53_extra_costs): Likewise.
(cortexa57_extra_costs): Likewise.
(xgene1_extra_costs): Likewise.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector
rtx_costs.
2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and
storev.
(cortexa8_extra_costs): Likewise.
(cortexa5_extra_costs): Likewise.
(cortexa7_extra_costs): Likewise.
(cortexa12_extra_costs): Likewise.
(cortexa15_extra_costs): Likewise.
(v7m_extra_costs): Likewise.
2015-05-20 Jeff Law <law@redhat.com> 2015-05-20 Jeff Law <law@redhat.com>
* tree-ssa-threadupdate.c (thread_single_edge): Use delete_jump_thread * tree-ssa-threadupdate.c (thread_single_edge): Use delete_jump_thread
......
gcc/config/aarch64/aarch64-cost-tables.h
...@@ -83,7 +83,9 @@ const struct cpu_cost_table thunderx_extra_costs = ...@@ -83,7 +83,9 @@ const struct cpu_cost_table thunderx_extra_costs =
0, /* N/A: Stm_regs_per_insn_subsequent. */ 0, /* N/A: Stm_regs_per_insn_subsequent. */
0, /* Storef. */ 0, /* Storef. */
0, /* Stored. */ 0, /* Stored. */
COSTS_N_INSNS (1) /* Store_unaligned. */ COSTS_N_INSNS (1), /* Store_unaligned. */
COSTS_N_INSNS (1), /* Loadv. */
COSTS_N_INSNS (1) /* Storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
......
gcc/config/aarch64/aarch64.c
...@@ -5617,16 +5617,6 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5617,16 +5617,6 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
above this default. */ above this default. */
*cost = COSTS_N_INSNS (1); *cost = COSTS_N_INSNS (1);
/* TODO: The cost infrastructure currently does not handle
vector operations. Assume that all vector operations
are equally expensive. */
if (VECTOR_MODE_P (mode))
{
if (speed)
*cost += extra_cost->vect.alu;
return true;
}
switch (code) switch (code)
{ {
case SET: case SET:
...@@ -5641,7 +5631,9 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5641,7 +5631,9 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
if (speed) if (speed)
{ {
rtx address = XEXP (op0, 0); rtx address = XEXP (op0, 0);
if (GET_MODE_CLASS (mode) == MODE_INT) if (VECTOR_MODE_P (mode))
*cost += extra_cost->ldst.storev;
else if (GET_MODE_CLASS (mode) == MODE_INT)
*cost += extra_cost->ldst.store; *cost += extra_cost->ldst.store;
else if (mode == SFmode) else if (mode == SFmode)
*cost += extra_cost->ldst.storef; *cost += extra_cost->ldst.storef;
...@@ -5662,15 +5654,22 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5662,15 +5654,22 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
/* Fall through. */ /* Fall through. */
case REG: case REG:
/* The cost is one per vector-register copied. */
if (VECTOR_MODE_P (GET_MODE (op0)) && REG_P (op1))
{
int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1)
/ GET_MODE_SIZE (V4SImode);
*cost = COSTS_N_INSNS (n_minus_1 + 1);
}
/* const0_rtx is in general free, but we will use an /* const0_rtx is in general free, but we will use an
instruction to set a register to 0. */ instruction to set a register to 0. */
if (REG_P (op1) || op1 == const0_rtx) else if (REG_P (op1) || op1 == const0_rtx)
{ {
/* The cost is 1 per register copied. */ /* The cost is 1 per register copied. */
int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1) int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1)
/ UNITS_PER_WORD; / UNITS_PER_WORD;
*cost = COSTS_N_INSNS (n_minus_1 + 1); *cost = COSTS_N_INSNS (n_minus_1 + 1);
} }
else else
/* Cost is just the cost of the RHS of the set. */ /* Cost is just the cost of the RHS of the set. */
*cost += rtx_cost (op1, SET, 1, speed); *cost += rtx_cost (op1, SET, 1, speed);
...@@ -5768,7 +5767,9 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5768,7 +5767,9 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
approximation for the additional cost of the addressing approximation for the additional cost of the addressing
mode. */ mode. */
rtx address = XEXP (x, 0); rtx address = XEXP (x, 0);
if (GET_MODE_CLASS (mode) == MODE_INT) if (VECTOR_MODE_P (mode))
*cost += extra_cost->ldst.loadv;
else if (GET_MODE_CLASS (mode) == MODE_INT)
*cost += extra_cost->ldst.load; *cost += extra_cost->ldst.load;
else if (mode == SFmode) else if (mode == SFmode)
*cost += extra_cost->ldst.loadf; *cost += extra_cost->ldst.loadf;
...@@ -5785,6 +5786,16 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5785,6 +5786,16 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
case NEG: case NEG:
op0 = XEXP (x, 0); op0 = XEXP (x, 0);
if (VECTOR_MODE_P (mode))
{
if (speed)
{
/* FNEG. */
*cost += extra_cost->vect.alu;
}
return false;
}
if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
{ {
if (GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMPARE if (GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMPARE
...@@ -5823,7 +5834,12 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5823,7 +5834,12 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
case CLRSB: case CLRSB:
case CLZ: case CLZ:
if (speed) if (speed)
*cost += extra_cost->alu.clz; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.clz;
}
return false; return false;
...@@ -5909,6 +5925,20 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, ...@@ -5909,6 +5925,20 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
return false; return false;
} }
if (VECTOR_MODE_P (mode))
{
/* Vector compare. */
if (speed)
*cost += extra_cost->vect.alu;
if (aarch64_float_const_zero_rtx_p (op1))
{
/* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
cost. */
return true;
}
return false;
}
return false; return false;
case MINUS: case MINUS:
...@@ -5961,12 +5991,21 @@ cost_minus: ...@@ -5961,12 +5991,21 @@ cost_minus:
if (speed) if (speed)
{ {
if (GET_MODE_CLASS (mode) == MODE_INT) if (VECTOR_MODE_P (mode))
/* SUB(S). */ {
*cost += extra_cost->alu.arith; /* Vector SUB. */
*cost += extra_cost->vect.alu;
}
else if (GET_MODE_CLASS (mode) == MODE_INT)
{
/* SUB(S). */
*cost += extra_cost->alu.arith;
}
else if (GET_MODE_CLASS (mode) == MODE_FLOAT) else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
/* FSUB. */ {
*cost += extra_cost->fp[mode == DFmode].addsub; /* FSUB. */
*cost += extra_cost->fp[mode == DFmode].addsub;
}
} }
return true; return true;
} }
...@@ -6030,12 +6069,21 @@ cost_plus: ...@@ -6030,12 +6069,21 @@ cost_plus:
if (speed) if (speed)
{ {
if (GET_MODE_CLASS (mode) == MODE_INT) if (VECTOR_MODE_P (mode))
/* ADD. */ {
*cost += extra_cost->alu.arith; /* Vector ADD. */
*cost += extra_cost->vect.alu;
}
else if (GET_MODE_CLASS (mode) == MODE_INT)
{
/* ADD. */
*cost += extra_cost->alu.arith;
}
else if (GET_MODE_CLASS (mode) == MODE_FLOAT) else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
/* FADD. */ {
*cost += extra_cost->fp[mode == DFmode].addsub; /* FADD. */
*cost += extra_cost->fp[mode == DFmode].addsub;
}
} }
return true; return true;
} }
...@@ -6044,8 +6092,12 @@ cost_plus: ...@@ -6044,8 +6092,12 @@ cost_plus:
*cost = COSTS_N_INSNS (1); *cost = COSTS_N_INSNS (1);
if (speed) if (speed)
*cost += extra_cost->alu.rev; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.rev;
}
return false; return false;
case IOR: case IOR:
...@@ -6053,10 +6105,14 @@ cost_plus: ...@@ -6053,10 +6105,14 @@ cost_plus:
{ {
*cost = COSTS_N_INSNS (1); *cost = COSTS_N_INSNS (1);
if (speed) if (speed)
*cost += extra_cost->alu.rev; {
if (VECTOR_MODE_P (mode))
return true; *cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.rev;
}
return true;
} }
if (aarch64_extr_rtx_p (x, &op0, &op1)) if (aarch64_extr_rtx_p (x, &op0, &op1))
...@@ -6075,6 +6131,13 @@ cost_plus: ...@@ -6075,6 +6131,13 @@ cost_plus:
op0 = XEXP (x, 0); op0 = XEXP (x, 0);
op1 = XEXP (x, 1); op1 = XEXP (x, 1);
if (VECTOR_MODE_P (mode))
{
if (speed)
*cost += extra_cost->vect.alu;
return true;
}
if (code == AND if (code == AND
&& GET_CODE (op0) == MULT && GET_CODE (op0) == MULT
&& CONST_INT_P (XEXP (op0, 1)) && CONST_INT_P (XEXP (op0, 1))
...@@ -6143,6 +6206,13 @@ cost_plus: ...@@ -6143,6 +6206,13 @@ cost_plus:
x = XEXP (x, 0); x = XEXP (x, 0);
op0 = aarch64_strip_shift (x); op0 = aarch64_strip_shift (x);
if (VECTOR_MODE_P (mode))
{
/* Vector NOT. */
*cost += extra_cost->vect.alu;
return false;
}
/* MVN-shifted-reg. */ /* MVN-shifted-reg. */
if (op0 != x) if (op0 != x)
{ {
...@@ -6214,10 +6284,19 @@ cost_plus: ...@@ -6214,10 +6284,19 @@ cost_plus:
return true; return true;
} }
/* UXTB/UXTH. */
if (speed) if (speed)
*cost += extra_cost->alu.extend; {
if (VECTOR_MODE_P (mode))
{
/* UMOV. */
*cost += extra_cost->vect.alu;
}
else
{
/* UXTB/UXTH. */
*cost += extra_cost->alu.extend;
}
}
return false; return false;
case SIGN_EXTEND: case SIGN_EXTEND:
...@@ -6237,7 +6316,12 @@ cost_plus: ...@@ -6237,7 +6316,12 @@ cost_plus:
} }
if (speed) if (speed)
*cost += extra_cost->alu.extend; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.extend;
}
return false; return false;
case ASHIFT: case ASHIFT:
...@@ -6246,10 +6330,20 @@ cost_plus: ...@@ -6246,10 +6330,20 @@ cost_plus:
if (CONST_INT_P (op1)) if (CONST_INT_P (op1))
{ {
/* LSL (immediate), UBMF, UBFIZ and friends. These are all
aliases. */
if (speed) if (speed)
*cost += extra_cost->alu.shift; {
if (VECTOR_MODE_P (mode))
{
/* Vector shift (immediate). */
*cost += extra_cost->vect.alu;
}
else
{
/* LSL (immediate), UBMF, UBFIZ and friends. These are all
aliases. */
*cost += extra_cost->alu.shift;
}
}
/* We can incorporate zero/sign extend for free. */ /* We can incorporate zero/sign extend for free. */
if (GET_CODE (op0) == ZERO_EXTEND if (GET_CODE (op0) == ZERO_EXTEND
...@@ -6261,10 +6355,19 @@ cost_plus: ...@@ -6261,10 +6355,19 @@ cost_plus:
} }
else else
{ {
/* LSLV. */
if (speed) if (speed)
*cost += extra_cost->alu.shift_reg; {
if (VECTOR_MODE_P (mode))
{
/* Vector shift (register). */
*cost += extra_cost->vect.alu;
}
else
{
/* LSLV. */
*cost += extra_cost->alu.shift_reg;
}
}
return false; /* All arguments need to be in registers. */ return false; /* All arguments need to be in registers. */
} }
...@@ -6279,7 +6382,12 @@ cost_plus: ...@@ -6279,7 +6382,12 @@ cost_plus:
{ {
/* ASR (immediate) and friends. */ /* ASR (immediate) and friends. */
if (speed) if (speed)
*cost += extra_cost->alu.shift; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.shift;
}
*cost += rtx_cost (op0, (enum rtx_code) code, 0, speed); *cost += rtx_cost (op0, (enum rtx_code) code, 0, speed);
return true; return true;
...@@ -6289,8 +6397,12 @@ cost_plus: ...@@ -6289,8 +6397,12 @@ cost_plus:
/* ASR (register) and friends. */ /* ASR (register) and friends. */
if (speed) if (speed)
*cost += extra_cost->alu.shift_reg; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.shift_reg;
}
return false; /* All arguments need to be in registers. */ return false; /* All arguments need to be in registers. */
} }
...@@ -6338,7 +6450,12 @@ cost_plus: ...@@ -6338,7 +6450,12 @@ cost_plus:
case SIGN_EXTRACT: case SIGN_EXTRACT:
/* UBFX/SBFX. */ /* UBFX/SBFX. */
if (speed) if (speed)
*cost += extra_cost->alu.bfx; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->alu.bfx;
}
/* We can trust that the immediates used will be correct (there /* We can trust that the immediates used will be correct (there
are no by-register forms), so we need only cost op0. */ are no by-register forms), so we need only cost op0. */
...@@ -6355,7 +6472,9 @@ cost_plus: ...@@ -6355,7 +6472,9 @@ cost_plus:
case UMOD: case UMOD:
if (speed) if (speed)
{ {
if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
*cost += (extra_cost->mult[GET_MODE (x) == DImode].add *cost += (extra_cost->mult[GET_MODE (x) == DImode].add
+ extra_cost->mult[GET_MODE (x) == DImode].idiv); + extra_cost->mult[GET_MODE (x) == DImode].idiv);
else if (GET_MODE (x) == DFmode) else if (GET_MODE (x) == DFmode)
...@@ -6372,7 +6491,9 @@ cost_plus: ...@@ -6372,7 +6491,9 @@ cost_plus:
case SQRT: case SQRT:
if (speed) if (speed)
{ {
if (GET_MODE_CLASS (mode) == MODE_INT) if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else if (GET_MODE_CLASS (mode) == MODE_INT)
/* There is no integer SQRT, so only DIV and UDIV can get /* There is no integer SQRT, so only DIV and UDIV can get
here. */ here. */
*cost += extra_cost->mult[mode == DImode].idiv; *cost += extra_cost->mult[mode == DImode].idiv;
...@@ -6404,7 +6525,12 @@ cost_plus: ...@@ -6404,7 +6525,12 @@ cost_plus:
op2 = XEXP (x, 2); op2 = XEXP (x, 2);
if (speed) if (speed)
*cost += extra_cost->fp[mode == DFmode].fma; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->fp[mode == DFmode].fma;
}
/* FMSUB, FNMADD, and FNMSUB are free. */ /* FMSUB, FNMADD, and FNMSUB are free. */
if (GET_CODE (op0) == NEG) if (GET_CODE (op0) == NEG)
...@@ -6450,12 +6576,28 @@ cost_plus: ...@@ -6450,12 +6576,28 @@ cost_plus:
case FLOAT_EXTEND: case FLOAT_EXTEND:
if (speed) if (speed)
*cost += extra_cost->fp[mode == DFmode].widen; {
if (VECTOR_MODE_P (mode))
{
/*Vector truncate. */
*cost += extra_cost->vect.alu;
}
else
*cost += extra_cost->fp[mode == DFmode].widen;
}
return false; return false;
case FLOAT_TRUNCATE: case FLOAT_TRUNCATE:
if (speed) if (speed)
*cost += extra_cost->fp[mode == DFmode].narrow; {
if (VECTOR_MODE_P (mode))
{
/*Vector conversion. */
*cost += extra_cost->vect.alu;
}
else
*cost += extra_cost->fp[mode == DFmode].narrow;
}
return false; return false;
case FIX: case FIX:
...@@ -6476,13 +6618,23 @@ cost_plus: ...@@ -6476,13 +6618,23 @@ cost_plus:
} }
if (speed) if (speed)
*cost += extra_cost->fp[GET_MODE (x) == DFmode].toint; {
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else
*cost += extra_cost->fp[GET_MODE (x) == DFmode].toint;
}
*cost += rtx_cost (x, (enum rtx_code) code, 0, speed); *cost += rtx_cost (x, (enum rtx_code) code, 0, speed);
return true; return true;
case ABS: case ABS:
if (GET_MODE_CLASS (mode) == MODE_FLOAT) if (VECTOR_MODE_P (mode))
{
/* ABS (vector). */
if (speed)
*cost += extra_cost->vect.alu;
}
else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
{ {
op0 = XEXP (x, 0); op0 = XEXP (x, 0);
...@@ -6515,10 +6667,15 @@ cost_plus: ...@@ -6515,10 +6667,15 @@ cost_plus:
case SMIN: case SMIN:
if (speed) if (speed)
{ {
/* FMAXNM/FMINNM/FMAX/FMIN. if (VECTOR_MODE_P (mode))
TODO: This may not be accurate for all implementations, but *cost += extra_cost->vect.alu;
we do not model this in the cost tables. */ else
*cost += extra_cost->fp[mode == DFmode].addsub; {
/* FMAXNM/FMINNM/FMAX/FMIN.
TODO: This may not be accurate for all implementations, but
we do not model this in the cost tables. */
*cost += extra_cost->fp[mode == DFmode].addsub;
}
} }
return false; return false;
......
gcc/config/arm/aarch-common-protos.h
...@@ -102,6 +102,8 @@ struct mem_cost_table ...@@ -102,6 +102,8 @@ struct mem_cost_table
const int storef; /* SFmode. */ const int storef; /* SFmode. */
const int stored; /* DFmode. */ const int stored; /* DFmode. */
const int store_unaligned; /* Extra for unaligned stores. */ const int store_unaligned; /* Extra for unaligned stores. */
const int loadv; /* Vector load. */
const int storev; /* Vector store. */
}; };
struct fp_cost_table struct fp_cost_table
......
gcc/config/arm/aarch-cost-tables.h
...@@ -81,7 +81,9 @@ const struct cpu_cost_table generic_extra_costs = ...@@ -81,7 +81,9 @@ const struct cpu_cost_table generic_extra_costs =
1, /* stm_regs_per_insn_subsequent. */ 1, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (3), /* stored. */ COSTS_N_INSNS (3), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -182,7 +184,9 @@ const struct cpu_cost_table cortexa53_extra_costs = ...@@ -182,7 +184,9 @@ const struct cpu_cost_table cortexa53_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -283,7 +287,9 @@ const struct cpu_cost_table cortexa57_extra_costs = ...@@ -283,7 +287,9 @@ const struct cpu_cost_table cortexa57_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -385,6 +391,8 @@ const struct cpu_cost_table xgene1_extra_costs = ...@@ -385,6 +391,8 @@ const struct cpu_cost_table xgene1_extra_costs =
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
0, /* store_unaligned. */ 0, /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
......
gcc/config/arm/arm.c
...@@ -1024,7 +1024,9 @@ const struct cpu_cost_table cortexa9_extra_costs = ...@@ -1024,7 +1024,9 @@ const struct cpu_cost_table cortexa9_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (1), /* storef. */ COSTS_N_INSNS (1), /* storef. */
COSTS_N_INSNS (1), /* stored. */ COSTS_N_INSNS (1), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1125,7 +1127,9 @@ const struct cpu_cost_table cortexa8_extra_costs = ...@@ -1125,7 +1127,9 @@ const struct cpu_cost_table cortexa8_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (1), /* storef. */ COSTS_N_INSNS (1), /* storef. */
COSTS_N_INSNS (1), /* stored. */ COSTS_N_INSNS (1), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1227,7 +1231,9 @@ const struct cpu_cost_table cortexa5_extra_costs = ...@@ -1227,7 +1231,9 @@ const struct cpu_cost_table cortexa5_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (2), /* stored. */ COSTS_N_INSNS (2), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1330,7 +1336,9 @@ const struct cpu_cost_table cortexa7_extra_costs = ...@@ -1330,7 +1336,9 @@ const struct cpu_cost_table cortexa7_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (2), /* stored. */ COSTS_N_INSNS (2), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1431,7 +1439,9 @@ const struct cpu_cost_table cortexa12_extra_costs = ...@@ -1431,7 +1439,9 @@ const struct cpu_cost_table cortexa12_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (2), /* stored. */ COSTS_N_INSNS (2), /* stored. */
0 /* store_unaligned. */ 0, /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1532,7 +1542,9 @@ const struct cpu_cost_table cortexa15_extra_costs = ...@@ -1532,7 +1542,9 @@ const struct cpu_cost_table cortexa15_extra_costs =
2, /* stm_regs_per_insn_subsequent. */ 2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */ 0, /* storef. */
0, /* stored. */ 0, /* stored. */
0 /* store_unaligned. */ 0, /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
...@@ -1633,7 +1645,9 @@ const struct cpu_cost_table v7m_extra_costs = ...@@ -1633,7 +1645,9 @@ const struct cpu_cost_table v7m_extra_costs =
1, /* stm_regs_per_insn_subsequent. */ 1, /* stm_regs_per_insn_subsequent. */
COSTS_N_INSNS (2), /* storef. */ COSTS_N_INSNS (2), /* storef. */
COSTS_N_INSNS (3), /* stored. */ COSTS_N_INSNS (3), /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */ COSTS_N_INSNS (1), /* store_unaligned. */
COSTS_N_INSNS (1), /* loadv. */
COSTS_N_INSNS (1) /* storev. */
}, },
{ {
/* FP SFmode */ /* FP SFmode */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment