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Commit b5c2f1d1 by Zack Weinberg Committed by Zack Weinberg
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rtl.def: Reorganize, placing all codes used only in machine descriptions at the end. 

	* rtl.def: Reorganize, placing all codes used only in machine
	descriptions at the end.

From-SVN: r86496
parent 076c7ab8
Showing with 879 additions and 889 deletions
gcc/ChangeLog
2004-08-24 Zack Weinberg <zack@codesourcery.com> 2004-08-24 Zack Weinberg <zack@codesourcery.com>
* rtl.def: Reorganize, placing all codes used only in machine
descriptions at the end.
2004-08-24 Zack Weinberg <zack@codesourcery.com>
* basic-block.h (struct basic_block_def): Reorder fields to * basic-block.h (struct basic_block_def): Reorder fields to
eliminate interior padding. Remove 'partition' field. eliminate interior padding. Remove 'partition' field.
(BB_DISABLE_SCHEDULE, BB_HOT_PARTITION, BB_COLD_PARTITION) (BB_DISABLE_SCHEDULE, BB_HOT_PARTITION, BB_COLD_PARTITION)
......
gcc/rtl.def
...@@ -73,21 +73,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA ...@@ -73,21 +73,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
an rtx code for autoincrement addressing modes (e.g. POST_DEC) an rtx code for autoincrement addressing modes (e.g. POST_DEC)
RTX_EXTRA RTX_EXTRA
everything else everything else
*/
/* --------------------------------------------------------------------- All of the expressions that appear only in machine descriptions,
Expressions (and "meta" expressions) used for structuring the not in RTL used by the compiler itself, are at the end of the file. */
rtl representation of a program.
--------------------------------------------------------------------- */
/* an expression code name unknown to the reader */ /* Unknown, or no such operation; the enumeration constant should have
value zero. */
DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
/* include a file */
DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
/* --------------------------------------------------------------------- /* ---------------------------------------------------------------------
Expressions used in constructing lists. Expressions used in constructing lists.
--------------------------------------------------------------------- */ --------------------------------------------------------------------- */
...@@ -99,1082 +92,1074 @@ DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) ...@@ -99,1082 +92,1074 @@ DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
The insns are represented in print by their uids. */ The insns are represented in print by their uids. */
DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
/* ---------------------------------------------------------------------- /* SEQUENCE appears in the result of a `gen_...' function
Expression types for machine descriptions. for a DEFINE_EXPAND that wants to make several insns.
These do not appear in actual rtl code in the compiler. Its elements are the bodies of the insns that should be made.
---------------------------------------------------------------------- */ `emit_insn' takes the SEQUENCE apart and makes separate insns. */
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
/* Appears only in machine descriptions. /* Refers to the address of its argument. This is only used in alias.c. */
Means use the function named by the second arg (the string) DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
as a predicate; if matched, store the structure that was matched
in the operand table at index specified by the first arg (the integer).
If the second arg is the null string, the structure is just stored.
A third string argument indicates to the register allocator restrictions /* ----------------------------------------------------------------------
on where the operand can be allocated. Expression types used for things in the instruction chain.
If the target needs no restriction on any instruction this field should All formats must start with "iuu" to handle the chain.
be the null string. Each insn expression holds an rtl instruction and its semantics
during back-end processing.
See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
The string is prepended by: ---------------------------------------------------------------------- */
'=' to indicate the operand is only written to.
'+' to indicate the operand is both read and written to.
Each character in the string represents an allocable class for an operand. /* An instruction that cannot jump. */
'g' indicates the operand can be any valid class. DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
'i' indicates the operand can be immediate (in the instruction) data.
'r' indicates the operand can be in a register.
'm' indicates the operand can be in memory.
'o' a subset of the 'm' class. Those memory addressing modes that
can be offset at compile time (have a constant added to them).
Other characters indicate target dependent operand classes and /* An instruction that can possibly jump.
are described in each target's machine description. Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
For instructions with more than one operand, sets of classes can be /* An instruction that can possibly call a subroutine
separated by a comma to indicate the appropriate multi-operand constraints. but which will not change which instruction comes next
There must be a 1 to 1 correspondence between these sets of classes in in the current function.
all operands for an instruction. Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
*/ All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
/* Appears only in machine descriptions. /* A marker that indicates that control will not flow through. */
Means match a SCRATCH or a register. When used to generate rtl, a DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
the desired mode and the first argument is the operand number.
The second argument is the constraint. */
DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
/* Appears only in machine descriptions. /* Holds a label that is followed by instructions.
Means match only something equal to what is stored in the operand table Operand:
at the index specified by the argument. */ 4: is used in jump.c for the use-count of the label.
DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 5: is used in flow.c to point to the chain of label_ref's to this label.
6: is a number that is unique in the entire compilation.
7: is the user-given name of the label, if any. */
DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
/* Appears only in machine descriptions. #ifdef USE_MAPPED_LOCATION
Means apply a predicate, AND match recursively the operands of the rtx. /* Say where in the code a source line starts, for symbol table's sake.
Operand 0 is the operand-number, as in match_operand. Operand:
Operand 1 is a predicate to apply (as a string, a function name). 4: unused if line number > 0, note-specific data otherwise.
Operand 2 is a vector of expressions, each of which must match 5: line number if > 0, enum note_insn otherwise.
one subexpression of the rtx this construct is matching. */ 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) #else
/* Say where in the code a source line starts, for symbol table's sake.
Operand:
4: filename, if line number > 0, note-specific data otherwise.
5: line number if > 0, enum note_insn otherwise.
6: unique number if line number == note_insn_deleted_label. */
#endif
DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
/* Appears only in machine descriptions. /* ----------------------------------------------------------------------
Means to match a PARALLEL of arbitrary length. The predicate is applied Top level constituents of INSN, JUMP_INSN and CALL_INSN.
to the PARALLEL and the initial expressions in the PARALLEL are matched. ---------------------------------------------------------------------- */
Operand 0 is the operand-number, as in match_operand.
Operand 1 is a predicate to apply to the PARALLEL. /* Conditionally execute code.
Operand 2 is a vector of expressions, each of which must match the Operand 0 is the condition that if true, the code is executed.
corresponding element in the PARALLEL. */ Operand 1 is the code to be executed (typically a SET).
DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
/* Appears only in machine descriptions. Semantics are that there are no side effects if the condition
Means match only something equal to what is stored in the operand table is false. This pattern is created automatically by the if_convert
at the index specified by the argument. For MATCH_OPERATOR. */ pass run after reload or by target-specific splitters. */
DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
/* Appears only in machine descriptions. /* Several operations to be done in parallel (perhaps under COND_EXEC). */
Means match only something equal to what is stored in the operand table DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
at the index specified by the argument. For MATCH_PARALLEL. */
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
/* Appears only in define_predicate/define_special predicate /* A string that is passed through to the assembler as input.
expressions in a machine description. Evaluates true only if the One can obviously pass comments through by using the
operand has an RTX code from the set given by the argument (a assembler comment syntax.
comma-separated list). */ These occur in an insn all by themselves as the PATTERN.
DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH) They also appear inside an ASM_OPERANDS
as a convenient way to hold a string. */
DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
/* Appears only in define_predicate/define_special_predicate expressions #ifdef USE_MAPPED_LOCATION
in a machine description. The argument is a C expression to be injected /* An assembler instruction with operands.
at this point in the predicate formula. */ 1st operand is the instruction template.
DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 2nd operand is the constraint for the output.
3rd operand is the number of the output this expression refers to.
When an insn stores more than one value, a separate ASM_OPERANDS
is made for each output; this integer distinguishes them.
4th is a vector of values of input operands.
5th is a vector of modes and constraints for the input operands.
Each element is an ASM_INPUT containing a constraint string
and whose mode indicates the mode of the input operand.
6th is the source line number. */
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
#else
/* An assembler instruction with operands.
1st operand is the instruction template.
2nd operand is the constraint for the output.
3rd operand is the number of the output this expression refers to.
When an insn stores more than one value, a separate ASM_OPERANDS
is made for each output; this integer distinguishes them.
4th is a vector of values of input operands.
5th is a vector of modes and constraints for the input operands.
Each element is an ASM_INPUT containing a constraint string
and whose mode indicates the mode of the input operand.
6th is the name of the containing source file.
7th is the source line number. */
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
#endif
/* Appears only in machine descriptions. /* A machine-specific operation.
Defines the pattern for one kind of instruction. 1st operand is a vector of operands being used by the operation so that
Operand: any needed reloads can be done.
0: names this instruction. 2nd operand is a unique value saying which of a number of machine-specific
If the name is the null string, the instruction is in the operations is to be performed.
machine description just to be recognized, and will never be emitted by (Note that the vector must be the first operand because of the way that
the tree to rtl expander. genrecog.c record positions within an insn.)
1: is the pattern. This can occur all by itself in a PATTERN, as a component of a PARALLEL,
2: is a string which is a C expression or inside an expression. */
giving an additional condition for recognizing this pattern. DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
A null string means no extra condition.
3: is the action to execute if this pattern is matched.
If this assembler code template starts with a * then it is a fragment of
C code to run to decide on a template to use. Otherwise, it is the
template to use.
4: optionally, a vector of attributes for this insn.
*/
DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
/* Definition of a peephole optimization. /* Similar, but a volatile operation and one which may trap. */
1st operand: vector of insn patterns to match DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
2nd operand: C expression that must be true
3rd operand: template or C code to produce assembler output.
4: optionally, a vector of attributes for this insn.
*/
DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
/* Definition of a split operation. /* Vector of addresses, stored as full words. */
1st operand: insn pattern to match /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
2nd operand: C expression that must be true DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
3rd operand: vector of insn patterns to place into a SEQUENCE
4th operand: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
elements of `recog_data.operand' for use by the vector of
insn-patterns.
(`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
/* Definition of an insn and associated split. /* Vector of address differences X0 - BASE, X1 - BASE, ...
This is the concatenation, with a few modifications, of a define_insn First operand is BASE; the vector contains the X's.
and a define_split which share the same pattern. The machine mode of this rtx says how much space to leave
Operand: for each difference and is adjusted by branch shortening if
0: names this instruction. CASE_VECTOR_SHORTEN_MODE is defined.
If the name is the null string, the instruction is in the The third and fourth operands store the target labels with the
machine description just to be recognized, and will never be emitted by minimum and maximum addresses respectively.
the tree to rtl expander. The fifth operand stores flags for use by branch shortening.
1: is the pattern. Set at the start of shorten_branches:
2: is a string which is a C expression min_align: the minimum alignment for any of the target labels.
giving an additional condition for recognizing this pattern. base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
A null string means no extra condition. min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
3: is the action to execute if this pattern is matched. max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
If this assembler code template starts with a * then it is a fragment of min_after_base: true iff minimum address target label is after BASE.
C code to run to decide on a template to use. Otherwise, it is the max_after_base: true iff maximum address target label is after BASE.
template to use. Set by the actual branch shortening process:
4: C expression that must be true for split. This may start with "&&" offset_unsigned: true iff offsets have to be treated as unsigned.
in which case the split condition is the logical and of the insn scale: scaling that is necessary to make offsets fit into the mode.
condition and what follows the "&&" of this operand.
5: vector of insn patterns to place into a SEQUENCE
6: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
elements of `recog_data.operand' for use by the vector of
insn-patterns.
(`operands' is an alias here for `recog_data.operand').
7: optionally, a vector of attributes for this insn. */
DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
/* Definition of an RTL peephole operation. The third, fourth and fifth operands are only valid when
Follows the same arguments as define_split. */ CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) compilations. */
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
/* Define how to generate multiple insns for a standard insn name. /* Memory prefetch, with attributes supported on some targets.
1st operand: the insn name. Operand 1 is the address of the memory to fetch.
2nd operand: vector of insn-patterns. Operand 2 is 1 for a write access, 0 otherwise.
Use match_operand to substitute an element of `recog_data.operand'. Operand 3 is the level of temporal locality; 0 means there is no
3rd operand: C expression that must be true for this to be available. temporal locality and 1, 2, and 3 are for increasing levels of temporal
This may not test any operands. locality.
4th operand: Extra C code to execute before generating the insns.
This might, for example, create some RTX's and store them in
elements of `recog_data.operand' for use by the vector of
insn-patterns.
(`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
/* Define a requirement for delay slots.
1st operand: Condition involving insn attributes that, if true,
indicates that the insn requires the number of delay slots
shown.
2nd operand: Vector whose length is the three times the number of delay
slots required.
Each entry gives three conditions, each involving attributes.
The first must be true for an insn to occupy that delay slot
location. The second is true for all insns that can be
annulled if the branch is true and the third is true for all
insns that can be annulled if the branch is false.
Multiple DEFINE_DELAYs may be present. They indicate differing The attributes specified by operands 2 and 3 are ignored for targets
requirements for delay slots. */ whose prefetch instructions do not support them. */
DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
/* Define attribute computation for `asm' instructions. */ /* ----------------------------------------------------------------------
DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) At the top level of an instruction (perhaps under PARALLEL).
---------------------------------------------------------------------- */
/* Definition of a conditional execution meta operation. Automatically /* Assignment.
generates new instances of DEFINE_INSN, selected by having attribute Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
"predicable" true. The new pattern will contain a COND_EXEC and the Operand 2 is the value stored there.
predicate at top-level. ALL assignment must use SET.
Instructions that do multiple assignments must use multiple SET,
under PARALLEL. */
DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
Operand: /* Indicate something is used in a way that we don't want to explain.
0: The predicate pattern. The top-level form should match a For example, subroutine calls will use the register
relational operator. Operands should have only one alternative. in which the static chain is passed. */
1: A C expression giving an additional condition for recognizing DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
the generated pattern.
2: A template or C code to produce assembler output. */
DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
/* Definition of an operand predicate. The difference between /* Indicate something is clobbered in a way that we don't want to explain.
DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will For example, subroutine calls will clobber some physical registers
not warn about a match_operand with no mode if it has a predicate (the ones that are by convention not saved). */
defined with DEFINE_SPECIAL_PREDICATE. DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
Operand: /* Call a subroutine.
0: The name of the predicate. Operand 1 is the address to call.
1: A boolean expression which computes whether or not the predicate Operand 2 is the number of arguments. */
matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
can calculate the set of RTX codes that can possibly match.
2: A C function body which must return true for the predicate to match.
Optional. Use this when the test is too complicated to fit into a
match_test expression. */
DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
/* SEQUENCE appears in the result of a `gen_...' function DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
for a DEFINE_EXPAND that wants to make several insns.
Its elements are the bodies of the insns that should be made.
`emit_insn' takes the SEQUENCE apart and makes separate insns. */
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
/* Refers to the address of its argument. This is only used in alias.c. */ /* Return from a subroutine. */
DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
/* Conditional trap.
Operand 1 is the condition.
Operand 2 is the trap code.
For an unconditional trap, make the condition (const_int 1). */
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
/* Placeholder for _Unwind_Resume before we know if a function call
or a branch is needed. Operand 1 is the exception region from
which control is flowing. */
DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
Constructions for CPU pipeline description described by NDFAs. Primitive values for use in expressions.
These do not appear in actual rtl code in the compiler.
---------------------------------------------------------------------- */ ---------------------------------------------------------------------- */
/* (define_cpu_unit string [string]) describes cpu functional /* numeric integer constant */
units (separated by comma). DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
1st operand: Names of cpu functional units. /* numeric floating point constant.
2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). Operands hold the value. They are all 'w' and there may be from 2 to 6;
see real.h. */
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
All define_reservations, define_cpu_units, and /* Describes a vector constant. */
define_query_cpu_units should have unique names which may not be DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA)
"nothing". */
DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
/* (define_query_cpu_unit string [string]) describes cpu functional /* String constant. Used for attributes in machine descriptions and
units analogously to define_cpu_unit. The reservation of such for special cases in DWARF2 debug output. NOT used for source-
units can be queried for automaton state. */ language string constants. */
DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
/* (exclusion_set string string) means that each CPU functional unit /* This is used to encapsulate an expression whose value is constant
in the first string can not be reserved simultaneously with any (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
unit whose name is in the second string and vise versa. CPU units recognized as a constant operand rather than by arithmetic instructions. */
in the string are separated by commas. For example, it is useful
for description CPU with fully pipelined floating point functional
unit which can execute simultaneously only single floating point
insns or only double floating point insns. All CPU functional
units in a set should belong to the same automaton. */
DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
/* (presence_set string string) means that each CPU functional unit in DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
the first string can not be reserved unless at least one of pattern
of units whose names are in the second string is reserved. This is
an asymmetric relation. CPU units or unit patterns in the strings
are separated by commas. Pattern is one unit name or unit names
separated by white-spaces.
For example, it is useful for description that slot1 is reserved
after slot0 reservation for a VLIW processor. We could describe it
by the following construction
(presence_set "slot1" "slot0") /* program counter. Ordinary jumps are represented
by a SET whose first operand is (PC). */
DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
Or slot1 is reserved only after slot0 and unit b0 reservation. In /* Used in the cselib routines to describe a value. */
this case we could write DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
(presence_set "slot1" "slot0 b0") /* A register. The "operand" is the register number, accessed with
the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
than a hardware register is being referred to. The second operand
holds the original register number - this will be different for a
pseudo register that got turned into a hard register.
This rtx needs to have as many (or more) fields as a MEM, since we
can change REG rtx's into MEMs during reload. */
DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
All CPU functional units in a set should belong to the same /* A scratch register. This represents a register used only within a
automaton. */ single insn. It will be turned into a REG during register allocation
DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) or reload unless the constraint indicates that the register won't be
needed, in which case it can remain a SCRATCH. This code is
marked as having one operand so it can be turned into a REG. */
DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
/* (final_presence_set string string) is analogous to `presence_set'. /* One word of a multi-word value.
The difference between them is when checking is done. When an The first operand is the complete value; the second says which word.
instruction is issued in given automaton state reflecting all The WORDS_BIG_ENDIAN flag controls whether word number 0
current and planned unit reservations, the automaton state is (as numbered in a SUBREG) is the most or least significant word.
changed. The first state is a source state, the second one is a
result state. Checking for `presence_set' is done on the source
state reservation, checking for `final_presence_set' is done on the
result reservation. This construction is useful to describe a
reservation which is actually two subsequent reservations. For
example, if we use
(presence_set "slot1" "slot0") This is also used to refer to a value in a different machine mode.
For example, it can be used to refer to a SImode value as if it were
Qimode, or vice versa. Then the word number is always 0. */
DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
the following insn will be never issued (because slot1 requires /* This one-argument rtx is used for move instructions
slot0 which is absent in the source state). that are guaranteed to alter only the low part of a destination.
Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
has an unspecified effect on the high part of REG,
but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
is guaranteed to alter only the bits of REG that are in HImode.
(define_reservation "insn_and_nop" "slot0 + slot1") The actual instruction used is probably the same in both cases,
but the register constraints may be tighter when STRICT_LOW_PART
is in use. */
but it can be issued if we use analogous `final_presence_set'. */ DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
/* (absence_set string string) means that each CPU functional unit in /* (CONCAT a b) represents the virtual concatenation of a and b
the first string can be reserved only if each pattern of units to make a value that has as many bits as a and b put together.
whose names are in the second string is not reserved. This is an This is used for complex values. Normally it appears only
asymmetric relation (actually exclusion set is analogous to this in DECL_RTLs and during RTL generation, but not in the insn chain. */
one but it is symmetric). CPU units or unit patterns in the string DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
are separated by commas. Pattern is one unit name or unit names
separated by white-spaces.
For example, it is useful for description that slot0 can not be /* A memory location; operand is the address. The second operand is the
reserved after slot1 or slot2 reservation for a VLIW processor. We alias set to which this MEM belongs. We use `0' instead of `w' for this
could describe it by the following construction field so that the field need not be specified in machine descriptions. */
DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
(absence_set "slot2" "slot0, slot1") /* Reference to an assembler label in the code for this function.
The operand is a CODE_LABEL found in the insn chain.
The unprinted fields 1 and 2 are used in flow.c for the
LABEL_NEXTREF and CONTAINING_INSN. */
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ)
Or slot2 can not be reserved if slot0 and unit b0 are reserved or /* Reference to a named label:
slot1 and unit b1 are reserved . In this case we could write Operand 0: label name
Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
Operand 2: tree from which this symbol is derived, or null.
This is either a DECL node, or some kind of constant. */
DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
(absence_set "slot2" "slot0 b0, slot1 b1") /* The condition code register is represented, in our imagination,
as a register holding a value that can be compared to zero.
In fact, the machine has already compared them and recorded the
results; but instructions that look at the condition code
pretend to be looking at the entire value and comparing it. */
DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
All CPU functional units in a set should to belong the same /* ----------------------------------------------------------------------
automaton. */ Expressions for operators in an rtl pattern
DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) ---------------------------------------------------------------------- */
/* (final_absence_set string string) is analogous to `absence_set' but /* if_then_else. This is used in representing ordinary
checking is done on the result (state) reservation. See comments conditional jump instructions.
for `final_presence_set'. */ Operand:
DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 0: condition
1: then expr
/* (define_bypass number out_insn_names in_insn_names) names bypass 2: else expr */
with given latency (the first number) from insns given by the first DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
string (see define_insn_reservation) into insns given by the second
string. Insn names in the strings are separated by commas. The
third operand is optional name of function which is additional
guard for the bypass. The function will get the two insns as
parameters. If the function returns zero the bypass will be
ignored for this case. Additional guard is necessary to recognize
complicated bypasses, e.g. when consumer is load address. */
DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
/* (define_automaton string) describes names of automata generated and
used for pipeline hazards recognition. The names are separated by
comma. Actually it is possibly to generate the single automaton
but unfortunately it can be very large. If we use more one
automata, the summary size of the automata usually is less than the
single one. The automaton name is used in define_cpu_unit and
define_query_cpu_unit. All automata should have unique names. */
DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
/* (automata_option string) describes option for generation of /* Comparison, produces a condition code result. */
automata. Currently there are the following options: DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
o "no-minimization" which makes no minimization of automata. This /* plus */
is only worth to do when we are debugging the description and DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
need to look more accurately at reservations of states.
o "time" which means printing additional time statistics about /* Operand 0 minus operand 1. */
generation of automata. DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
o "v" which means generation of file describing the result
automata. The file has suffix `.dfa' and can be used for the
description verification and debugging.
o "w" which means generation of warning instead of error for /* Minus operand 0. */
non-critical errors. DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
o "ndfa" which makes nondeterministic finite state automata. DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
o "progress" which means output of a progress bar showing how many /* Operand 0 divided by operand 1. */
states were generated so far for automaton being processed. */ DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) /* Remainder of operand 0 divided by operand 1. */
DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
/* (define_reservation string string) names reservation (the first /* Unsigned divide and remainder. */
string) of cpu functional units (the 2nd string). Sometimes unit DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
reservations for different insns contain common parts. In such DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
case, you can describe common part and use its name (the 1st
parameter) in regular expression in define_insn_reservation. All
define_reservations, define_cpu_units, and define_query_cpu_units
should have unique names which may not be "nothing". */
DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
/* (define_insn_reservation name default_latency condition regexpr) /* Bitwise operations. */
describes reservation of cpu functional units (the 3nd operand) for DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
instruction which is selected by the condition (the 2nd parameter).
The first parameter is used for output of debugging information.
The reservations are described by a regular expression according
the following syntax:
regexp = regexp "," oneof DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
| oneof
oneof = oneof "|" allof DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
| allof
allof = allof "+" repeat DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
| repeat
repeat = element "*" number
| element
element = cpu_function_unit_name /* Operand:
| reservation_name 0: value to be shifted.
| result_name 1: number of bits. */
| "nothing" DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
| "(" regexp ")" DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
1. "," is used for describing start of the next cycle in /* Minimum and maximum values of two operands. We need both signed and
reservation. unsigned forms. (We cannot use MIN for SMIN because it conflicts
with a macro of the same name.) */
2. "|" is used for describing the reservation described by the DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
first regular expression *or* the reservation described by the DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
second regular expression *or* etc. DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
3. "+" is used for describing the reservation described by the /* These unary operations are used to represent incrementation
first regular expression *and* the reservation described by the and decrementation as they occur in memory addresses.
second regular expression *and* etc. The amount of increment or decrement are not represented
because they can be understood from the machine-mode of the
containing MEM. These operations exist in only two cases:
1. pushes onto the stack.
2. created automatically by the life_analysis pass in flow.c. */
DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
4. "*" is used for convenience and simply means sequence in /* These binary operations are used to represent generic address
which the regular expression are repeated NUMBER times with side-effects in memory addresses, except for simple incrementation
cycle advancing (see ","). or decrementation which use the above operations. They are
created automatically by the life_analysis pass in flow.c.
The first operand is a REG which is used as the address.
The second operand is an expression that is assigned to the
register, either before (PRE_MODIFY) or after (POST_MODIFY)
evaluating the address.
Currently, the compiler can only handle second operands of the
form (plus (reg) (reg)) and (plus (reg) (const_int)), where
the first operand of the PLUS has to be the same register as
the first operand of the *_MODIFY. */
DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
5. cpu functional unit name which means its reservation. /* Comparison operations. The ordered comparisons exist in two
flavors, signed and unsigned. */
DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
6. reservation name -- see define_reservation. /* Additional floating point unordered comparison flavors. */
DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
7. string "nothing" means no units reservation. */ /* These are equivalent to unordered or ... */
DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
/* ---------------------------------------------------------------------- /* Represents the result of sign-extending the sole operand.
Expressions used for insn attributes. These also do not appear in The machine modes of the operand and of the SIGN_EXTEND expression
actual rtl code in the compiler. determine how much sign-extension is going on. */
---------------------------------------------------------------------- */ DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
/* Definition of an insn attribute. /* Similar for zero-extension (such as unsigned short to int). */
1st operand: name of the attribute DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
2nd operand: comma-separated list of possible attribute values
3rd operand: expression for the default value of the attribute. */
DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
/* Marker for the name of an attribute. */ /* Similar but here the operand has a wider mode. */
DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and /* Similar for extending floating-point values (such as SFmode to DFmode). */
in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
pattern. DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
(set_attr "name" "value") is equivalent to /* Conversion of fixed point operand to floating point value. */
(set (attr "name") (const_string "value")) */ DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to /* With fixed-point machine mode:
specify that attribute values are to be assigned according to the Conversion of floating point operand to fixed point value.
alternative matched. Value is defined only when the operand's value is an integer.
With floating-point machine mode (and operand with same mode):
Operand is rounded toward zero to produce an integer value
represented in floating point. */
DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
The following three expressions are equivalent: /* Conversion of unsigned fixed point operand to floating point value. */
DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
(set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") /* With fixed-point machine mode:
(eq_attrq "alternative" "2") (const_string "a2")] Conversion of floating point operand to *unsigned* fixed point value.
(const_string "a3"))) Value is defined only when the operand's value is an integer. */
(set_attr_alternative "att" [(const_string "a1") (const_string "a2") DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
(const_string "a3")])
(set_attr "att" "a1,a2,a3")
*/
DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
/* A conditional expression true if the value of the specified attribute of /* Absolute value */
the current insn equals the specified value. The first operand is the DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
attribute name and the second is the comparison value. */
DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
/* A special case of the above representing a set of alternatives. The first /* Square root */
operand is bitmap of the set, the second one is the default value. */ DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
/* A conditional expression which is true if the specified flag is /* Find first bit that is set.
true for the insn being scheduled in reorg. Value is 1 + number of trailing zeros in the arg.,
or 0 if arg is 0. */
DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
genattr.c defines the following flags which can be tested by /* Count leading zeros. */
(attr_flag "foo") expressions in eligible_for_delay. DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
forward, backward, very_likely, likely, very_unlikely, and unlikely. */ /* Count trailing zeros. */
DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) /* Population count (number of 1 bits). */
DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
/* ---------------------------------------------------------------------- /* Population parity (number of 1 bits modulo 2). */
Expression types used for things in the instruction chain. DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
All formats must start with "iuu" to handle the chain. /* Reference to a signed bit-field of specified size and position.
Each insn expression holds an rtl instruction and its semantics Operand 0 is the memory unit (usually SImode or QImode) which
during back-end processing. contains the field's first bit. Operand 1 is the width, in bits.
See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. Operand 2 is the number of bits in the memory unit before the
first bit of this field.
If BITS_BIG_ENDIAN is defined, the first bit is the msb and
operand 2 counts from the msb of the memory unit.
Otherwise, the first bit is the lsb and operand 2 counts from
the lsb of the memory unit. */
DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
---------------------------------------------------------------------- */ /* Similar for unsigned bit-field. */
DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
/* An instruction that cannot jump. */ /* For RISC machines. These save memory when splitting insns. */
DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
/* An instruction that can possibly jump. /* HIGH are the high-order bits of a constant expression. */
Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
/* An instruction that can possibly call a subroutine /* LO_SUM is the sum of a register and the low-order bits
but which will not change which instruction comes next of a constant expression. */
in the current function. DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
/* A marker that indicates that control will not flow through. */ /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA) Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
the registers that can be substituted within this range. Operand 3 is the
number of calls in the range. Operand 4 is the number of insns in the
range. Operand 5 is the unique range number for this range. Operand 6 is
the basic block # of the start of the live range. Operand 7 is the basic
block # of the end of the live range. Operand 8 is the loop depth. Operand
9 is a bitmap of the registers live at the start of the range. Operand 10
is a bitmap of the registers live at the end of the range. Operand 11 is
marker number for the start of the range. Operand 12 is the marker number
for the end of the range. */
DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", RTX_EXTRA)
/* Holds a label that is followed by instructions. /* Registers that can be substituted within the range. Operand 0 is the
Operand: original pseudo register number. Operand 1 will be filled in with the
4: is used in jump.c for the use-count of the label. pseudo register the value is copied for the duration of the range. Operand
5: is used in flow.c to point to the chain of label_ref's to this label. 2 is the number of references within the range to the register. Operand 3
6: is a number that is unique in the entire compilation. is the number of sets or clobbers of the register in the range. Operand 4
7: is the user-given name of the label, if any. */ is the number of deaths the register has. Operand 5 is the copy flags that
DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) give the status of whether a copy is needed from the original register to
the new register at the beginning of the range, or whether a copy from the
new register back to the original at the end of the range. Operand 6 is the
live length. Operand 7 is the number of calls that this register is live
across. Operand 8 is the symbol node of the variable if the register is a
user variable. Operand 9 is the block node that the variable is declared
in if the register is a user variable. */
DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", RTX_EXTRA)
#ifdef USE_MAPPED_LOCATION /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
/* Say where in the code a source line starts, for symbol table's sake. the different ranges a variable is in where it is copied to a different
Operand: pseudo register. Operand 1 is the block that the variable is declared in.
4: unused if line number > 0, note-specific data otherwise. Operand 2 is the number of distinct ranges. */
5: line number if > 0, enum note_insn otherwise. DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", RTX_EXTRA)
6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
#else
/* Say where in the code a source line starts, for symbol table's sake.
Operand:
4: filename, if line number > 0, note-specific data otherwise.
5: line number if > 0, enum note_insn otherwise.
6: unique number if line number == note_insn_deleted_label. */
#endif
DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
/* ---------------------------------------------------------------------- /* Information about the registers that are live at the current point. Operand
Top level constituents of INSN, JUMP_INSN and CALL_INSN. 0 is the live bitmap. Operand 1 is the original block number. */
---------------------------------------------------------------------- */ DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", RTX_EXTRA)
/* Conditionally execute code.
Operand 0 is the condition that if true, the code is executed.
Operand 1 is the code to be executed (typically a SET).
Semantics are that there are no side effects if the condition /* Describes a merge operation between two vector values.
is false. This pattern is created automatically by the if_convert Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
pass run after reload or by target-specific splitters. */ that specifies where the parts of the result are taken from. Set bits
DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) indicate operand 0, clear bits indicate operand 1. The parts are defined
by the mode of the vectors. */
DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
/* Several operations to be done in parallel (perhaps under COND_EXEC). */ /* Describes an operation that selects parts of a vector.
DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) Operands 0 is the source vector, operand 1 is a PARALLEL that contains
a CONST_INT for each of the subparts of the result vector, giving the
number of the source subpart that should be stored into it. */
DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
/* A string that is passed through to the assembler as input. /* Describes a vector concat operation. Operands 0 and 1 are the source
One can obviously pass comments through by using the vectors, the result is a vector that is as long as operands 0 and 1
assembler comment syntax. combined and is the concatenation of the two source vectors. */
These occur in an insn all by themselves as the PATTERN. DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
They also appear inside an ASM_OPERANDS
as a convenient way to hold a string. */
DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
#ifdef USE_MAPPED_LOCATION /* Describes an operation that converts a small vector into a larger one by
/* An assembler instruction with operands. duplicating the input values. The output vector mode must have the same
1st operand is the instruction template. submodes as the input vector mode, and the number of output parts must be
2nd operand is the constraint for the output. an integer multiple of the number of input parts. */
3rd operand is the number of the output this expression refers to. DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
When an insn stores more than one value, a separate ASM_OPERANDS
is made for each output; this integer distinguishes them. /* Addition with signed saturation */
4th is a vector of values of input operands. DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
5th is a vector of modes and constraints for the input operands.
Each element is an ASM_INPUT containing a constraint string
and whose mode indicates the mode of the input operand.
6th is the source line number. */
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
#else
/* An assembler instruction with operands.
1st operand is the instruction template.
2nd operand is the constraint for the output.
3rd operand is the number of the output this expression refers to.
When an insn stores more than one value, a separate ASM_OPERANDS
is made for each output; this integer distinguishes them.
4th is a vector of values of input operands.
5th is a vector of modes and constraints for the input operands.
Each element is an ASM_INPUT containing a constraint string
and whose mode indicates the mode of the input operand.
6th is the name of the containing source file.
7th is the source line number. */
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
#endif
/* A machine-specific operation. /* Addition with unsigned saturation */
1st operand is a vector of operands being used by the operation so that DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
any needed reloads can be done.
2nd operand is a unique value saying which of a number of machine-specific
operations is to be performed.
(Note that the vector must be the first operand because of the way that
genrecog.c record positions within an insn.)
This can occur all by itself in a PATTERN, as a component of a PARALLEL,
or inside an expression. */
DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
/* Similar, but a volatile operation and one which may trap. */ /* Operand 0 minus operand 1, with signed saturation. */
DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
/* Vector of addresses, stored as full words. */ /* Operand 0 minus operand 1, with unsigned saturation. */
/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
/* Vector of address differences X0 - BASE, X1 - BASE, ... /* Signed saturating truncate. */
First operand is BASE; the vector contains the X's. DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
The machine mode of this rtx says how much space to leave
for each difference and is adjusted by branch shortening if
CASE_VECTOR_SHORTEN_MODE is defined.
The third and fourth operands store the target labels with the
minimum and maximum addresses respectively.
The fifth operand stores flags for use by branch shortening.
Set at the start of shorten_branches:
min_align: the minimum alignment for any of the target labels.
base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
min_after_base: true iff minimum address target label is after BASE.
max_after_base: true iff maximum address target label is after BASE.
Set by the actual branch shortening process:
offset_unsigned: true iff offsets have to be treated as unsigned.
scale: scaling that is necessary to make offsets fit into the mode.
The third, fourth and fifth operands are only valid when /* Unsigned saturating truncate. */
CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
compilations. */
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
/* Memory prefetch, with attributes supported on some targets. /* Information about the variable and its location. */
Operand 1 is the address of the memory to fetch. DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
Operand 2 is 1 for a write access, 0 otherwise.
Operand 3 is the level of temporal locality; 0 means there is no
temporal locality and 1, 2, and 3 are for increasing levels of temporal
locality.
The attributes specified by operands 2 and 3 are ignored for targets /* All expressions from this point forward appear only in machine
whose prefetch instructions do not support them. */ descriptions. */
DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
/* ---------------------------------------------------------------------- /* Include a secondary machine-description file at this point. */
At the top level of an instruction (perhaps under PARALLEL). DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
---------------------------------------------------------------------- */
/* Assignment. /* Pattern-matching operators: */
Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
Operand 2 is the value stored there.
ALL assignment must use SET.
Instructions that do multiple assignments must use multiple SET,
under PARALLEL. */
DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
/* Indicate something is used in a way that we don't want to explain. /* Use the function named by the second arg (the string)
For example, subroutine calls will use the register as a predicate; if matched, store the structure that was matched
in which the static chain is passed. */ in the operand table at index specified by the first arg (the integer).
DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) If the second arg is the null string, the structure is just stored.
/* Indicate something is clobbered in a way that we don't want to explain. A third string argument indicates to the register allocator restrictions
For example, subroutine calls will clobber some physical registers on where the operand can be allocated.
(the ones that are by convention not saved). */
DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
/* Call a subroutine. If the target needs no restriction on any instruction this field should
Operand 1 is the address to call. be the null string.
Operand 2 is the number of arguments. */
DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) The string is prepended by:
'=' to indicate the operand is only written to.
'+' to indicate the operand is both read and written to.
/* Return from a subroutine. */ Each character in the string represents an allocable class for an operand.
'g' indicates the operand can be any valid class.
'i' indicates the operand can be immediate (in the instruction) data.
'r' indicates the operand can be in a register.
'm' indicates the operand can be in memory.
'o' a subset of the 'm' class. Those memory addressing modes that
can be offset at compile time (have a constant added to them).
DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) Other characters indicate target dependent operand classes and
are described in each target's machine description.
/* Conditional trap. For instructions with more than one operand, sets of classes can be
Operand 1 is the condition. separated by a comma to indicate the appropriate multi-operand constraints.
Operand 2 is the trap code. There must be a 1 to 1 correspondence between these sets of classes in
For an unconditional trap, make the condition (const_int 1). */ all operands for an instruction.
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) */
DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
/* Placeholder for _Unwind_Resume before we know if a function call /* Match a SCRATCH or a register. When used to generate rtl, a
or a branch is needed. Operand 1 is the exception region from SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
which control is flowing. */ the desired mode and the first argument is the operand number.
DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA) The second argument is the constraint. */
DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
/* ---------------------------------------------------------------------- /* Apply a predicate, AND match recursively the operands of the rtx.
Primitive values for use in expressions. Operand 0 is the operand-number, as in match_operand.
---------------------------------------------------------------------- */ Operand 1 is a predicate to apply (as a string, a function name).
Operand 2 is a vector of expressions, each of which must match
one subexpression of the rtx this construct is matching. */
DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
/* numeric integer constant */ /* Match a PARALLEL of arbitrary length. The predicate is applied
DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) to the PARALLEL and the initial expressions in the PARALLEL are matched.
Operand 0 is the operand-number, as in match_operand.
Operand 1 is a predicate to apply to the PARALLEL.
Operand 2 is a vector of expressions, each of which must match the
corresponding element in the PARALLEL. */
DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
/* numeric floating point constant. /* Match only something equal to what is stored in the operand table
Operands hold the value. They are all 'w' and there may be from 2 to 6; at the index specified by the argument. Use with MATCH_OPERAND. */
see real.h. */ DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
/* Describes a vector constant. */ /* Match only something equal to what is stored in the operand table
DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA) at the index specified by the argument. Use with MATCH_OPERATOR. */
DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
/* String constant. Used only for attributes right now. */ /* Match only something equal to what is stored in the operand table
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) at the index specified by the argument. Use with MATCH_PARALLEL. */
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
/* This is used to encapsulate an expression whose value is constant /* Appears only in define_predicate/define_special_predicate
(such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be expressions. Evaluates true only if the operand has an RTX code
recognized as a constant operand rather than by arithmetic instructions. */ from the set given by the argument (a comma-separated list). */
DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH)
DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) /* Appears only in define_predicate/define_special_predicate
expressions. The argument is a C expression to be injected at this
point in the predicate formula. */
DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
/* program counter. Ordinary jumps are represented /* Insn (and related) definitions. */
by a SET whose first operand is (PC). */
DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
/* Used in the cselib routines to describe a value. */ /* Definition of the pattern for one kind of instruction.
DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) Operand:
0: names this instruction.
If the name is the null string, the instruction is in the
machine description just to be recognized, and will never be emitted by
the tree to rtl expander.
1: is the pattern.
2: is a string which is a C expression
giving an additional condition for recognizing this pattern.
A null string means no extra condition.
3: is the action to execute if this pattern is matched.
If this assembler code template starts with a * then it is a fragment of
C code to run to decide on a template to use. Otherwise, it is the
template to use.
4: optionally, a vector of attributes for this insn.
*/
DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
/* A register. The "operand" is the register number, accessed with /* Definition of a peephole optimization.
the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 1st operand: vector of insn patterns to match
than a hardware register is being referred to. The second operand 2nd operand: C expression that must be true
holds the original register number - this will be different for a 3rd operand: template or C code to produce assembler output.
pseudo register that got turned into a hard register. 4: optionally, a vector of attributes for this insn.
This rtx needs to have as many (or more) fields as a MEM, since we
can change REG rtx's into MEMs during reload. */
DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
/* A scratch register. This represents a register used only within a This form is deprecated; use define_peephole2 instead. */
single insn. It will be turned into a REG during register allocation DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
or reload unless the constraint indicates that the register won't be
needed, in which case it can remain a SCRATCH. This code is
marked as having one operand so it can be turned into a REG. */
DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
/* One word of a multi-word value. /* Definition of a split operation.
The first operand is the complete value; the second says which word. 1st operand: insn pattern to match
The WORDS_BIG_ENDIAN flag controls whether word number 0 2nd operand: C expression that must be true
(as numbered in a SUBREG) is the most or least significant word. 3rd operand: vector of insn patterns to place into a SEQUENCE
4th operand: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
elements of `recog_data.operand' for use by the vector of
insn-patterns.
(`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
/* Definition of an insn and associated split.
This is the concatenation, with a few modifications, of a define_insn
and a define_split which share the same pattern.
Operand:
0: names this instruction.
If the name is the null string, the instruction is in the
machine description just to be recognized, and will never be emitted by
the tree to rtl expander.
1: is the pattern.
2: is a string which is a C expression
giving an additional condition for recognizing this pattern.
A null string means no extra condition.
3: is the action to execute if this pattern is matched.
If this assembler code template starts with a * then it is a fragment of
C code to run to decide on a template to use. Otherwise, it is the
template to use.
4: C expression that must be true for split. This may start with "&&"
in which case the split condition is the logical and of the insn
condition and what follows the "&&" of this operand.
5: vector of insn patterns to place into a SEQUENCE
6: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
elements of `recog_data.operand' for use by the vector of
insn-patterns.
(`operands' is an alias here for `recog_data.operand').
7: optionally, a vector of attributes for this insn. */
DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
/* Definition of an RTL peephole operation.
Follows the same arguments as define_split. */
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
/* Define how to generate multiple insns for a standard insn name.
1st operand: the insn name.
2nd operand: vector of insn-patterns.
Use match_operand to substitute an element of `recog_data.operand'.
3rd operand: C expression that must be true for this to be available.
This may not test any operands.
4th operand: Extra C code to execute before generating the insns.
This might, for example, create some RTX's and store them in
elements of `recog_data.operand' for use by the vector of
insn-patterns.
(`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
/* Define a requirement for delay slots.
1st operand: Condition involving insn attributes that, if true,
indicates that the insn requires the number of delay slots
shown.
2nd operand: Vector whose length is the three times the number of delay
slots required.
Each entry gives three conditions, each involving attributes.
The first must be true for an insn to occupy that delay slot
location. The second is true for all insns that can be
annulled if the branch is true and the third is true for all
insns that can be annulled if the branch is false.
This is also used to refer to a value in a different machine mode. Multiple DEFINE_DELAYs may be present. They indicate differing
For example, it can be used to refer to a SImode value as if it were requirements for delay slots. */
Qimode, or vice versa. Then the word number is always 0. */ DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
/* This one-argument rtx is used for move instructions /* Define attribute computation for `asm' instructions. */
that are guaranteed to alter only the low part of a destination. DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
has an unspecified effect on the high part of REG,
but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
is guaranteed to alter only the bits of REG that are in HImode.
The actual instruction used is probably the same in both cases, /* Definition of a conditional execution meta operation. Automatically
but the register constraints may be tighter when STRICT_LOW_PART generates new instances of DEFINE_INSN, selected by having attribute
is in use. */ "predicable" true. The new pattern will contain a COND_EXEC and the
predicate at top-level.
DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) Operand:
0: The predicate pattern. The top-level form should match a
relational operator. Operands should have only one alternative.
1: A C expression giving an additional condition for recognizing
the generated pattern.
2: A template or C code to produce assembler output. */
DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
/* (CONCAT a b) represents the virtual concatenation of a and b /* Definition of an operand predicate. The difference between
to make a value that has as many bits as a and b put together. DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
This is used for complex values. Normally it appears only not warn about a match_operand with no mode if it has a predicate
in DECL_RTLs and during RTL generation, but not in the insn chain. */ defined with DEFINE_SPECIAL_PREDICATE.
DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
/* A memory location; operand is the address. The second operand is the Operand:
alias set to which this MEM belongs. We use `0' instead of `w' for this 0: The name of the predicate.
field so that the field need not be specified in machine descriptions. */ 1: A boolean expression which computes whether or not the predicate
DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
can calculate the set of RTX codes that can possibly match.
2: A C function body which must return true for the predicate to match.
Optional. Use this when the test is too complicated to fit into a
match_test expression. */
DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
/* Reference to an assembler label in the code for this function. /* Constructions for CPU pipeline description described by NDFAs. */
The operand is a CODE_LABEL found in the insn chain.
The unprinted fields 1 and 2 are used in flow.c for the
LABEL_NEXTREF and CONTAINING_INSN. */
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ)
/* Reference to a named label: /* (define_cpu_unit string [string]) describes cpu functional
Operand 0: label name units (separated by comma).
Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
Operand 2: tree from which this symbol is derived, or null.
This is either a DECL node, or some kind of constant. */
DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
/* The condition code register is represented, in our imagination, 1st operand: Names of cpu functional units.
as a register holding a value that can be compared to zero. 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
In fact, the machine has already compared them and recorded the
results; but instructions that look at the condition code
pretend to be looking at the entire value and comparing it. */
DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
/* ---------------------------------------------------------------------- All define_reservations, define_cpu_units, and
Expressions for operators in an rtl pattern define_query_cpu_units should have unique names which may not be
---------------------------------------------------------------------- */ "nothing". */
DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
/* if_then_else. This is used in representing ordinary /* (define_query_cpu_unit string [string]) describes cpu functional
conditional jump instructions. units analogously to define_cpu_unit. The reservation of such
Operand: units can be queried for automaton state. */
0: condition DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1: then expr
2: else expr */
DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
/* General conditional. The first operand is a vector composed of pairs of /* (exclusion_set string string) means that each CPU functional unit
expressions. The first element of each pair is evaluated, in turn. in the first string can not be reserved simultaneously with any
The value of the conditional is the second expression of the first pair unit whose name is in the second string and vise versa. CPU units
whose first expression evaluates nonzero. If none of the expressions is in the string are separated by commas. For example, it is useful
true, the second operand will be used as the value of the conditional. for description CPU with fully pipelined floating point functional
unit which can execute simultaneously only single floating point
insns or only double floating point insns. All CPU functional
units in a set should belong to the same automaton. */
DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
This should be replaced with use of IF_THEN_ELSE. */ /* (presence_set string string) means that each CPU functional unit in
DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) the first string can not be reserved unless at least one of pattern
of units whose names are in the second string is reserved. This is
an asymmetric relation. CPU units or unit patterns in the strings
are separated by commas. Pattern is one unit name or unit names
separated by white-spaces.
For example, it is useful for description that slot1 is reserved
after slot0 reservation for a VLIW processor. We could describe it
by the following construction
/* Comparison, produces a condition code result. */ (presence_set "slot1" "slot0")
DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
/* plus */ Or slot1 is reserved only after slot0 and unit b0 reservation. In
DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) this case we could write
/* Operand 0 minus operand 1. */ (presence_set "slot1" "slot0 b0")
DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
/* Minus operand 0. */ All CPU functional units in a set should belong to the same
DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) automaton. */
DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) /* (final_presence_set string string) is analogous to `presence_set'.
The difference between them is when checking is done. When an
instruction is issued in given automaton state reflecting all
current and planned unit reservations, the automaton state is
changed. The first state is a source state, the second one is a
result state. Checking for `presence_set' is done on the source
state reservation, checking for `final_presence_set' is done on the
result reservation. This construction is useful to describe a
reservation which is actually two subsequent reservations. For
example, if we use
/* Operand 0 divided by operand 1. */ (presence_set "slot1" "slot0")
DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
/* Remainder of operand 0 divided by operand 1. */
DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
/* Unsigned divide and remainder. */ the following insn will be never issued (because slot1 requires
DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) slot0 which is absent in the source state).
DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
/* Bitwise operations. */ (define_reservation "insn_and_nop" "slot0 + slot1")
DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) but it can be issued if we use analogous `final_presence_set'. */
DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) /* (absence_set string string) means that each CPU functional unit in
the first string can be reserved only if each pattern of units
whose names are in the second string is not reserved. This is an
asymmetric relation (actually exclusion set is analogous to this
one but it is symmetric). CPU units or unit patterns in the string
are separated by commas. Pattern is one unit name or unit names
separated by white-spaces.
DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) For example, it is useful for description that slot0 can not be
reserved after slot1 or slot2 reservation for a VLIW processor. We
could describe it by the following construction
/* Operand: (absence_set "slot2" "slot0, slot1")
0: value to be shifted.
1: number of bits. */
DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
/* Minimum and maximum values of two operands. We need both signed and Or slot2 can not be reserved if slot0 and unit b0 are reserved or
unsigned forms. (We cannot use MIN for SMIN because it conflicts slot1 and unit b1 are reserved . In this case we could write
with a macro of the same name.) */
DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) (absence_set "slot2" "slot0 b0, slot1 b1")
DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
/* These unary operations are used to represent incrementation All CPU functional units in a set should to belong the same
and decrementation as they occur in memory addresses. automaton. */
The amount of increment or decrement are not represented DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
because they can be understood from the machine-mode of the
containing MEM. These operations exist in only two cases:
1. pushes onto the stack.
2. created automatically by the life_analysis pass in flow.c. */
DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
/* These binary operations are used to represent generic address /* (final_absence_set string string) is analogous to `absence_set' but
side-effects in memory addresses, except for simple incrementation checking is done on the result (state) reservation. See comments
or decrementation which use the above operations. They are for `final_presence_set'. */
created automatically by the life_analysis pass in flow.c. DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
The first operand is a REG which is used as the address.
The second operand is an expression that is assigned to the
register, either before (PRE_MODIFY) or after (POST_MODIFY)
evaluating the address.
Currently, the compiler can only handle second operands of the
form (plus (reg) (reg)) and (plus (reg) (const_int)), where
the first operand of the PLUS has to be the same register as
the first operand of the *_MODIFY. */
DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
/* Comparison operations. The ordered comparisons exist in two /* (define_bypass number out_insn_names in_insn_names) names bypass
flavors, signed and unsigned. */ with given latency (the first number) from insns given by the first
DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) string (see define_insn_reservation) into insns given by the second
DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) string. Insn names in the strings are separated by commas. The
DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) third operand is optional name of function which is additional
DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) guard for the bypass. The function will get the two insns as
DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) parameters. If the function returns zero the bypass will be
DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) ignored for this case. Additional guard is necessary to recognize
DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) complicated bypasses, e.g. when consumer is load address. */
DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
/* Additional floating point unordered comparison flavors. */ /* (define_automaton string) describes names of automata generated and
DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) used for pipeline hazards recognition. The names are separated by
DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) comma. Actually it is possibly to generate the single automaton
but unfortunately it can be very large. If we use more one
automata, the summary size of the automata usually is less than the
single one. The automaton name is used in define_cpu_unit and
define_query_cpu_unit. All automata should have unique names. */
DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
/* These are equivalent to unordered or ... */ /* (automata_option string) describes option for generation of
DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) automata. Currently there are the following options:
DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ o "no-minimization" which makes no minimization of automata. This
DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) is only worth to do when we are debugging the description and
need to look more accurately at reservations of states.
/* Represents the result of sign-extending the sole operand. o "time" which means printing additional time statistics about
The machine modes of the operand and of the SIGN_EXTEND expression generation of automata.
determine how much sign-extension is going on. */
DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) o "v" which means generation of file describing the result
automata. The file has suffix `.dfa' and can be used for the
description verification and debugging.
/* Similar for zero-extension (such as unsigned short to int). */ o "w" which means generation of warning instead of error for
DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) non-critical errors.
/* Similar but here the operand has a wider mode. */ o "ndfa" which makes nondeterministic finite state automata.
DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
/* Similar for extending floating-point values (such as SFmode to DFmode). */ o "progress" which means output of a progress bar showing how many
DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) states were generated so far for automaton being processed. */
DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
/* Conversion of fixed point operand to floating point value. */ /* (define_reservation string string) names reservation (the first
DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) string) of cpu functional units (the 2nd string). Sometimes unit
reservations for different insns contain common parts. In such
case, you can describe common part and use its name (the 1st
parameter) in regular expression in define_insn_reservation. All
define_reservations, define_cpu_units, and define_query_cpu_units
should have unique names which may not be "nothing". */
DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
/* With fixed-point machine mode: /* (define_insn_reservation name default_latency condition regexpr)
Conversion of floating point operand to fixed point value. describes reservation of cpu functional units (the 3nd operand) for
Value is defined only when the operand's value is an integer. instruction which is selected by the condition (the 2nd parameter).
With floating-point machine mode (and operand with same mode): The first parameter is used for output of debugging information.
Operand is rounded toward zero to produce an integer value The reservations are described by a regular expression according
represented in floating point. */ the following syntax:
DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
/* Conversion of unsigned fixed point operand to floating point value. */ regexp = regexp "," oneof
DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) | oneof
/* With fixed-point machine mode: oneof = oneof "|" allof
Conversion of floating point operand to *unsigned* fixed point value. | allof
Value is defined only when the operand's value is an integer. */
DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
/* Absolute value */ allof = allof "+" repeat
DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) | repeat
repeat = element "*" number
| element
/* Square root */ element = cpu_function_unit_name
DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) | reservation_name
| result_name
| "nothing"
| "(" regexp ")"
/* Find first bit that is set. 1. "," is used for describing start of the next cycle in
Value is 1 + number of trailing zeros in the arg., reservation.
or 0 if arg is 0. */
DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
/* Count leading zeros. */ 2. "|" is used for describing the reservation described by the
DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) first regular expression *or* the reservation described by the
second regular expression *or* etc.
/* Count trailing zeros. */ 3. "+" is used for describing the reservation described by the
DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) first regular expression *and* the reservation described by the
second regular expression *and* etc.
/* Population count (number of 1 bits). */ 4. "*" is used for convenience and simply means sequence in
DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) which the regular expression are repeated NUMBER times with
cycle advancing (see ",").
/* Population parity (number of 1 bits modulo 2). */ 5. cpu functional unit name which means its reservation.
DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
/* Reference to a signed bit-field of specified size and position. 6. reservation name -- see define_reservation.
Operand 0 is the memory unit (usually SImode or QImode) which
contains the field's first bit. Operand 1 is the width, in bits.
Operand 2 is the number of bits in the memory unit before the
first bit of this field.
If BITS_BIG_ENDIAN is defined, the first bit is the msb and
operand 2 counts from the msb of the memory unit.
Otherwise, the first bit is the lsb and operand 2 counts from
the lsb of the memory unit. */
DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
/* Similar for unsigned bit-field. */ 7. string "nothing" means no units reservation. */
DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
/* For RISC machines. These save memory when splitting insns. */ DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
/* HIGH are the high-order bits of a constant expression. */ /* Expressions used for insn attributes. */
DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
/* LO_SUM is the sum of a register and the low-order bits /* Definition of an insn attribute.
of a constant expression. */ 1st operand: name of the attribute
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 2nd operand: comma-separated list of possible attribute values
3rd operand: expression for the default value of the attribute. */
DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn. /* Marker for the name of an attribute. */
Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
the registers that can be substituted within this range. Operand 3 is the
number of calls in the range. Operand 4 is the number of insns in the
range. Operand 5 is the unique range number for this range. Operand 6 is
the basic block # of the start of the live range. Operand 7 is the basic
block # of the end of the live range. Operand 8 is the loop depth. Operand
9 is a bitmap of the registers live at the start of the range. Operand 10
is a bitmap of the registers live at the end of the range. Operand 11 is
marker number for the start of the range. Operand 12 is the marker number
for the end of the range. */
DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", RTX_EXTRA)
/* Registers that can be substituted within the range. Operand 0 is the /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
original pseudo register number. Operand 1 will be filled in with the in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
pseudo register the value is copied for the duration of the range. Operand pattern.
2 is the number of references within the range to the register. Operand 3
is the number of sets or clobbers of the register in the range. Operand 4
is the number of deaths the register has. Operand 5 is the copy flags that
give the status of whether a copy is needed from the original register to
the new register at the beginning of the range, or whether a copy from the
new register back to the original at the end of the range. Operand 6 is the
live length. Operand 7 is the number of calls that this register is live
across. Operand 8 is the symbol node of the variable if the register is a
user variable. Operand 9 is the block node that the variable is declared
in if the register is a user variable. */
DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", RTX_EXTRA)
/* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of (set_attr "name" "value") is equivalent to
the different ranges a variable is in where it is copied to a different (set (attr "name") (const_string "value")) */
pseudo register. Operand 1 is the block that the variable is declared in. DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
Operand 2 is the number of distinct ranges. */
DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", RTX_EXTRA)
/* Information about the registers that are live at the current point. Operand /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
0 is the live bitmap. Operand 1 is the original block number. */ specify that attribute values are to be assigned according to the
DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", RTX_EXTRA) alternative matched.
/* Describes a merge operation between two vector values. The following three expressions are equivalent:
Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
that specifies where the parts of the result are taken from. Set bits
indicate operand 0, clear bits indicate operand 1. The parts are defined
by the mode of the vectors. */
DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
/* Describes an operation that selects parts of a vector. (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
Operands 0 is the source vector, operand 1 is a PARALLEL that contains (eq_attrq "alternative" "2") (const_string "a2")]
a CONST_INT for each of the subparts of the result vector, giving the (const_string "a3")))
number of the source subpart that should be stored into it. */ (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) (const_string "a3")])
(set_attr "att" "a1,a2,a3")
*/
DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
/* Describes a vector concat operation. Operands 0 and 1 are the source /* A conditional expression true if the value of the specified attribute of
vectors, the result is a vector that is as long as operands 0 and 1 the current insn equals the specified value. The first operand is the
combined and is the concatenation of the two source vectors. */ attribute name and the second is the comparison value. */
DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
/* Describes an operation that converts a small vector into a larger one by /* A special case of the above representing a set of alternatives. The first
duplicating the input values. The output vector mode must have the same operand is bitmap of the set, the second one is the default value. */
submodes as the input vector mode, and the number of output parts must be DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
an integer multiple of the number of input parts. */
DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
/* Addition with signed saturation */
DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
/* Addition with unsigned saturation */ /* A conditional expression which is true if the specified flag is
DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) true for the insn being scheduled in reorg.
/* Operand 0 minus operand 1, with signed saturation. */ genattr.c defines the following flags which can be tested by
DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) (attr_flag "foo") expressions in eligible_for_delay.
/* Operand 0 minus operand 1, with unsigned saturation. */ forward, backward, very_likely, likely, very_unlikely, and unlikely. */
DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
/* Signed saturating truncate. */ DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
/* Unsigned saturating truncate. */ /* General conditional. The first operand is a vector composed of pairs of
DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) expressions. The first element of each pair is evaluated, in turn.
The value of the conditional is the second expression of the first pair
whose first expression evaluates nonzero. If none of the expressions is
true, the second operand will be used as the value of the conditional. */
DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
/* Information about the variable and its location. */
DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
/* /*
Local variables: Local variables:
......
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