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riscv-gcc-1
Commit b4d83be3 by Richard Henderson Committed by Richard Henderson
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rx: Cleanup flags generation. 

All arithmetic should only clobber the flags by default;
setting the flags to a useful value should be done by a
separate pattern.

From-SVN: r168924
parent d0acb939
Showing with 277 additions and 68 deletions
gcc/ChangeLog
2011-01-17 Richard Henderson <rth@redhat.com> 2011-01-17 Richard Henderson <rth@redhat.com>
* config/rx/rx.c (rx_match_ccmode): New.
* config/rx/rx-protos.h: Update.
* config/rx/rx.md (abssi2): Clobber, don't set flags.
(addsi3, adddi3, andsi3, negsi2, one_cmplsi2, iorsi3): Likewise.
(rotlsi3, rotrsi3, ashrsi3, lshrsi3, ashlsi3): Likewise.
(subsi3, subdi3, xorsi3, addsf3, divsf3, mulsf3, subsf3): Likewise.
(fix_truncsfsi2, floatsisf2): Likewise.
(*abssi2_flags, *addsi3_flags, *andsi3_flags, *negsi2_flags): New.
(*one_cmplsi2_flags, *iorsi3_flags, *rotlsi3_flags): New.
(*rotrsi3_flags, *ashrsi3_flags, *lshrsi3_flags, *ashlsi3_flags): New.
(*subsi3_flags, *xorsi3_flags): New.
* config/rx/rx.md (cstoresf4, *cstoresf4): New patterns. * config/rx/rx.md (cstoresf4, *cstoresf4): New patterns.
* config/rx/rx.c (rx_print_operand): Remove workaround for * config/rx/rx.c (rx_print_operand): Remove workaround for
......
gcc/config/rx/rx-protos.h
...@@ -42,6 +42,7 @@ extern void rx_notice_update_cc (rtx body, rtx insn); ...@@ -42,6 +42,7 @@ extern void rx_notice_update_cc (rtx body, rtx insn);
extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx); extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx);
extern bool rx_split_fp_compare (Rcode, Rcode *, Rcode *); extern bool rx_split_fp_compare (Rcode, Rcode *, Rcode *);
extern Mmode rx_select_cc_mode (Rcode, rtx, rtx); extern Mmode rx_select_cc_mode (Rcode, rtx, rtx);
extern bool rx_match_ccmode (rtx, Mmode);
#endif #endif
#endif /* GCC_RX_PROTOS_H */ #endif /* GCC_RX_PROTOS_H */
gcc/config/rx/rx.c
...@@ -2755,6 +2755,34 @@ rx_split_cbranch (enum machine_mode cc_mode, enum rtx_code cmp1, ...@@ -2755,6 +2755,34 @@ rx_split_cbranch (enum machine_mode cc_mode, enum rtx_code cmp1,
emit_jump_insn (x); emit_jump_insn (x);
} }
/* A helper function for matching parallels that set the flags. */
bool
rx_match_ccmode (rtx insn, enum machine_mode cc_mode)
{
rtx op1, flags;
enum machine_mode flags_mode;
gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
op1 = XVECEXP (PATTERN (insn), 0, 1);
gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
flags = SET_DEST (op1);
flags_mode = GET_MODE (flags);
if (GET_MODE (SET_SRC (op1)) != flags_mode)
return false;
if (GET_MODE_CLASS (flags_mode) != MODE_CC)
return false;
/* Ensure that the mode of FLAGS is compatible with CC_MODE. */
if (flags_from_mode (flags_mode) & ~flags_from_mode (cc_mode))
return false;
return true;
}
#undef TARGET_FUNCTION_VALUE #undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE rx_function_value #define TARGET_FUNCTION_VALUE rx_function_value
......
gcc/config/rx/rx.md
...@@ -915,9 +915,7 @@ ...@@ -915,9 +915,7 @@
(define_insn "abssi2" (define_insn "abssi2"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(abs:SI (match_operand:SI 1 "register_operand" "0,r"))) (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
(set (reg:CC_ZSO CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZSO (abs:SI (match_dup 1))
(const_int 0)))]
"" ""
"@ "@
abs\t%0 abs\t%0
...@@ -925,13 +923,24 @@ ...@@ -925,13 +923,24 @@
[(set_attr "length" "2,3")] [(set_attr "length" "2,3")]
) )
(define_insn "*abssi2_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(abs:SI (match_operand:SI 1 "register_operand" "0,r")))
(set (reg CC_REG)
(compare (abs:SI (match_dup 1))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSOmode)"
"@
abs\t%0
abs\t%1, %0"
[(set_attr "length" "2,3")]
)
(define_insn "addsi3" (define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
(set (reg:CC_ZSC CC_REG) ;; See subsi3 (clobber (reg:CC CC_REG))]
(compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
add\t%2, %0 add\t%2, %0
...@@ -952,14 +961,39 @@ ...@@ -952,14 +961,39 @@
(set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
) )
(define_insn "*addsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
(set (reg CC_REG)
(compare (plus:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
"@
add\t%2, %0
add\t%2, %0
sub\t%N2, %0
add\t%2, %0
add\t%2, %0
add\t%2, %0
add\t%2, %0
add\t%1, %0
add\t%2, %1, %0
add\t%2, %1, %0
add\t%2, %1, %0
add\t%2, %1, %0
add\t%2, %1, %0
add\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
(set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
)
(define_insn "adddi3" (define_insn "adddi3"
[(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r") [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
(plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0") (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0")
(match_operand:DI 2 "rx_source_operand" (match_operand:DI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q"))) "r,Sint08,Sint16,Sint24,i,Q")))
(set (reg:CC_ZSC CC_REG) ;; See subsi3 (clobber (reg:CC CC_REG))]
(compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"add\t%L2, %L0\n\tadc\t%H2, %H0" "add\t%L2, %L0\n\tadc\t%H2, %H0"
[(set_attr "timings" "22,22,22,22,22,44") [(set_attr "timings" "22,22,22,22,22,44")
...@@ -970,9 +1004,7 @@ ...@@ -970,9 +1004,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
and\t%2, %0 and\t%2, %0
...@@ -988,6 +1020,28 @@ ...@@ -988,6 +1020,28 @@
(set_attr "length" "2,2,3,4,5,6,2,5,5")] (set_attr "length" "2,2,3,4,5,6,2,5,5")]
) )
(define_insn "*andsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
(set (reg CC_REG)
(compare (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
and\t%2, %0
and\t%2, %0
and\t%2, %0
and\t%2, %0
and\t%2, %0
and\t%2, %0
and\t%1, %0
and\t%2, %1, %0
and\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,11,11,11,33,33")
(set_attr "length" "2,2,3,4,5,6,2,5,5")]
)
;; Byte swap (single 32-bit value). ;; Byte swap (single 32-bit value).
(define_insn "bswapsi2" (define_insn "bswapsi2"
[(set (match_operand:SI 0 "register_operand" "+r") [(set (match_operand:SI 0 "register_operand" "+r")
...@@ -1107,12 +1161,23 @@ ...@@ -1107,12 +1161,23 @@
(define_insn "negsi2" (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(neg:SI (match_operand:SI 1 "register_operand" "0,r"))) (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
(set (reg:CC CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC (neg:SI (match_dup 1)) ""
"@
neg\t%0
neg\t%1, %0"
[(set_attr "length" "2,3")]
)
;; Note that the O and C flags are not set as per a normal compare,
;; and thus are unusable in that context.
(define_insn "*negsi2_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(neg:SI (match_operand:SI 1 "register_operand" "0,r")))
(set (reg CC_REG)
(compare (neg:SI (match_dup 1))
(const_int 0)))] (const_int 0)))]
;; The NEG instruction does not comply with -fwrapv semantics. "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
;; See gcc.c-torture/execute/pr22493-1.c for an example of this.
"! flag_wrapv"
"@ "@
neg\t%0 neg\t%0
neg\t%1, %0" neg\t%1, %0"
...@@ -1122,9 +1187,7 @@ ...@@ -1122,9 +1187,7 @@
(define_insn "one_cmplsi2" (define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(not:SI (match_operand:SI 1 "register_operand" "0,r"))) (not:SI (match_operand:SI 1 "register_operand" "0,r")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (not:SI (match_dup 1))
(const_int 0)))]
"" ""
"@ "@
not\t%0 not\t%0
...@@ -1132,13 +1195,24 @@ ...@@ -1132,13 +1195,24 @@
[(set_attr "length" "2,3")] [(set_attr "length" "2,3")]
) )
(define_insn "*one_cmplsi2_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(not:SI (match_operand:SI 1 "register_operand" "0,r")))
(set (reg CC_REG)
(compare (not:SI (match_dup 1))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
not\t%0
not\t%1, %0"
[(set_attr "length" "2,3")]
)
(define_insn "iorsi3" (define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
or\t%2, %0 or\t%2, %0
...@@ -1154,37 +1228,77 @@ ...@@ -1154,37 +1228,77 @@
(set_attr "length" "2,2,3,4,5,6,2,3,5")] (set_attr "length" "2,2,3,4,5,6,2,3,5")]
) )
(define_insn "*iorsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
(set (reg CC_REG)
(compare (ior:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
or\t%2, %0
or\t%2, %0
or\t%2, %0
or\t%2, %0
or\t%2, %0
or\t%Q2, %0
or\t%1, %0
or\t%2, %1, %0
or\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,11,11,11,11,33")
(set_attr "length" "2,2,3,4,5,6,2,3,5")]
)
(define_insn "rotlsi3" (define_insn "rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "0") (rotate:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "rx_shift_operand" "rn"))) (match_operand:SI 2 "rx_shift_operand" "rn")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"rotl\t%2, %0" "rotl\t%2, %0"
[(set_attr "length" "3")] [(set_attr "length" "3")]
) )
(define_insn "*rotlsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "rx_shift_operand" "rn")))
(set (reg CC_REG)
(compare (rotate:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"rotl\t%2, %0"
[(set_attr "length" "3")]
)
(define_insn "rotrsi3" (define_insn "rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "0") (rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "rx_shift_operand" "rn"))) (match_operand:SI 2 "rx_shift_operand" "rn")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"rotr\t%2, %0" "rotr\t%2, %0"
[(set_attr "length" "3")] [(set_attr "length" "3")]
) )
(define_insn "*rotrsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "rx_shift_operand" "rn")))
(set (reg CC_REG)
(compare (rotatert:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"rotr\t%2, %0"
[(set_attr "length" "3")]
)
(define_insn "ashrsi3" (define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n"))) (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
shar\t%2, %0 shar\t%2, %0
...@@ -1193,13 +1307,26 @@ ...@@ -1193,13 +1307,26 @@
[(set_attr "length" "3,2,3")] [(set_attr "length" "3,2,3")]
) )
(define_insn "*ashrsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
(set (reg CC_REG)
(compare (ashiftrt:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
shar\t%2, %0
shar\t%2, %0
shar\t%2, %1, %0"
[(set_attr "length" "3,2,3")]
)
(define_insn "lshrsi3" (define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n"))) (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
shlr\t%2, %0 shlr\t%2, %0
...@@ -1208,13 +1335,26 @@ ...@@ -1208,13 +1335,26 @@
[(set_attr "length" "3,2,3")] [(set_attr "length" "3,2,3")]
) )
(define_insn "*lshrsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
(set (reg CC_REG)
(compare (lshiftrt:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
shlr\t%2, %0
shlr\t%2, %0
shlr\t%2, %1, %0"
[(set_attr "length" "3,2,3")]
)
(define_insn "ashlsi3" (define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r") (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n"))) (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
shll\t%2, %0 shll\t%2, %0
...@@ -1223,16 +1363,26 @@ ...@@ -1223,16 +1363,26 @@
[(set_attr "length" "3,2,3")] [(set_attr "length" "3,2,3")]
) )
(define_insn "*ashlsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
(match_operand:SI 2 "rx_shift_operand" "r,n,n")))
(set (reg CC_REG)
(compare (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"@
shll\t%2, %0
shll\t%2, %0
shll\t%2, %1, %0"
[(set_attr "length" "3,2,3")]
)
(define_insn "subsi3" (define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))) (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
(set (reg:CC_ZSC CC_REG) (clobber (reg:CC CC_REG))]
;; Note - we do not acknowledge that the SUB instruction sets the Overflow
;; flag because its interpretation is different from comparing the result
;; against zero. Compile and run gcc.c-torture/execute/cmpsi-1.c to see this.
(compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"@ "@
sub\t%2, %0 sub\t%2, %0
...@@ -1244,13 +1394,31 @@ ...@@ -1244,13 +1394,31 @@
(set_attr "length" "2,2,6,3,5")] (set_attr "length" "2,2,6,3,5")]
) )
;; Note that the O flag is set as if (compare op1 op2) not for
;; what is described here, (compare op0 0).
(define_insn "*subsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
(match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
(set (reg CC_REG)
(compare (minus:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
"@
sub\t%2, %0
sub\t%2, %0
add\t%N2, %0
sub\t%2, %1, %0
sub\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,33")
(set_attr "length" "2,2,6,3,5")]
)
(define_insn "subdi3" (define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=r,r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(minus:DI (match_operand:DI 1 "register_operand" "0,0") (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "rx_source_operand" "r,Q"))) (match_operand:DI 2 "rx_source_operand" "r,Q")))
(set (reg:CC_ZSC CC_REG) ;; See subsi3 (clobber (reg:CC CC_REG))]
(compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"sub\t%L2, %L0\n\tsbb\t%H2, %H0" "sub\t%L2, %L0\n\tsbb\t%H2, %H0"
[(set_attr "timings" "22,44") [(set_attr "timings" "22,44")
...@@ -1262,24 +1430,34 @@ ...@@ -1262,24 +1430,34 @@
(xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
(match_operand:SI 2 "rx_source_operand" (match_operand:SI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q"))) "r,Sint08,Sint16,Sint24,i,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"" ""
"xor\t%Q2, %0" "xor\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,11,33") [(set_attr "timings" "11,11,11,11,11,33")
(set_attr "length" "3,4,5,6,7,6")] (set_attr "length" "3,4,5,6,7,6")]
) )
(define_insn "*xorsi3_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
(match_operand:SI 2 "rx_source_operand"
"r,Sint08,Sint16,Sint24,i,Q")))
(set (reg CC_REG)
(compare (xor:SI (match_dup 1) (match_dup 2))
(const_int 0)))]
"reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
"xor\t%Q2, %0"
[(set_attr "timings" "11,11,11,11,11,33")
(set_attr "length" "3,4,5,6,7,6")]
)
;; Floating Point Instructions ;; Floating Point Instructions
(define_insn "addsf3" (define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=r,r,r") [(set (match_operand:SF 0 "register_operand" "=r,r,r")
(plus:SF (match_operand:SF 1 "register_operand" "%0,0,0") (plus:SF (match_operand:SF 1 "register_operand" "%0,0,0")
(match_operand:SF 2 "rx_source_operand" "r,F,Q"))) (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2))
(const_int 0)))]
"ALLOW_RX_FPU_INSNS" "ALLOW_RX_FPU_INSNS"
"fadd\t%2, %0" "fadd\t%2, %0"
[(set_attr "timings" "44,44,66") [(set_attr "timings" "44,44,66")
...@@ -1290,9 +1468,7 @@ ...@@ -1290,9 +1468,7 @@
[(set (match_operand:SF 0 "register_operand" "=r,r,r") [(set (match_operand:SF 0 "register_operand" "=r,r,r")
(div:SF (match_operand:SF 1 "register_operand" "0,0,0") (div:SF (match_operand:SF 1 "register_operand" "0,0,0")
(match_operand:SF 2 "rx_source_operand" "r,F,Q"))) (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (div:SF (match_dup 1) (match_dup 2))
(const_int 0)))]
"ALLOW_RX_FPU_INSNS" "ALLOW_RX_FPU_INSNS"
"fdiv\t%2, %0" "fdiv\t%2, %0"
[(set_attr "timings" "1616,1616,1818") [(set_attr "timings" "1616,1616,1818")
...@@ -1303,9 +1479,7 @@ ...@@ -1303,9 +1479,7 @@
[(set (match_operand:SF 0 "register_operand" "=r,r,r") [(set (match_operand:SF 0 "register_operand" "=r,r,r")
(mult:SF (match_operand:SF 1 "register_operand" "%0,0,0") (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
(match_operand:SF 2 "rx_source_operand" "r,F,Q"))) (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2))
(const_int 0)))]
"ALLOW_RX_FPU_INSNS" "ALLOW_RX_FPU_INSNS"
"fmul\t%2, %0" "fmul\t%2, %0"
[(set_attr "timings" "33,33,55") [(set_attr "timings" "33,33,55")
...@@ -1316,9 +1490,7 @@ ...@@ -1316,9 +1490,7 @@
[(set (match_operand:SF 0 "register_operand" "=r,r,r") [(set (match_operand:SF 0 "register_operand" "=r,r,r")
(minus:SF (match_operand:SF 1 "register_operand" "0,0,0") (minus:SF (match_operand:SF 1 "register_operand" "0,0,0")
(match_operand:SF 2 "rx_source_operand" "r,F,Q"))) (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2))
(const_int 0)))]
"ALLOW_RX_FPU_INSNS" "ALLOW_RX_FPU_INSNS"
"fsub\t%Q2, %0" "fsub\t%Q2, %0"
[(set_attr "timings" "44,44,66") [(set_attr "timings" "44,44,66")
...@@ -1328,9 +1500,7 @@ ...@@ -1328,9 +1500,7 @@
(define_insn "fix_truncsfsi2" (define_insn "fix_truncsfsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q"))) (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (fix:SI (match_dup 1))
(const_int 0)))]
"ALLOW_RX_FPU_INSNS" "ALLOW_RX_FPU_INSNS"
"ftoi\t%Q1, %0" "ftoi\t%Q1, %0"
[(set_attr "timings" "22,44") [(set_attr "timings" "22,44")
...@@ -1340,9 +1510,7 @@ ...@@ -1340,9 +1510,7 @@
(define_insn "floatsisf2" (define_insn "floatsisf2"
[(set (match_operand:SF 0 "register_operand" "=r,r") [(set (match_operand:SF 0 "register_operand" "=r,r")
(float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q"))) (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
(set (reg:CC_ZS CC_REG) (clobber (reg:CC CC_REG))]
(compare:CC_ZS (float:SF (match_dup 1))
(const_int 0)))]
"ALLOW_RX_FPU_INSNS" "ALLOW_RX_FPU_INSNS"
"itof\t%Q1, %0" "itof\t%Q1, %0"
[(set_attr "timings" "22,44") [(set_attr "timings" "22,44")
......
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