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riscv-gcc-1
Commit b3fe4634 by Richard Stallman
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Handle CCEVENmode as a new mode. 

Handle CCEVENmode as a new mode.  Logical operations
on CCmode registers now results in CCEVENmode.
Add patterns for jumps and ext's for CCEVENmode.
(cmpsf, cmpdf): Use reg 65 and clobber reg 64.

From-SVN: r6032
parent 347da86b
Showing with 443 additions and 73 deletions
gcc/config/m88k/m88k.md
;;- Machine description for the Motorola 88000 for GNU C compiler
;; Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc.
;; Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc.
;; Contributed by Michael Tiemann (tiemann@mcc.com)
;; Additional changes by Michael Meissner (meissner@osf.org)
;; Version 2 port by Tom Wood (Tom_Wood@NeXT.com)
......@@ -397,6 +397,7 @@
;; We define all logical operations on CCmode values to preserve the pairwise
;; relationship of the compare bits. This allows a future branch prediction
;; pass the degree of freedom needed to change and/bb0-le into or/bb1-gt.
;; THIS IS CURRENTLY FALSE!
;;
;; Opportunities arise when conditional expressions using && and || are made
;; unconditional. When these are used to branch, the sequence is
......@@ -419,21 +420,21 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (neg:SI
(match_operator 1 "relop"
[(match_operand:CC 2 "register_operand" "%r")
(match_operator 1 "even_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "relop"
[(match_operand:CC 4 "register_operand" "r")
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
(ior:CC (match_dup 4)
(ior:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
"operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
; /* The conditions match. */
else if (GET_CODE (operands[1])
......@@ -456,43 +457,140 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operator 1 "relop"
[(match_operand:CC 2 "register_operand" "%r")
(ior:SI (neg:SI
(match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "odd_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
(and:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
; /* The conditions match. */
else
{
/* Make the condition pairs line up by rotating the compare word. */
int cv1 = condition_value (operands[1]);
int cv2 = condition_value (operands[3]);
operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
gen_rtx (CONST_INT, VOIDmode,
(cv2 - cv1) & 0x1f));
}")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (neg:SI
(match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "even_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
(ior:CCEVEN (not:CC (match_dup 2))
(match_dup 4)))
(set (match_dup 0)
(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1])
== reverse_condition (GET_CODE (operands[3])))
;
else
{
/* Make the condition pairs line up by rotating the compare word. */
int cv1 = condition_value (operands[1]);
int cv2 = condition_value (operands[3]);
operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
gen_rtx (CONST_INT, VOIDmode,
((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
}")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operator 1 "even_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "relop"
[(match_operand:CC 4 "register_operand" "r")
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == GET_CODE (operands[3])
|| GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
[(set (match_dup 5)
(ior:CC (match_dup 4)
(ior:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
"operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
/* Reverse the condition by complimenting the compare word. */
if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "odd_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == GET_CODE (operands[3])"
[(set (match_dup 5)
(and:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "even_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
[(set (match_dup 5)
(ior:CCEVEN (not:CC (match_dup 4))
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (neg:SI
(match_operator 1 "relop"
[(match_operand:CC 2 "register_operand" "%r")
(match_operator 1 "even_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "relop"
[(match_operand:CC 4 "register_operand" "r")
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
(and:CC (match_dup 4)
(and:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
"operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
; /* The conditions match. */
else if (GET_CODE (operands[1])
......@@ -504,7 +602,6 @@
/* Make the condition pairs line up by rotating the compare word. */
int cv1 = condition_value (operands[1]);
int cv2 = condition_value (operands[3]);
operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
gen_rtx (CONST_INT, VOIDmode,
((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
......@@ -515,53 +612,148 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operator 1 "relop"
[(match_operand:CC 2 "register_operand" "%r")
(and:SI (neg:SI
(match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "odd_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
(ior:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
; /* The conditions match. */
else
{
/* Make the condition pairs line up by rotating the compare word. */
int cv1 = condition_value (operands[1]);
int cv2 = condition_value (operands[3]);
operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
gen_rtx (CONST_INT, VOIDmode,
(cv2 - cv1) & 0x1f));
}")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (neg:SI
(match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "even_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
(and:CCEVEN (not:CC (match_dup 2))
(match_dup 4)))
(set (match_dup 0)
(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1])
== reverse_condition (GET_CODE (operands[3])))
;
else
{
/* Make the condition pairs line up by rotating the compare word. */
int cv1 = condition_value (operands[1]);
int cv2 = condition_value (operands[3]);
operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
gen_rtx (CONST_INT, VOIDmode,
((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
}")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operator 1 "even_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "relop"
[(match_operand:CC 4 "register_operand" "r")
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == GET_CODE (operands[3])
|| GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
[(set (match_dup 5)
(and:CC (match_dup 4)
(and:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
"operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
/* Reverse the condition by complimenting the compare word. */
if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "odd_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == GET_CODE (operands[3])"
[(set (match_dup 5)
(ior:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operator 1 "odd_relop"
[(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "even_relop"
[(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
[(set (match_dup 5)
(and:CCEVEN (not:CC (match_dup 2))
(match_dup 4)))
(set (match_dup 0)
(match_op_dup 3 [(match_dup 5) (const_int 0)]))]
"operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
;; Logical operations on compare words.
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(and:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
(match_operand:CC 2 "register_operand" "r")))]
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
(match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"and.c %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(and:CC (match_operand:CC 1 "register_operand" "%r")
(match_operand:CC 2 "register_operand" "r")))]
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
(match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"and %0,%1,%2")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(ior:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
(match_operand:CC 2 "register_operand" "r")))]
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
(match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"or.c %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(ior:CC (match_operand:CC 1 "register_operand" "%r")
(match_operand:CC 2 "register_operand" "r")))]
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
(match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"or %0,%1,%2")
......@@ -573,95 +765,104 @@
"rot %0,%1,%2"
[(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))]
""
"rot %0,%1,%2"
[(set_attr "type" "bit")])
;; rotate/and[.c] and rotate/ior[.c]
(define_split
[(set (match_operand:CC 0 "register_operand" "=r")
(ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_operand:CC 4 "register_operand" "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(ior:CC (match_dup 4) (match_dup 3)))]
(ior:CCEVEN (match_dup 4) (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(ior:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_scratch:CC 4 "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
(define_split
[(set (match_operand:CC 0 "register_operand" "=r")
(ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_operand:CC 4 "register_operand" "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(ior:CC (not:CC (match_dup 4)) (match_dup 3)))]
(ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_scratch:CC 4 "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
(define_split
[(set (match_operand:CC 0 "register_operand" "=r")
(and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_operand:CC 4 "register_operand" "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(and:CC (match_dup 4) (match_dup 3)))]
(and:CCEVEN (match_dup 4) (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_scratch:CC 4 "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
(define_split
[(set (match_operand:CC 0 "register_operand" "=r")
(and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_operand:CC 4 "register_operand" "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(and:CC (not:CC (match_dup 4)) (match_dup 3)))]
(and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:CC 0 "register_operand" "=r")
(and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
[(set (match_operand:CCEVEN 0 "register_operand" "=r")
(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
(match_operand:CC 3 "register_operand" "r")))
(clobber (match_scratch:CC 4 "=r"))]
(match_operand 3 "partial_ccmode_register_operand" "r")))
(clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
;; Recognize bcnd instructions for integer values. This is distinguished
;; from a conditional branch instruction (below) with SImode instead of
......@@ -1006,14 +1207,18 @@
(define_expand "cmpsf"
[(set (match_dup 2)
(compare:CC (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" "")))]
(match_operand:SF 1 "register_operand" "")))
(use (reg:SI 65))
(clobber (reg:SI 64))]
""
"operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);")
(define_expand "cmpdf"
[(set (match_dup 2)
(compare:CC (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" "")))]
(match_operand:DF 1 "general_operand" "")))
(use (reg:SI 65))
(clobber (reg:SI 64))]
""
"
{
......@@ -1179,6 +1384,44 @@
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 1 "even_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)]))]
""
"ext %0,%2,1<%C1>"
[(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operator:SI 1 "odd_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)])))]
""
"ext %0,%2,1<%!%C1>"
[(set_attr "type" "bit")])
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 1 "odd_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)]))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
""
[(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))
(set (match_dup 0) (not:SI (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 1 "odd_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)]))
(clobber (match_scratch:SI 3 "=r"))]
""
"#")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI
(match_operator:SI 1 "relop"
[(match_operand:CC 2 "register_operand" "r")
......@@ -1186,6 +1429,51 @@
""
"extu %0,%2,1<%C1>"
[(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI
(match_operator:SI 1 "even_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)])))]
""
"extu %0,%2,1<%C1>"
[(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI
(not:SI (match_operator:SI 1 "odd_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)]))))]
""
"extu %0,%2,1<%!%C1>"
[(set_attr "type" "bit")])
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operator:SI 1 "odd_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
""
[(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2)
(const_int 0)]))))
(set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))]
"")
(define_insn
""
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operator:SI 1 "odd_relop"
[(match_operand:CCEVEN 2 "register_operand" "r")
(const_int 0)])))
(clobber (match_scratch:SI 3 "=r"))]
""
"#")
;; Conditional branch insns. The compare insns set a register
;; rather than cc0 and record that register for use here. See above
......@@ -1360,8 +1648,38 @@
}"
[(set_attr "type" "branch")])
;;
;; Here branch prediction is sacrificed. To get it back, you need
;; - CCODD (CC mode where the ODD bits are valid)
;; - several define_split that can apply De Morgan's Law.
;; - transformations between CCEVEN and CCODD modes.
;;
(define_insn ""
[(set (pc) (if_then_else
(match_operator 0 "even_relop"
[(match_operand:CCEVEN 1 "register_operand" "r")
(const_int 0)])
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb%L2%. %C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc) (if_then_else
(match_operator 0 "odd_relop"
[(match_operand:CCEVEN 1 "register_operand" "r")
(const_int 0)])
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb%L3%. %!%C0,%1,%P2%P3"
[(set_attr "type" "branch")])
;; Branch conditional on scc values. These arise from manipulations on
;; compare words above.
;; Are these really used ?
(define_insn ""
[(set (pc)
......@@ -1379,6 +1697,32 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (match_operator 0 "even_relop"
[(match_operand:CCEVEN 1 "register_operand" "r")
(const_int 0)])
(const_int 0))
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb%L2 %C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(ne (match_operator 0 "odd_relop"
[(match_operand:CCEVEN 1 "register_operand" "r")
(const_int 0)])
(const_int 0))
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb%L3 %!%C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(eq (match_operator 0 "relop"
[(match_operand:CC 1 "register_operand" "r")
(const_int 0)])
......@@ -1388,6 +1732,32 @@
""
"bb%L3 %C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(eq (match_operator 0 "even_relop"
[(match_operand:CCEVEN 1 "register_operand" "r")
(const_int 0)])
(const_int 0))
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb%L3 %C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(eq (match_operator 0 "odd_relop"
[(match_operand:CCEVEN 1 "register_operand" "r")
(const_int 0)])
(const_int 0))
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
"bb%L2 %!%C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn "locate1"
[(set (match_operand:SI 0 "register_operand" "=r")
......
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