From Jie Zhang <jie.zhang@analog.com>:

	* config/bfin/predicates.md (p_register_operand): New
	predicate.
	(dp_register_operand): New predicate.
	* config/bfin/bfin-protos.h (WA_05000074): Define.
	(ENABLE_WA_05000074): Define.
	* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
	all cpus.
	(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
	* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
	(define_attr addrtype): Allow load/store register to be
	P register.
	(define_attr storereg): New.
	(define_cpu_unit anomaly_05000074): New.
	(define_insn_reservation dsp32shiftimm): New.
	(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
	(define_insn_reservation loadp): Cannot use slot2.
	(define_insn_reservation loadsp): Cannot use slot2.
	(define_insn_reservation storep): Cannot use slot2. Does not
	apply when working around 05000074.
	(define_insn_reservation storep_anomaly_05000074): New.
	(define_insn_reservation storei): Does not apply when working
	around 05000074.
	(define_insn_reservation storei_anomaly_05000074): New.
	(define_attr length): Add dsp32shiftimm case.
	(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
	ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
	movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
	ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
	Set type as dsp32shiftimm for dsp32shiftimm alternatives.

From-SVN: r151490

gcc/ChangeLog

@@ -41,6 +41,37 @@
 	* doc/invoke.texi (Blackfin Options): Document that -mcpu now accepts
 	bf542m, bf544m, bf547m, bf548m, and bf549m.
 
+	From Jie Zhang <jie.zhang@analog.com>:
+	* config/bfin/predicates.md (p_register_operand): New
+	predicate.
+	(dp_register_operand): New predicate.
+	* config/bfin/bfin-protos.h (WA_05000074): Define.
+	(ENABLE_WA_05000074): Define.
+	* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
+	all cpus.
+	(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
+	* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
+	(define_attr addrtype): Allow load/store register to be
+	P register.
+	(define_attr storereg): New.
+	(define_cpu_unit anomaly_05000074): New.
+	(define_insn_reservation dsp32shiftimm): New.
+	(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
+	(define_insn_reservation loadp): Cannot use slot2.
+	(define_insn_reservation loadsp): Cannot use slot2.
+	(define_insn_reservation storep): Cannot use slot2. Does not
+	apply when working around 05000074.
+	(define_insn_reservation storep_anomaly_05000074): New.
+	(define_insn_reservation storei): Does not apply when working
+	around 05000074.
+	(define_insn_reservation storei_anomaly_05000074): New.
+	(define_attr length): Add dsp32shiftimm case.
+	(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
+	ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
+	movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
+	ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
+	Set type as dsp32shiftimm for dsp32shiftimm alternatives.
+
 2009-09-07  Martin Jambor  <mjambor@suse.cz>
 
 	PR middle-end/41282

gcc/config/bfin/bfin-protos.h

@@ -59,6 +59,10 @@
 #define ENABLE_WA_LOAD_LCREGS \
   (bfin_workarounds & WA_LOAD_LCREGS)
 
+#define WA_05000074 0x00000100
+#define ENABLE_WA_05000074 \
+  (bfin_workarounds & WA_05000074)
+
 #define Mmode enum machine_mode
 
 extern rtx function_arg (CUMULATIVE_ARGS *, Mmode, tree, int);

gcc/config/bfin/predicates.md

@@ -88,6 +88,14 @@
   (and (match_code "reg")
        (match_test "D_REGNO_P (REGNO (op))")))
 
+(define_predicate "p_register_operand"
+  (and (match_code "reg")
+       (match_test "P_REGNO_P (REGNO (op))")))
+
+(define_predicate "dp_register_operand"
+  (and (match_code "reg")
+       (match_test "D_REGNO_P (REGNO (op)) || P_REGNO_P (REGNO (op))")))
+
 ;; Return nonzero if OP is a LC register.
 (define_predicate "lc_register_operand"
   (and (match_code "reg")