fold-vec-abs-int.c: Remove scan-assembler stanzas.

[testsuite]

2018-01-26  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-abs-int.c: Remove scan-assembler stanzas.
	* gcc.target/powerpc/fold-vec-abs-int-fwrap.c: Same.
	* gcc.target/powerpc/fold-vec-abs-int.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.c: Remove scan-assembler stanzas.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c: Same.
	* gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-short.c: Add xxspltib to valid instruction list.
	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Same.

From-SVN: r257097

gcc/testsuite/ChangeLog

 2018-01-26  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
+	* gcc.target/powerpc/fold-vec-abs-int.c: Remove scan-assembler stanzas.
+	* gcc.target/powerpc/fold-vec-abs-int-fwrap.c: Same.
+	* gcc.target/powerpc/fold-vec-abs-int.p7.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int.p8.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int.p9.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong.c: Remove scan-assembler
+	stanzas.
+	* gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c: Same.
+	* gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New.
+	* gcc.target/powerpc/fold-vec-abs-short.c: Add xxspltib to valid
+	instruction list.
+	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Same.
+
+2018-01-26  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
 	* gcc.target/powerpc/fold-vec-cmp-int.c: Delete.
 	* gcc.target/powerpc/fold-vec-cmp-int.h: New.
 	* gcc.target/powerpc/fold-vec-cmp-int.p7.c: New.

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c

@@ -13,6 +13,4 @@ test1 (vector signed int x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-int-fwrapv.p*.c tests.  */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c

+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power7 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c

+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power8 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c

+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power9 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c

@@ -13,6 +13,4 @@ test1 (vector signed int x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+/* scan-assembler entries moved to fold-vec-abs-int.p*.c files. */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c

+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power7 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c

+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power8 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c

+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power9 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c

@@ -13,6 +13,5 @@ test3 (vector signed long long x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c.  */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c

+
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c

+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c

@@ -13,6 +13,4 @@ test3 (vector signed long long x)
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c . */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c

+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c

+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */