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Commit b1875f52 by H.J. Lu Committed by H.J. Lu
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config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 

2006-10-22  H.J. Lu  <hongjiu.lu@intel.com>

	* config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
	(x86_64-*-*): Likewise.

	* config/i386/i386.c (pta_flags): Add PTA_SSSE3.
	(override_options): Check SSSE3.
	(ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
	IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
	IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
	IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
	IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
	IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
	IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
	IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
	IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
	IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
	IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
	IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
	IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
	IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
	IX86_BUILTIN_PABSD128.
	(bdesc_2arg): Add SSSE3.
	(bdesc_1arg): Likewise.
	(ix86_init_mmx_sse_builtins): Support SSSE3.
	(ix86_expand_builtin): Likewise.
	* config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.

	* config/i386/i386.md (UNSPEC_PSHUFB): New.
	(UNSPEC_PSIGN): Likewise.
	(UNSPEC_PALIGNR): Likewise.
	Include mmx.md before sse.md.

	* config/i386/i386.opt: Add -mssse3.

	* config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
	(ssse3_phaddwv4hi3): Likewise.
	(ssse3_phadddv4si3): Likewise.
	(ssse3_phadddv2si3): Likewise.
	(ssse3_phaddswv8hi3): Likewise.
	(ssse3_phaddswv4hi3): Likewise.
	(ssse3_phsubwv8hi3): Likewise.
	(ssse3_phsubwv4hi3): Likewise.
	(ssse3_phsubdv4si3): Likewise.
	(ssse3_phsubdv2si3): Likewise.
	(ssse3_phsubswv8hi3): Likewise.
	(ssse3_phsubswv4hi3): Likewise.
	(ssse3_pmaddubswv8hi3): Likewise.
	(ssse3_pmaddubswv4hi3): Likewise.
	(ssse3_pmulhrswv8hi3): Likewise.
	(ssse3_pmulhrswv4hi3): Likewise.
	(ssse3_pshufbv16qi3): Likewise.
	(ssse3_pshufbv8qi3): Likewise.
	(ssse3_psign<mode>3): Likewise.
	(ssse3_psign<mode>3): Likewise.
	(ssse3_palignrti): Likewise.
	(ssse3_palignrdi): Likewise.
	(abs<mode>2): Likewise.
	(abs<mode>2): Likewise.

	* config/i386/tmmintrin.h: New file.

	* doc/extend.texi: Document SSSE3 built-in functions.

	* doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.

From-SVN: r117958
parent 6e4be1fa
Showing with 135 additions and 7 deletions
gcc/ChangeLog
2006-10-22 H.J. Lu <hongjiu.lu@intel.com>
* config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
(x86_64-*-*): Likewise.
* config/i386/i386.c (pta_flags): Add PTA_SSSE3.
(override_options): Check SSSE3.
(ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
IX86_BUILTIN_PABSD128.
(bdesc_2arg): Add SSSE3.
(bdesc_1arg): Likewise.
(ix86_init_mmx_sse_builtins): Support SSSE3.
(ix86_expand_builtin): Likewise.
* config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
* config/i386/i386.md (UNSPEC_PSHUFB): New.
(UNSPEC_PSIGN): Likewise.
(UNSPEC_PALIGNR): Likewise.
Include mmx.md before sse.md.
* config/i386/i386.opt: Add -mssse3.
* config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
(ssse3_phaddwv4hi3): Likewise.
(ssse3_phadddv4si3): Likewise.
(ssse3_phadddv2si3): Likewise.
(ssse3_phaddswv8hi3): Likewise.
(ssse3_phaddswv4hi3): Likewise.
(ssse3_phsubwv8hi3): Likewise.
(ssse3_phsubwv4hi3): Likewise.
(ssse3_phsubdv4si3): Likewise.
(ssse3_phsubdv2si3): Likewise.
(ssse3_phsubswv8hi3): Likewise.
(ssse3_phsubswv4hi3): Likewise.
(ssse3_pmaddubswv8hi3): Likewise.
(ssse3_pmaddubswv4hi3): Likewise.
(ssse3_pmulhrswv8hi3): Likewise.
(ssse3_pmulhrswv4hi3): Likewise.
(ssse3_pshufbv16qi3): Likewise.
(ssse3_pshufbv8qi3): Likewise.
(ssse3_psign<mode>3): Likewise.
(ssse3_psign<mode>3): Likewise.
(ssse3_palignrti): Likewise.
(ssse3_palignrdi): Likewise.
(abs<mode>2): Likewise.
(abs<mode>2): Likewise.
* config/i386/tmmintrin.h: New file.
* doc/extend.texi: Document SSSE3 built-in functions.
* doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
2006-10-22 Ira Rosen <irar@il.ibm.com>
* tree-vect-transform.c (vectorizable_load): Use the type of the
......
gcc/config.gcc
......@@ -268,11 +268,13 @@ xscale-*-*)
;;
i[34567]86-*-*)
cpu_type=i386
extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h pmmintrin.h"
extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
pmmintrin.h tmmintrin.h"
;;
x86_64-*-*)
cpu_type=i386
extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h pmmintrin.h"
extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
pmmintrin.h tmmintrin.h"
need_64bit_hwint=yes
;;
ia64-*-*)
......
gcc/config/i386/i386.h
......@@ -409,6 +409,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
builtin_define ("__SSE2__"); \
if (TARGET_SSE3) \
builtin_define ("__SSE3__"); \
if (TARGET_SSSE3) \
builtin_define ("__SSSE3__"); \
if (TARGET_SSE_MATH && TARGET_SSE) \
builtin_define ("__SSE_MATH__"); \
if (TARGET_SSE_MATH && TARGET_SSE2) \
......
gcc/config/i386/i386.md
......@@ -148,6 +148,11 @@
(UNSPEC_SP_TEST 101)
(UNSPEC_SP_TLS_SET 102)
(UNSPEC_SP_TLS_TEST 103)
; SSSE3
(UNSPEC_PSHUFB 120)
(UNSPEC_PSIGN 121)
(UNSPEC_PALIGNR 122)
])
(define_constants
......@@ -20954,6 +20959,6 @@
}
[(set_attr "type" "multi")])
(include "sse.md")
(include "mmx.md")
(include "sse.md")
(include "sync.md")
gcc/config/i386/i386.opt
......@@ -197,6 +197,10 @@ msse3
Target Report Mask(SSE3)
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
mssse3
Target Report Mask(SSSE3)
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
msseregparm
Target RejectNegative Mask(SSEREGPARM)
Use SSE register passing conventions for SF and DF mode
......
gcc/doc/extend.texi
......@@ -7169,6 +7169,52 @@ The following built-in functions are available when @option{-msse3} is used.
Generates the @code{movddup} machine instruction as a load from memory.
@end table
The following built-in functions are available when @option{-mssse3} is used.
All of them generate the machine instruction that is part of the name
with MMX registers.
@smallexample
v2si __builtin_ia32_phaddd (v2si, v2si)
v4hi __builtin_ia32_phaddw (v4hi, v4hi)
v4hi __builtin_ia32_phaddsw (v4hi, v4hi)
v2si __builtin_ia32_phsubd (v2si, v2si)
v4hi __builtin_ia32_phsubw (v4hi, v4hi)
v4hi __builtin_ia32_phsubsw (v4hi, v4hi)
v8qi __builtin_ia32_pmaddubsw (v8qi, v8qi)
v4hi __builtin_ia32_pmulhrsw (v4hi, v4hi)
v8qi __builtin_ia32_pshufb (v8qi, v8qi)
v8qi __builtin_ia32_psignb (v8qi, v8qi)
v2si __builtin_ia32_psignd (v2si, v2si)
v4hi __builtin_ia32_psignw (v4hi, v4hi)
long long __builtin_ia32_palignr (long long, long long, int)
v8qi __builtin_ia32_pabsb (v8qi)
v2si __builtin_ia32_pabsd (v2si)
v4hi __builtin_ia32_pabsw (v4hi)
@end smallexample
The following built-in functions are available when @option{-mssse3} is used.
All of them generate the machine instruction that is part of the name
with SSE registers.
@smallexample
v4si __builtin_ia32_phaddd128 (v4si, v4si)
v8hi __builtin_ia32_phaddw128 (v8hi, v8hi)
v8hi __builtin_ia32_phaddsw128 (v8hi, v8hi)
v4si __builtin_ia32_phsubd128 (v4si, v4si)
v8hi __builtin_ia32_phsubw128 (v8hi, v8hi)
v8hi __builtin_ia32_phsubsw128 (v8hi, v8hi)
v16qi __builtin_ia32_pmaddubsw128 (v16qi, v16qi)
v8hi __builtin_ia32_pmulhrsw128 (v8hi, v8hi)
v16qi __builtin_ia32_pshufb128 (v16qi, v16qi)
v16qi __builtin_ia32_psignb128 (v16qi, v16qi)
v4si __builtin_ia32_psignd128 (v4si, v4si)
v8hi __builtin_ia32_psignw128 (v8hi, v8hi)
v2di __builtin_ia32_palignr (v2di, v2di, int)
v16qi __builtin_ia32_pabsb128 (v16qi)
v4si __builtin_ia32_pabsd128 (v4si)
v8hi __builtin_ia32_pabsw128 (v8hi)
@end smallexample
The following built-in functions are available when @option{-m3dnow} is used.
All of them generate the machine instruction that is part of the name.
......
gcc/doc/invoke.texi
......@@ -533,7 +533,7 @@ Objective-C and Objective-C++ Dialects}.
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
-mmmx -msse -msse2 -msse3 -m3dnow @gol
-mmmx -msse -msse2 -msse3 -mssse3 -m3dnow @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -msseregparm @gol
......@@ -9568,6 +9568,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@itemx -mno-sse2
@item -msse3
@itemx -mno-sse3
@item -mssse3
@itemx -mno-ssse3
@item -m3dnow
@itemx -mno-3dnow
@opindex mmmx
......@@ -9577,9 +9579,10 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
SSE, SSE2 or 3DNow! extended instruction sets. These extensions are
also available as built-in functions: see @ref{X86 Built-in Functions},
for details of the functions enabled and disabled by these switches.
SSE, SSE2, SSE3, SSSE3 or 3DNow! extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
disabled by these switches.
To have SSE/SSE2 instructions generated automatically from floating-point
code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
......
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