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lvzhengyang
riscv-gcc-1
Commits
b0193a92
Commit
b0193a92
authored
Nov 12, 1992
by
Michael Meissner
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Split mov{df,sf}_internal into 2 insns, one for soft float, one for hard.
From-SVN: r2748
parent
e1f998ad
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6 deletions
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-6
gcc/config/mips/mips.md
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gcc/config/mips/mips.md
View file @
b0193a92
...
@@ -2013,19 +2013,34 @@ move\\t%0,%z4\\n\\
...
@@ -2013,19 +2013,34 @@ move\\t%0,%z4\\n\\
}
}
}")
}")
(define_insn "movsf_internal"
(define_insn "movsf_internal
1
"
[
(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,
*f,*
d,
*d,*
d,
*d,*
R,
*
m")
[
(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,
*f,*
d,
*d,*
d,
*d,*
R,
*
m")
(match_operand:SF 1 "general_operand" "f,G,R,Em,fG,fG,
*d,*
f,
*G*
d,
*R,*
E
*m,*
d,
*
d"))]
(match_operand:SF 1 "general_operand" "f,G,R,Em,fG,fG,
*d,*
f,
*G*
d,
*R,*
E
*m,*
d,
*
d"))]
"register_operand (operands
[
0
]
, SFmode)
"TARGET_HARD_FLOAT
&& (register_operand (operands
[
0
]
, SFmode)
|| register_operand (operands
[
1
]
, SFmode)
|| register_operand (operands
[
1
]
, SFmode)
|| (GET_CODE (operands
[
1
]
) == CONST_INT && INTVAL (operands
[
1
]
) == 0)
|| (GET_CODE (operands
[
1
]
) == CONST_INT && INTVAL (operands
[
1
]
) == 0)
|| operands
[
1
]
== CONST0_RTX (SFmode
)"
|| operands
[
1
]
== CONST0_RTX (SFmode)
)"
"
*
return mips_move_1word (operands, insn, FALSE);"
"
*
return mips_move_1word (operands, insn, FALSE);"
[
(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
[
(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SF")
(set_attr "mode" "SF")
(set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
(set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
(define_insn "movsf_internal2"
[
(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
(match_operand:SF 1 "general_operand" " Gd,R,Em,d,d"))]
"TARGET_SOFT_FLOAT
&& (register_operand (operands
[
0
]
, SFmode)
|| register_operand (operands
[
1
]
, SFmode)
|| (GET_CODE (operands
[
1
]
) == CONST_INT && INTVAL (operands
[
1
]
) == 0)
|| operands
[
1
]
== CONST0_RTX (SFmode))"
"
*
return mips_move_1word (operands, insn, FALSE);"
[
(set_attr "type" "move,load,load,store,store")
(set_attr "mode" "SF")
(set_attr "length" "1,1,2,1,2")])
;; 64-bit floating point moves
;; 64-bit floating point moves
(define_expand "movdf"
(define_expand "movdf"
...
@@ -2046,18 +2061,32 @@ move\\t%0,%z4\\n\\
...
@@ -2046,18 +2061,32 @@ move\\t%0,%z4\\n\\
}
}
}")
}")
(define_insn "movdf_internal"
(define_insn "movdf_internal
1
"
[
(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,
*f,*
d,
*d,*
d,
*d,*
R,
*
o")
[
(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,
*f,*
d,
*d,*
d,
*d,*
R,
*
o")
(match_operand:DF 1 "general_operand" "f,R,o,fG,fG,E,
*d,*
f,
*d*
G,
*R,*
o
*E,*
d,
*
d"))]
(match_operand:DF 1 "general_operand" "f,R,o,fG,fG,E,
*d,*
f,
*d*
G,
*R,*
o
*E,*
d,
*
d"))]
"register_operand (operands
[
0
]
, DFmode)
"TARGET_HARD_FLOAT
&& (register_operand (operands
[
0
]
, DFmode)
|| register_operand (operands
[
1
]
, DFmode)
|| register_operand (operands
[
1
]
, DFmode)
|| (GET_CODE (operands
[
1
]
) == CONST_INT && INTVAL (operands
[
1
]
) == 0)
|| (GET_CODE (operands
[
1
]
) == CONST_INT && INTVAL (operands
[
1
]
) == 0)
|| operands
[
1
]
== CONST0_RTX (DFmode
)"
|| operands
[
1
]
== CONST0_RTX (DFmode)
)"
"
*
return mips_move_2words (operands, insn); "
"
*
return mips_move_2words (operands, insn); "
[
(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
[
(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "DF")
(set_attr "mode" "DF")
(set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
(set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
(define_insn "movdf_internal2"
[
(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,o")
(match_operand:DF 1 "general_operand" "dG,R,oE,d,d"))]
"TARGET_SOFT_FLOAT
&& (register_operand (operands
[
0
]
, DFmode)
|| register_operand (operands
[
1
]
, DFmode)
|| (GET_CODE (operands
[
1
]
) == CONST_INT && INTVAL (operands
[
1
]
) == 0)
|| operands
[
1
]
== CONST0_RTX (DFmode))"
"
*
return mips_move_2words (operands, insn); "
[
(set_attr "type" "move,load,load,store,store")
(set_attr "mode" "DF")
(set_attr "length" "2,2,4,2,4")])
(define_split
(define_split
[
(set (match_operand:DF 0 "register_operand" "")
[
(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))]
(match_operand:DF 1 "register_operand" ""))]
...
...
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