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riscv-gcc-1
Commit af952763 by Oleg Endo
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longlong.h (umul_ppmm): Remove SHMEDIA checks. 

include/
	* longlong.h (umul_ppmm): Remove SHMEDIA checks.
	(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.

gcc/
	* common/config/sh/sh-common.c (sh_option_optimization_table): Remove
	remaining SH5 related settings.
	* config/sh/sh-protos.h (shmedia_cleanup_truncate,
	shmedia_prepare_call_address): Delete.
	* config/sh/sh.c (sh_print_operand, output_stack_adjust,
	DWARF_CIE_DATA_ALIGNMENT, LOCAL_ALIGNMENT): Update comments.
	* config/sh/sh.h (SUBTARGET_ASM_RELAX_SPEC,
	UNSUPPORTED_SH2A): Remove m5 checks.
	(sh_divide_strategy_e): Remove SH5 division strategies.
	(TARGET_PTRMEMFUNC_VBIT_LOCATION): Remove and use default.
	* config/sh/sh.md (divsf3): Reinstate define_expand pattern.

From-SVN: r235632
parent 1ab06af6
Showing with 38 additions and 61 deletions
gcc/ChangeLog
2016-04-29 Oleg Endo <olegendo@gcc.gnu.org>
* common/config/sh/sh-common.c (sh_option_optimization_table): Remove
remaining SH5 related settings.
* config/sh/sh-protos.h (shmedia_cleanup_truncate,
shmedia_prepare_call_address): Delete.
* config/sh/sh.c (sh_print_operand, output_stack_adjust,
DWARF_CIE_DATA_ALIGNMENT, LOCAL_ALIGNMENT): Update comments.
* config/sh/sh.h (SUBTARGET_ASM_RELAX_SPEC,
UNSUPPORTED_SH2A): Remove m5 checks.
(sh_divide_strategy_e): Remove SH5 division strategies.
(TARGET_PTRMEMFUNC_VBIT_LOCATION): Remove and use default.
* config/sh/sh.md (divsf3): Reinstate define_expand pattern.
2016-04-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/s390.c (s390_rtx_costs): Update documentation.
......
gcc/common/config/sh/sh-common.c
......@@ -31,15 +31,8 @@ along with GCC; see the file COPYING3. If not see
static const struct default_options sh_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_mdiv_, "inv:minlat", 1 },
{ OPT_LEVELS_SIZE, OPT_mdiv_, SH_DIV_STR_FOR_SIZE, 1 },
{ OPT_LEVELS_0_ONLY, OPT_mdiv_, "", 1 },
/* We can't meaningfully test TARGET_SHMEDIA here, because -m
options haven't been parsed yet, hence we'd read only the
default. sh_target_reg_class will return NO_REGS if this is
not SHMEDIA, so it's OK to always set
flag_branch_target_load_optimize. */
{ OPT_LEVELS_2_PLUS, OPT_fbranch_target_load_optimize, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
......
gcc/config/sh/sh-protos.h
......@@ -392,11 +392,8 @@ extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
signed int, machine_mode);
extern rtx sh_dwarf_register_span (rtx);
extern int shmedia_cleanup_truncate (rtx);
extern bool sh_contains_memref_p (rtx);
extern bool sh_loads_bankedreg_p (rtx);
extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
extern int sh2a_get_function_vector_number (rtx);
extern bool sh2a_is_function_vector_call (rtx);
extern void sh_fix_range (const char *);
......
gcc/config/sh/sh.c
......@@ -1177,9 +1177,6 @@ sh_print_operand (FILE *stream, rtx x, int code)
output_addr_const (stream, x);
break;
/* N.B.: %R / %S / %T adjust memory addresses by four.
For SHMEDIA, that means they can be used to access the first and
second 32 bit part of a 64 bit (or larger) value that
might be held in floating point registers or memory.
While they can be used to access 64 bit parts of a larger value
held in general purpose registers, that won't work with memory -
neither for fp registers, since the frxx names are used. */
......@@ -6748,14 +6745,11 @@ output_stack_adjust (int size, rtx reg, int epilogue_p,
rtx adj_reg, tmp_reg, mem;
/* If we reached here, the most likely case is the (sibcall)
epilogue for non SHmedia. Put a special push/pop sequence
for such case as the last resort. This looks lengthy but
would not be problem because it seems to be very
rare. */
epilogue. Put a special push/pop sequence for such case as
the last resort. This looks lengthy but would not be problem
because it seems to be very rare. */
gcc_assert (epilogue_p);
/* ??? There is still the slight possibility that r4 or
r5 have been reserved as fixed registers or assigned
as global registers, and they change during an
......
gcc/config/sh/sh.h
......@@ -206,7 +206,7 @@ extern int code_for_indirect_jump_scratch;
SUBTARGET_EXTRA_SPECS
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*::-isa=sh4-up}}}"
#else
#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
#endif
......@@ -250,7 +250,7 @@ extern int code_for_indirect_jump_scratch;
/* Strict nofpu means that the compiler should tell the assembler
to reject FPU instructions. E.g. from ASM inserts. */
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*::-isa=sh4-nofpu}}}}"
#else
#define SUBTARGET_ASM_ISA_SPEC \
......@@ -299,7 +299,7 @@ extern int code_for_indirect_jump_scratch;
#if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
#define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
"%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
"%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}"
#else
#define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
"%{m2a*:%eSH2a does not support little-endian}}"
......@@ -323,17 +323,6 @@ extern int code_for_indirect_jump_scratch;
extern int assembler_dialect;
enum sh_divide_strategy_e {
/* SH5 strategies. */
SH_DIV_CALL,
SH_DIV_CALL2,
SH_DIV_FP, /* We could do this also for SH4. */
SH_DIV_INV,
SH_DIV_INV_MINLAT,
SH_DIV_INV20U,
SH_DIV_INV20L,
SH_DIV_INV_CALL,
SH_DIV_INV_CALL2,
SH_DIV_INV_FP,
/* SH1 .. SH4 strategies. Because of the small number of registers
available, the compiler uses knowledge of the actual set of registers
being clobbered by the different functions called. */
......@@ -390,10 +379,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
#define MIN_UNITS_PER_WORD 4
/* Scaling factor for Dwarf data offsets for CFI information.
The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
SHmedia; however, since we do partial register saves for the registers
visible to SHcompact, and for target registers for SHMEDIA32, we have
to allow saves that are only 4-byte aligned. */
The dwarf2out.c default would use -UNITS_PER_WORD. */
#define DWARF_CIE_DATA_ALIGNMENT -4
/* Width in bits of a pointer.
......@@ -415,11 +401,6 @@ extern enum sh_divide_strategy_e sh_div_strategy;
code of a function. */
#define FUNCTION_BOUNDARY (16)
/* On SH5, the lowest bit is used to indicate SHmedia functions, so
the vbit must go into the delta field of
pointers-to-member-functions. */
#define TARGET_PTRMEMFUNC_VBIT_LOCATION (ptrmemfunc_vbit_in_pfn)
/* Alignment of field after `int : 0' in a structure. */
#define EMPTY_FIELD_BOUNDARY 32
......@@ -437,9 +418,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
/* get_mode_alignment assumes complex values are always held in multiple
registers, but that is not the case on the SH; CQImode and CHImode are
held in a single integer register. SH5 also holds CSImode and SCmode
values in integer registers. This is relevant for argument passing on
SHcompact as we use a stack temp in order to pass CSImode by reference. */
held in a single integer register. */
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
|| GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
......
gcc/config/sh/sh.md
......@@ -9300,6 +9300,16 @@
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(define_expand "divsf3"
[(set (match_operand:SF 0 "fp_arith_reg_operand")
(div:SF (match_operand:SF 1 "fp_arith_reg_operand")
(match_operand:SF 2 "fp_arith_reg_operand")))]
"TARGET_SH2E"
{
emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
DONE;
})
(define_insn "divsf3_i"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
......
include/ChangeLog
2016-04-29 Oleg Endo <olegendo@gcc.gnu.org>
* longlong.h (umul_ppmm): Remove SHMEDIA checks.
(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.
2016-04-29 Claudiu Zissulescu <claziss@synopsys.com>
* longlong.h (add_ssaaaa): Replace obsolete 'J' constraint with
......
include/longlong.h
......@@ -1086,7 +1086,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
} while (0)
#endif
#if defined(__sh__) && (!defined (__SHMEDIA__) || !__SHMEDIA__) && W_TYPE_SIZE == 32
#if defined(__sh__) && W_TYPE_SIZE == 32
#ifndef __sh1__
#define umul_ppmm(w1, w0, u, v) \
__asm__ ( \
......@@ -1159,21 +1159,6 @@ extern UDItype __umulsidi3 (USItype, USItype);
#endif /* __sh__ */
#if defined (__SH5__) && defined (__SHMEDIA__) && __SHMEDIA__ && W_TYPE_SIZE == 32
#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
#define count_leading_zeros(count, x) \
do \
{ \
UDItype x_ = (USItype)(x); \
SItype c_; \
\
__asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
(count) = c_ - 31; \
} \
while (0)
#define COUNT_LEADING_ZEROS_0 32
#endif
#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
&& W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
......
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