ia64.h (enum fetchop_code): Remove.

        * config/ia64/ia64.h (enum fetchop_code): Remove.
        (enum ia64_builtins): Move ...
        * config/ia64/ia64.c (enum ia64_builtins): ... here.  Remove all
        members except BSP and FLUSHRS.
        (ia64_init_builtins): Remove __sync builtins.
        (ia64_expand_builtin): Likewise.
        (ia64_expand_fetch_and_op, ia64_expand_op_and_fetch): Remove.
        (ia64_expand_compare_and_swap, ia64_expand_lock_test_and_set): Remove.
        (ia64_expand_lock_release): Remove.
        * config/ia64/ia64.md (mf): Move to sync.md.
        (mf_internal, fetchadd_acq_si, fetchadd_acq_di, cmpxchg_acq_si,
        cmpxchg_acq_di, xchgsi, xchgdi): Likewise.
        * config/ia64/sync.md: New file.
        (memory_barrier): Rename from mf.
        (fetchadd_acq_<I48MODE>): Macroize from _si/_di patterns.
        (cmpxchg_acq_<I48MODE>): Likewise.
        (sync_lock_test_and_set<I48MODE>): Likewise.

        * config/ia64/ia64intrin.h: Define nothing for C; limit #defines
        to c++.  Remove __sync* declarations.  s/_si/_4/.  s/_di/_8/.

From-SVN: r98156

gcc/ChangeLog

 2004-04-14  Richard Henderson  <rth@redhat.com>
 
+	* config/ia64/ia64.h (enum fetchop_code): Remove.
+	(enum ia64_builtins): Move ...
+	* config/ia64/ia64.c (enum ia64_builtins): ... here.  Remove all
+	members except BSP and FLUSHRS.
+	(ia64_init_builtins): Remove __sync builtins.
+	(ia64_expand_builtin): Likewise.
+	(ia64_expand_fetch_and_op, ia64_expand_op_and_fetch): Remove.
+	(ia64_expand_compare_and_swap, ia64_expand_lock_test_and_set): Remove.
+	(ia64_expand_lock_release): Remove.
+	* config/ia64/ia64.md (mf): Move to sync.md.
+	(mf_internal, fetchadd_acq_si, fetchadd_acq_di, cmpxchg_acq_si,
+	cmpxchg_acq_di, xchgsi, xchgdi): Likewise.
+	* config/ia64/sync.md: New file.
+	(memory_barrier): Rename from mf.
+	(fetchadd_acq_<I48MODE>): Macroize from _si/_di patterns.
+	(cmpxchg_acq_<I48MODE>): Likewise.
+	(sync_lock_test_and_set<I48MODE>): Likewise.
+
+	* config/ia64/ia64intrin.h: Define nothing for C; limit #defines
+	to c++.  Remove __sync* declarations.  s/_si/_4/.  s/_di/_8/.
+
+2004-04-14  Richard Henderson  <rth@redhat.com>
+
 	* config/i386/i386.c (x86_cmpxchg, x86_xadd): New.
 	(ix86_compare_emitted): New.
 	(ix86_expand_compare): Use ix86_compare_emitted if set.

gcc/config/ia64/ia64.h

@@ -2034,66 +2034,6 @@ struct machine_function GTY(())
   int state_num;
 };
 
-
-enum ia64_builtins
-{
-  IA64_BUILTIN_SYNCHRONIZE,
-
-  IA64_BUILTIN_FETCH_AND_ADD_SI,
-  IA64_BUILTIN_FETCH_AND_SUB_SI,
-  IA64_BUILTIN_FETCH_AND_OR_SI,
-  IA64_BUILTIN_FETCH_AND_AND_SI,
-  IA64_BUILTIN_FETCH_AND_XOR_SI,
-  IA64_BUILTIN_FETCH_AND_NAND_SI,
-
-  IA64_BUILTIN_ADD_AND_FETCH_SI,
-  IA64_BUILTIN_SUB_AND_FETCH_SI,
-  IA64_BUILTIN_OR_AND_FETCH_SI,
-  IA64_BUILTIN_AND_AND_FETCH_SI,
-  IA64_BUILTIN_XOR_AND_FETCH_SI,
-  IA64_BUILTIN_NAND_AND_FETCH_SI,
-
-  IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
-  IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
-
-  IA64_BUILTIN_SYNCHRONIZE_SI,
-
-  IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
-
-  IA64_BUILTIN_LOCK_RELEASE_SI,
-
-  IA64_BUILTIN_FETCH_AND_ADD_DI,
-  IA64_BUILTIN_FETCH_AND_SUB_DI,
-  IA64_BUILTIN_FETCH_AND_OR_DI,
-  IA64_BUILTIN_FETCH_AND_AND_DI,
-  IA64_BUILTIN_FETCH_AND_XOR_DI,
-  IA64_BUILTIN_FETCH_AND_NAND_DI,
-
-  IA64_BUILTIN_ADD_AND_FETCH_DI,
-  IA64_BUILTIN_SUB_AND_FETCH_DI,
-  IA64_BUILTIN_OR_AND_FETCH_DI,
-  IA64_BUILTIN_AND_AND_FETCH_DI,
-  IA64_BUILTIN_XOR_AND_FETCH_DI,
-  IA64_BUILTIN_NAND_AND_FETCH_DI,
-
-  IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
-  IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
-
-  IA64_BUILTIN_SYNCHRONIZE_DI,
-
-  IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
-
-  IA64_BUILTIN_LOCK_RELEASE_DI,
-
-  IA64_BUILTIN_BSP,
-  IA64_BUILTIN_FLUSHRS
-};
-
-/* Codes for expand_compare_and_swap and expand_swap_and_compare.  */
-enum fetchop_code {
-  IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
-};
-
 #define DONT_USE_BUILTIN_SETJMP
 
 /* Output any profiling code before the prologue.  */
@@ -2106,7 +2046,6 @@ enum fetchop_code {
 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
 
 
-
 /* Switch on code for querying unit reservations.  */
 #define CPU_UNITS_QUERY 1
 

gcc/config/ia64/ia64.md

@@ -6048,88 +6048,6 @@
 })
 
 
-;;; Intrinsics support.
-
-(define_expand "mf"
-  [(set (mem:BLK (match_dup 0))
-	(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
-  ""
-{
-  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
-  MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*mf_internal"
-  [(set (match_operand:BLK 0 "" "")
-	(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
-  ""
-  "mf"
-  [(set_attr "itanium_class" "syst_m")])
-
-(define_insn "fetchadd_acq_si"
-  [(set (match_operand:SI 0 "gr_register_operand" "=r")
-	(match_operand:SI 1 "not_postinc_memory_operand" "+S"))
-   (set (match_dup 1)
-	(unspec:SI [(match_dup 1)
-		    (match_operand:SI 2 "fetchadd_operand" "n")]
-		   UNSPEC_FETCHADD_ACQ))]
-  ""
-  "fetchadd4.acq %0 = %1, %2"
-  [(set_attr "itanium_class" "sem")])
-
-(define_insn "fetchadd_acq_di"
-  [(set (match_operand:DI 0 "gr_register_operand" "=r")
-	(match_operand:DI 1 "not_postinc_memory_operand" "+S"))
-   (set (match_dup 1)
-	(unspec:DI [(match_dup 1)
-		    (match_operand:DI 2 "fetchadd_operand" "n")]
-		   UNSPEC_FETCHADD_ACQ))]
-  ""
-  "fetchadd8.acq %0 = %1, %2"
-  [(set_attr "itanium_class" "sem")])
-
-(define_insn "cmpxchg_acq_si"
-  [(set (match_operand:SI 0 "gr_register_operand" "=r")
-	(match_operand:SI 1 "not_postinc_memory_operand" "+S"))
-   (set (match_dup 1)
-        (unspec:SI [(match_dup 1)
-                    (match_operand:SI 2 "gr_register_operand" "r")
-		    (match_operand:DI 3 "ar_ccv_reg_operand" "")]
-		   UNSPEC_CMPXCHG_ACQ))]
-  ""
-  "cmpxchg4.acq %0 = %1, %2, %3"
-  [(set_attr "itanium_class" "sem")])
-
-(define_insn "cmpxchg_acq_di"
-  [(set (match_operand:DI 0 "gr_register_operand" "=r")
-	(match_operand:DI 1 "not_postinc_memory_operand" "+S"))
-   (set (match_dup 1)
-        (unspec:DI [(match_dup 1)
-                    (match_operand:DI 2 "gr_register_operand" "r")
-		    (match_operand:DI 3 "ar_ccv_reg_operand" "")]
-		   UNSPEC_CMPXCHG_ACQ))]
-  ""
-  "cmpxchg8.acq %0 = %1, %2, %3"
-  [(set_attr "itanium_class" "sem")])
-
-(define_insn "xchgsi"
-  [(set (match_operand:SI 0 "gr_register_operand" "=r")
-        (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
-   (set (match_dup 1)
-        (match_operand:SI 2 "gr_register_operand" "r"))]
-  ""
-  "xchg4 %0 = %1, %2"
-  [(set_attr "itanium_class" "sem")])
-
-(define_insn "xchgdi"
-  [(set (match_operand:DI 0 "gr_register_operand" "=r")
-        (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
-   (set (match_dup 1)
-        (match_operand:DI 2 "gr_register_operand" "r"))]
-  ""
-  "xchg8 %0 = %1, %2"
-  [(set_attr "itanium_class" "sem")])
-
 ;; Predication.
 
 (define_cond_exec
@@ -6200,3 +6118,5 @@
 
 ;; Vector operations
 (include "vect.md")
+;; Atomic operations
+(include "sync.md")

gcc/config/ia64/ia64intrin.h

 #ifndef _IA64INTRIN_H_INCLUDED
 #define _IA64INTRIN_H_INCLUDED
 
-/* Actually, everything is a compiler builtin, but just so
-   there's no confusion...  */
+/* ??? Overloaded builtins havn't been ported to C++ yet.  */
 #ifdef __cplusplus
-extern "C" {
-#endif
 
-extern void __sync_synchronize (void);
-
-extern int __sync_val_compare_and_swap_si (int *, int, int);
-extern long __sync_val_compare_and_swap_di (long *, long, long);
 #define __sync_val_compare_and_swap(PTR, OLD, NEW)			\
  ((sizeof (*(PTR)) == sizeof(int))					\
   ? (__typeof__(*(PTR)))						\
-    __sync_val_compare_and_swap_si((int *)(void *)(PTR),(int)(OLD),(int)(NEW))	\
+    __sync_val_compare_and_swap_4((int *)(void *)(PTR),(int)(OLD),(int)(NEW))	\
   : (__typeof__(*(PTR)))						\
-    __sync_val_compare_and_swap_di((long *)(void *)(PTR),(long)(OLD),(long)(NEW)))
+    __sync_val_compare_and_swap_8((long *)(void *)(PTR),(long)(OLD),(long)(NEW)))
 
-extern int __sync_bool_compare_and_swap_si (int *, int, int);
-extern int __sync_bool_compare_and_swap_di (long *, long, long);
 #define __sync_bool_compare_and_swap(PTR, OLD, NEW)			\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? __sync_bool_compare_and_swap_si((int *)(void *)(PTR),(int)(OLD),(int)(NEW))	\
-  : __sync_bool_compare_and_swap_di((long *)(void *)(PTR),(long)(OLD),(long)(NEW)))
+  ? __sync_bool_compare_and_swap_4((int *)(void *)(PTR),(int)(OLD),(int)(NEW))	\
+  : __sync_bool_compare_and_swap_8((long *)(void *)(PTR),(long)(OLD),(long)(NEW)))
 
-extern void __sync_lock_release_si (int *);
-extern void __sync_lock_release_di (long *);
 #define __sync_lock_release(PTR)		\
   ((sizeof (*(PTR)) == sizeof(int))		\
-   ? __sync_lock_release_si((int *)(void *)(PTR))	\
-   : __sync_lock_release_di((long *)(void *)(PTR)))
+   ? __sync_lock_release_4((int *)(void *)(PTR))	\
+   : __sync_lock_release_8((long *)(void *)(PTR)))
 
-extern int __sync_lock_test_and_set_si (int *, int);
-extern long __sync_lock_test_and_set_di (long *, long);
 #define __sync_lock_test_and_set(PTR,VAL)				\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_lock_test_and_set_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_lock_test_and_set_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_lock_test_and_set_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_lock_test_and_set_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_fetch_and_add_si (int *, int);
-extern long __sync_fetch_and_add_di (long *, long);
 #define __sync_fetch_and_add(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_fetch_and_add_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_fetch_and_add_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_fetch_and_add_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_fetch_and_add_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_fetch_and_sub_si (int *, int);
-extern long __sync_fetch_and_sub_di (long *, long);
 #define __sync_fetch_and_sub(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_fetch_and_sub_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_fetch_and_sub_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_fetch_and_sub_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_fetch_and_sub_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_fetch_and_and_si (int *, int);
-extern long __sync_fetch_and_and_di (long *, long);
 #define __sync_fetch_and_and(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_fetch_and_and_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_fetch_and_and_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_fetch_and_and_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_fetch_and_and_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_fetch_and_or_si (int *, int);
-extern long __sync_fetch_and_or_di (long *, long);
 #define __sync_fetch_and_or(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_fetch_and_or_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_fetch_and_or_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_fetch_and_or_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_fetch_and_or_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_fetch_and_xor_si (int *, int);
-extern long __sync_fetch_and_xor_di (long *, long);
 #define __sync_fetch_and_xor(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_fetch_and_xor_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_fetch_and_xor_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_fetch_and_xor_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_fetch_and_xor_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_fetch_and_nand_si (int *, int);
-extern long __sync_fetch_and_nand_di (long *, long);
 #define __sync_fetch_and_nand(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_fetch_and_nand_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_fetch_and_nand_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_fetch_and_nand_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_fetch_and_nand_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_add_and_fetch_si (int *, int);
-extern long __sync_add_and_fetch_di (long *, long);
 #define __sync_add_and_fetch(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_add_and_fetch_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_add_and_fetch_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_add_and_fetch_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_add_and_fetch_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_sub_and_fetch_si (int *, int);
-extern long __sync_sub_and_fetch_di (long *, long);
 #define __sync_sub_and_fetch(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_sub_and_fetch_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_sub_and_fetch_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_sub_and_fetch_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_sub_and_fetch_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_and_and_fetch_si (int *, int);
-extern long __sync_and_and_fetch_di (long *, long);
 #define __sync_and_and_fetch(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_and_and_fetch_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_and_and_fetch_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_and_and_fetch_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_and_and_fetch_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_or_and_fetch_si (int *, int);
-extern long __sync_or_and_fetch_di (long *, long);
 #define __sync_or_and_fetch(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_or_and_fetch_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_or_and_fetch_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_or_and_fetch_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_or_and_fetch_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_xor_and_fetch_si (int *, int);
-extern long __sync_xor_and_fetch_di (long *, long);
 #define __sync_xor_and_fetch(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_xor_and_fetch_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_xor_and_fetch_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_xor_and_fetch_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_xor_and_fetch_8((long *)(void *)(PTR),(long)(VAL)))
 
-extern int __sync_nand_and_fetch_si (int *, int);
-extern long __sync_nand_and_fetch_di (long *, long);
 #define __sync_nand_and_fetch(PTR,VAL)					\
  ((sizeof (*(PTR)) == sizeof(int))					\
-  ? (__typeof__(*(PTR))) __sync_nand_and_fetch_si((int *)(void *)(PTR),(int)(VAL)) \
-  : (__typeof__(*(PTR))) __sync_nand_and_fetch_di((long *)(void *)(PTR),(long)(VAL)))
+  ? (__typeof__(*(PTR))) __sync_nand_and_fetch_4((int *)(void *)(PTR),(int)(VAL)) \
+  : (__typeof__(*(PTR))) __sync_nand_and_fetch_8((long *)(void *)(PTR),(long)(VAL)))
 
-#ifdef __cplusplus
-}
-#endif
+#endif /* __cplusplus */
 
-#endif
+#endif /* _IA64INTRIN_H_INCLUDED */

gcc/config/ia64/sync.md

+;; GCC machine description for IA-64 synchronization instructions.
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+(define_mode_macro I48MODE [SI DI])
+(define_mode_attr modesuffix [(SI "4") (DI "8")])
+
+
+(define_expand "memory_barrier"
+  [(set (mem:BLK (match_dup 0))
+	(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
+  ""
+{
+  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
+  MEM_VOLATILE_P (operands[0]) = 1;
+})
+
+(define_insn "*mf_internal"
+  [(set (match_operand:BLK 0 "" "")
+	(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
+  ""
+  "mf"
+  [(set_attr "itanium_class" "syst_m")])
+
+(define_expand "sync_add<mode>"
+  [(match_operand:I48MODE 0 "gr_register_operand" "")
+   (match_operand:I48MODE 1 "memory_operand" "")
+   (match_operand:I48MODE 2 "general_operand" "")]
+  ""
+{
+  if (!fetchadd_operand (operands[2], <MODE>mode))
+    FAIL;
+  emit_insn (gen_memory_barrier ());
+  emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
+  DONE;
+})
+
+(define_expand "sync_old_add<mode>"
+  [(match_operand:I48MODE 0 "gr_register_operand" "")
+   (match_operand:I48MODE 1 "memory_operand" "")
+   (match_operand:I48MODE 2 "general_operand" "")]
+  ""
+{
+  if (!fetchadd_operand (operands[2], <MODE>mode))
+    FAIL;
+  emit_insn (gen_memory_barrier ());
+  emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
+  DONE;
+})
+
+(define_insn "fetchadd_acq_<mode>"
+  [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
+	(match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
+   (set (match_dup 1)
+	(unspec:I48MODE [(match_dup 1)
+			 (match_operand:I48MODE 2 "fetchadd_operand" "n")]
+		        UNSPEC_FETCHADD_ACQ))]
+  ""
+  "fetchadd<modesuffix>.acq %0 = %1, %2"
+  [(set_attr "itanium_class" "sem")])
+
+(define_expand "sync_compare_and_swap<mode>"
+  [(match_operand:I48MODE 0 "gr_register_operand" "")
+   (match_operand:I48MODE 1 "memory_operand" "")
+   (match_operand:I48MODE 2 "gr_register_operand" "")
+   (match_operand:I48MODE 3 "gr_register_operand" "")]
+  ""
+{
+  rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
+  convert_move (ccv, operands[2], 1);
+  emit_insn (gen_memory_barrier ());
+  emit_insn (gen_cmpxchg_acq_<mode> (operands[0], operands[1],
+				     ccv, operands[3]));
+  DONE;
+})
+
+(define_insn "cmpxchg_acq_<mode>"
+  [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
+	(match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
+   (set (match_dup 1)
+        (unspec:I48MODE [(match_dup 1)
+			 (match_operand:DI 2 "ar_ccv_reg_operand" "")
+			 (match_operand:I48MODE 3 "gr_register_operand" "r")]
+			UNSPEC_CMPXCHG_ACQ))]
+  ""
+  "cmpxchg<modesuffix>.acq %0 = %1, %3, %2"
+  [(set_attr "itanium_class" "sem")])
+
+(define_insn "sync_lock_test_and_set<mode>"
+  [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
+        (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
+   (set (match_dup 1)
+        (match_operand:I48MODE 2 "gr_register_operand" "r"))]
+  ""
+  "xchg<modesuffix> %0 = %1, %2"
+  [(set_attr "itanium_class" "sem")])
+
+(define_expand "sync_lock_release<mode>"
+  [(set (match_operand:I48MODE 0 "memory_operand" "")
+        (const_int 0))]
+  ""
+{
+  gcc_assert (MEM_VOLATILE_P (operands[0]));
+})