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riscv-gcc-1
Commit aebf2462 by Jim Wilson Committed by Jim Wilson
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Delete A step Itanium support. 

	* config/ia64/ia64.c (ia64_print_operand_address): Delete 'B' support.
	(fixup_errata): Delete TARGET_A_STEP use.
	* config/ia64/ia64.h (MASK_A_STEP, TARGET_A_STEP): Delete.
	(TARGET_SWITCHES): Delete -ma-step option.
	* config/ia64/ia64.md (all FP patterns): Delete %B0.
	(movqicc_astep, movqi_internal_astep, movhicc_astep,
	movhi_internal_astep, movsicc_astep, movsi_internal_astep, movdi+1,
	movdi_internal_astep, movsfcc_astep, movsf_internal_astep,
	movdfcc_astep, movdf_internal_astep, movtfcc_astep,
	movtf_internal_astep, cmovdi_internal_astep, cmovsi_internal_astep):
	Delete.
	(movqi_internal, movhi_internal, movsi_internal, movdi_internal,
	movsf_internal, movdf_internal, movtf_internal, cmovdi_internal,
	cmovsi_internal): Delete ! TARGET_A_STEP check.

From-SVN: r39075
parent aebb127a
Showing with 119 additions and 436 deletions
gcc/ChangeLog
2001-01-16 Jim Wilson <wilson@redhat.com>
* config/ia64/ia64.c (ia64_print_operand_address): Delete 'B' support.
(fixup_errata): Delete TARGET_A_STEP use.
* config/ia64/ia64.h (MASK_A_STEP, TARGET_A_STEP): Delete.
(TARGET_SWITCHES): Delete -ma-step option.
* config/ia64/ia64.md (all FP patterns): Delete %B0.
(movqicc_astep, movqi_internal_astep, movhicc_astep,
movhi_internal_astep, movsicc_astep, movsi_internal_astep, movdi+1,
movdi_internal_astep, movsfcc_astep, movsf_internal_astep,
movdfcc_astep, movdf_internal_astep, movtfcc_astep,
movtf_internal_astep, cmovdi_internal_astep, cmovsi_internal_astep):
Delete.
(movqi_internal, movhi_internal, movsi_internal, movdi_internal,
movsf_internal, movdf_internal, movtf_internal, cmovdi_internal,
cmovsi_internal): Delete ! TARGET_A_STEP check.
2001-01-16 Gerald Pfeifer <pfeifer@dbai.tuwien.ac.at>
* gcc.texi (Bug Lists): Do not mention newsgroups nor the
......
gcc/config/ia64/ia64.c
......@@ -3133,7 +3133,6 @@ ia64_print_operand_address (stream, address)
}
/* Print an operand to a assembler instruction.
B Work arounds for hardware bugs.
C Swap and print a comparison operator.
D Print an FP comparison operator.
E Print 32 - constant, for SImode shifts as extract.
......@@ -3167,11 +3166,6 @@ ia64_print_operand (file, x, code)
/* Handled below. */
break;
case 'B':
if (TARGET_A_STEP)
fputs (" ;; nop 0 ;; nop 0 ;;", file);
return;
case 'C':
{
enum rtx_code c = swap_condition (GET_CODE (x));
......@@ -4684,7 +4678,7 @@ fixup_errata ()
group_idx = (group_idx + 1) % 3;
memset (last_group + group_idx, 0, sizeof last_group[group_idx]);
}
if ((TARGET_B_STEP || TARGET_A_STEP) && INSN_P (insn))
if (TARGET_B_STEP && INSN_P (insn))
errata_emit_nops (insn);
}
}
......
gcc/config/ia64/ia64.h
......@@ -53,7 +53,7 @@ extern int target_flags;
#define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
#define MASK_A_STEP 0x00000020 /* Emit code for Itanium A step. */
/* 0x00000020 is available. */
#define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
......@@ -81,8 +81,6 @@ extern int target_flags;
#define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
#define TARGET_A_STEP (target_flags & MASK_A_STEP)
#define TARGET_B_STEP (target_flags & MASK_B_STEP)
#define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
......@@ -126,8 +124,6 @@ extern int target_flags;
N_("Emit stop bits before and after volatile extended asms") }, \
{ "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
N_("Don't emit stop bits before and after volatile extended asms") }, \
{ "a-step", MASK_A_STEP, \
N_("Emit code for Itanium (TM) processor A step")}, \
{ "b-step", MASK_B_STEP, \
N_("Emit code for Itanium (TM) processor B step")}, \
{ "register-names", MASK_REG_NAMES, \
......
gcc/config/ia64/ia64.md
......@@ -279,49 +279,10 @@
operands[1] = force_reg (QImode, operands[1]);
}")
;; Errata 72 implies that we cannot use predicated loads and stores
;; on affected systems. Reuse TARGET_A_STEP for convenience.
;; ??? It would be convenient at this point if the cond_exec pattern
;; expander understood non-constant conditions on attributes. Failing
;; that we have to replicate patterns.
(define_insn "*movqicc_astep"
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c,c,c,c,c")
(const_int 0)])
(set (match_operand:QI 0 "register_operand" "=r,r, r,*f,*f")
(match_operand:QI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
(%J2) mov %0 = %r1
(%J2) addl %0 = %1, r0
(%J2) getf.sig %0 = %1
(%J2) setf.sig %0 = %r1
(%J2) mov %0 = %1"
[(set_attr "itanium_class" "ialu,ialu,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movqi_internal_astep"
[(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
(match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %r1
addl %0 = %1, r0
ld1%O1 %0 = %1%P1
st1%Q0 %0 = %r1%P0
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
[(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
(match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %r1
addl %0 = %1, r0
......@@ -343,43 +304,10 @@
operands[1] = force_reg (HImode, operands[1]);
}")
;; Errata 72 workaround.
(define_insn "*movhicc_astep"
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c,c,c,c,c")
(const_int 0)])
(set (match_operand:HI 0 "register_operand" "=r,r, r,*f,*f")
(match_operand:HI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
(%J2) mov %0 = %r1
(%J2) addl %0 = %1, r0
(%J2) getf.sig %0 = %1
(%J2) setf.sig %0 = %r1
(%J2) mov %0 = %1"
[(set_attr "itanium_class" "ialu,ialu,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movhi_internal_astep"
[(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
(match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %r1
addl %0 = %1, r0
ld2%O1 %0 = %1%P1
st2%Q0 %0 = %r1%P0
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
[(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
(match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %r1
addl %0 = %1, r0
......@@ -401,51 +329,10 @@
operands[1] = force_reg (SImode, operands[1]);
}")
;; Errata 72 workaround.
(define_insn "*movsicc_astep"
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c")
(const_int 0)])
(set (match_operand:SI 0 "register_operand" "=r,r,r, r,*f,*f, r,*d")
(match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f,*d,rK")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
(%J2) mov %0 = %r1
(%J2) addl %0 = %1, r0
(%J2) movl %0 = %1
(%J2) getf.sig %0 = %1
(%J2) setf.sig %0 = %r1
(%J2) mov %0 = %1
(%J2) mov %0 = %1
(%J2) mov %0 = %r1"
;; frar_m, toar_m ??? why not frar_i and toar_i
[(set_attr "itanium_class" "ialu,ialu,long_i,frfr,tofr,fmisc,frar_m,toar_m")
(set_attr "predicable" "no")])
(define_insn "*movsi_internal_astep"
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %r1
addl %0 = %1, r0
movl %0 = %1
ld4%O1 %0 = %1%P1
st4%Q0 %0 = %r1%P0
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1
mov %0 = %1
mov %0 = %r1"
;; frar_m, toar_m ??? why not frar_i and toar_i
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
(set_attr "predicable" "no")])
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %r1
addl %0 = %1, r0
......@@ -491,54 +378,6 @@
}
}")
;; Errata 72 workaround.
(define_insn ""
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c,c")
(const_int 0)])
(set (match_operand:DI 0 "register_operand"
"=r,r,r, r,*f,*f, r,*b, r,*e, r,*d")
(match_operand:DI 1 "nonmemory_operand"
"rO,J,i,*f,rO,*f,*b,rO,*e,rK,*d,rK")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"*
{
static const char * const alt[] = {
\"(%J2) mov %0 = %r1\",
\"(%J2) addl %0 = %1, r0\",
\"(%J2) movl %0 = %1\",
\"(%J2) getf.sig %0 = %1\",
\"(%J2) setf.sig %0 = %r1\",
\"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %r1\",
\"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %1\"
};
/* We use 'i' for alternative 2 despite possible PIC problems.
If we define LEGITIMATE_CONSTANT_P such that symbols are not
allowed, then the compiler dumps the data into constant memory
instead of letting us read the values from the GOT. Similarly
if we use 'n' instead of 'i'.
Instead, we allow such insns through reload and then split them
afterward (even without optimization). Therefore, we should
never get so far with a symbolic operand. */
if (which_alternative == 2 && ! TARGET_NO_PIC
&& symbolic_operand (operands[1], VOIDmode))
abort ();
return alt[which_alternative];
}"
[(set_attr "itanium_class" "ialu,ialu,long_i,frfr,tofr,fmisc,frbr,tobr,frar_i,toar_i,frar_m,toar_m")
(set_attr "predicable" "no")])
;; This is used during early compilation to delay the decision on
;; how to refer to a variable as long as possible. This is especially
;; important between initial rtl generation and optimization for
......@@ -559,50 +398,12 @@
[(const_int 0)]
"ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;")
(define_insn "*movdi_internal_astep"
[(set (match_operand:DI 0 "destination_operand"
"=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
(match_operand:DI 1 "move_operand"
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"*
{
static const char * const alt[] = {
\"mov %0 = %r1\",
\"addl %0 = %1, r0\",
\"movl %0 = %1\",
\"ld8%O1 %0 = %1%P1\",
\"st8%Q0 %0 = %r1%P0\",
\"getf.sig %0 = %1\",
\"setf.sig %0 = %r1\",
\"mov %0 = %1\",
\"ldf8 %0 = %1%P1\",
\"stf8 %0 = %1%P0\",
\"mov %0 = %1\",
\"mov %0 = %r1\",
\"mov %0 = %1\",
\"mov %0 = %1\",
\"mov %0 = %1\",
\"mov %0 = %1\",
\"mov %0 = pr\",
\"mov pr = %1, -1\"
};
if (which_alternative == 2 && ! TARGET_NO_PIC
&& symbolic_operand (operands[1], VOIDmode))
abort ();
return alt[which_alternative];
}"
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
(set_attr "predicable" "no")])
(define_insn "*movdi_internal"
[(set (match_operand:DI 0 "destination_operand"
"=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
(match_operand:DI 1 "move_operand"
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"*
{
static const char * const alt[] = {
......@@ -835,43 +636,10 @@
operands[1] = force_reg (SFmode, operands[1]);
}")
;; Errata 72 workaround.
(define_insn "*movsfcc_astep"
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c,c,c,c")
(const_int 0)])
(set (match_operand:SF 0 "register_operand" "=f,*r, f,*r")
(match_operand:SF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
(%J2) mov %0 = %F1
(%J2) getf.s %0 = %F1
(%J2) setf.s %0 = %1
(%J2) mov %0 = %1"
[(set_attr "itanium_class" "fmisc,frfr,tofr,ialu")
(set_attr "predicable" "no")])
(define_insn "*movsf_internal_astep"
[(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfs %0 = %1%P1
stfs %0 = %F1%P0
getf.s %0 = %F1
setf.s %0 = %1
mov %0 = %1
ld4%O1 %0 = %1%P1
st4%Q0 %0 = %1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
(set_attr "predicable" "no")])
(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfs %0 = %1%P1
......@@ -894,43 +662,10 @@
operands[1] = force_reg (DFmode, operands[1]);
}")
;; Errata 72 workaround.
(define_insn "*movdfcc_astep"
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c,c,c,c")
(const_int 0)])
(set (match_operand:DF 0 "register_operand" "=f,*r, f,*r")
(match_operand:DF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
(%J2) mov %0 = %F1
(%J2) getf.d %0 = %F1
(%J2) setf.d %0 = %1
(%J2) mov %0 = %1"
[(set_attr "itanium_class" "fmisc,frfr,tofr,ialu")
(set_attr "predicable" "no")])
(define_insn "*movdf_internal_astep"
[(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfd %0 = %1%P1
stfd %0 = %F1%P0
getf.d %0 = %F1
setf.d %0 = %1
mov %0 = %1
ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
(set_attr "predicable" "no")])
(define_insn "*movdf_internal"
[(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfd %0 = %1%P1
......@@ -1016,34 +751,10 @@
;; ??? There's no easy way to mind volatile acquire/release semantics.
;; Errata 72 workaround.
(define_insn "*movtfcc_astep"
[(cond_exec
(match_operator 2 "predicate_operator"
[(match_operand:BI 3 "register_operand" "c")
(const_int 0)])
(set (match_operand:TF 0 "register_operand" "=f")
(match_operand:TF 1 "nonmemory_operand" "fG")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"(%J2) mov %0 = %F1"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
(define_insn "*movtf_internal_astep"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
stfe %0 = %F1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf")
(set_attr "predicable" "no")])
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
......@@ -1078,7 +789,7 @@
""
"@
sxt4 %0 = %1
fsxt.r %0 = %1, %1%B0"
fsxt.r %0 = %1, %1"
[(set_attr "itanium_class" "xtd,fmisc")])
;; Unsigned conversions from a smaller integer to a larger integer
......@@ -1109,7 +820,7 @@
"@
zxt4 %0 = %1
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1%B0"
fmix.r %0 = f0, %1"
[(set_attr "itanium_class" "xtd,ld,fmisc")])
;; Convert between floating point types of different sizes.
......@@ -1193,21 +904,21 @@
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fnorm.s %0 = %1%B0"
"fnorm.s %0 = %1"
[(set_attr "itanium_class" "fmac")])
(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fnorm.s %0 = %1%B0"
"fnorm.s %0 = %1"
[(set_attr "itanium_class" "fmac")])
(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fnorm.d %0 = %1%B0"
"fnorm.d %0 = %1"
[(set_attr "itanium_class" "fmac")])
;; Convert between signed integer types and floating point.
......@@ -1223,21 +934,21 @@
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_trunctfdi2_alts"
......@@ -1245,7 +956,7 @@
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
""
"fcvt.fx.trunc.s%2 %0 = %1%B0"
"fcvt.fx.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
;; Convert between unsigned integer types and floating point.
......@@ -1254,42 +965,42 @@
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xuf.s %0 = %1%B0"
"fcvt.xuf.s %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "floatunsdidf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xuf.d %0 = %1%B0"
"fcvt.xuf.d %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "floatunsditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xuf %0 = %1%B0"
"fcvt.xuf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_trunctfdi2_alts"
......@@ -1297,7 +1008,7 @@
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
""
"fcvt.fxu.trunc.s%2 %0 = %1%B0"
"fcvt.fxu.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
;; ::::::::::::::::::::
......@@ -2091,7 +1802,7 @@
(mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
(match_operand:SI 2 "grfr_register_operand" "f")))]
""
"xmpy.l %0 = %1, %2%B0"
"xmpy.l %0 = %1, %2"
[(set_attr "itanium_class" "xmpy")])
(define_insn "maddsi4"
......@@ -2100,7 +1811,7 @@
(match_operand:SI 2 "grfr_register_operand" "f"))
(match_operand:SI 3 "grfr_register_operand" "f")))]
""
"xma.l %0 = %1, %2, %3%B0"
"xma.l %0 = %1, %2, %3"
[(set_attr "itanium_class" "xmpy")])
(define_insn "negsi2"
......@@ -2403,7 +2114,7 @@
(mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
(match_operand:DI 2 "grfr_register_operand" "f")))]
""
"xmpy.l %0 = %1, %2%B0"
"xmpy.l %0 = %1, %2"
[(set_attr "itanium_class" "xmpy")])
;; ??? If operand 3 is an eliminable reg, then register elimination causes the
......@@ -2424,7 +2135,7 @@
(match_operand:DI 3 "grfr_register_operand" "f")))
(clobber (match_scratch:DI 4 "=X"))]
""
"xma.l %0 = %1, %2, %3%B0"
"xma.l %0 = %1, %2, %3"
[(set_attr "itanium_class" "xmpy")])
;; This can be created by register elimination if operand3 of shladd is an
......@@ -2474,7 +2185,7 @@
(match_operand:DI 2 "fr_register_operand" "f")))
(const_int 64))))]
""
"xmpy.h %0 = %1, %2%B0"
"xmpy.h %0 = %1, %2"
[(set_attr "itanium_class" "xmpy")])
(define_insn "umuldi3_highpart"
......@@ -2487,7 +2198,7 @@
(match_operand:DI 2 "fr_register_operand" "f")))
(const_int 64))))]
""
"xmpy.hu %0 = %1, %2%B0"
"xmpy.hu %0 = %1, %2"
[(set_attr "itanium_class" "xmpy")])
(define_insn "negdi2"
......@@ -2803,7 +2514,7 @@
(plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fadd.s %0 = %1, %F2%B0"
"fadd.s %0 = %1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "subsf3"
......@@ -2811,7 +2522,7 @@
(minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fsub.s %0 = %F1, %F2%B0"
"fsub.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "mulsf3"
......@@ -2819,28 +2530,28 @@
(mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
(match_operand:SF 2 "fr_register_operand" "f")))]
""
"fmpy.s %0 = %1, %2%B0"
"fmpy.s %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fabs %0 = %1%B0"
"fabs %0 = %1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fneg %0 = %1%B0"
"fneg %0 = %1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabssf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
""
"fnegabs %0 = %1%B0"
"fnegabs %0 = %1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "minsf3"
......@@ -2848,7 +2559,7 @@
(smin:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmin %0 = %1, %F2%B0"
"fmin %0 = %1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "maxsf3"
......@@ -2856,7 +2567,7 @@
(smax:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmax %0 = %1, %F2%B0"
"fmax %0 = %1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*maddsf4"
......@@ -2865,7 +2576,7 @@
(match_operand:SF 2 "fr_register_operand" "f"))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fma.s %0 = %1, %2, %F3%B0"
"fma.s %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubsf4"
......@@ -2874,7 +2585,7 @@
(match_operand:SF 2 "fr_register_operand" "f"))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fms.s %0 = %1, %2, %F3%B0"
"fms.s %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmulsf3"
......@@ -2882,7 +2593,7 @@
(neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_register_operand" "f"))))]
""
"fnmpy.s %0 = %1, %2%B0"
"fnmpy.s %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
......@@ -2894,7 +2605,7 @@
(match_operand:SF 2 "fr_register_operand" "f")))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fnma.s %0 = %1, %2, %F3%B0"
"fnma.s %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_expand "divsf3"
......@@ -3029,7 +2740,7 @@
(plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fadd.d %0 = %1, %F2%B0"
"fadd.d %0 = %1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*adddf3_trunc"
......@@ -3038,7 +2749,7 @@
(plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"fadd.s %0 = %1, %F2%B0"
"fadd.s %0 = %1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "subdf3"
......@@ -3046,7 +2757,7 @@
(minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fsub.d %0 = %F1, %F2%B0"
"fsub.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*subdf3_trunc"
......@@ -3055,7 +2766,7 @@
(minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"fsub.s %0 = %F1, %F2%B0"
"fsub.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "muldf3"
......@@ -3063,7 +2774,7 @@
(mult:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f")))]
""
"fmpy.d %0 = %1, %2%B0"
"fmpy.d %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*muldf3_trunc"
......@@ -3072,28 +2783,28 @@
(mult:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f"))))]
""
"fmpy.s %0 = %1, %2%B0"
"fmpy.s %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fabs %0 = %1%B0"
"fabs %0 = %1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fneg %0 = %1%B0"
"fneg %0 = %1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabsdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
""
"fnegabs %0 = %1%B0"
"fnegabs %0 = %1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "mindf3"
......@@ -3101,7 +2812,7 @@
(smin:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmin %0 = %1, %F2%B0"
"fmin %0 = %1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "maxdf3"
......@@ -3109,7 +2820,7 @@
(smax:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmax %0 = %1, %F2%B0"
"fmax %0 = %1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*madddf4"
......@@ -3118,7 +2829,7 @@
(match_operand:DF 2 "fr_register_operand" "f"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fma.d %0 = %1, %2, %F3%B0"
"fma.d %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*madddf4_trunc"
......@@ -3128,7 +2839,7 @@
(match_operand:DF 2 "fr_register_operand" "f"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"fma.s %0 = %1, %2, %F3%B0"
"fma.s %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubdf4"
......@@ -3137,7 +2848,7 @@
(match_operand:DF 2 "fr_register_operand" "f"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fms.d %0 = %1, %2, %F3%B0"
"fms.d %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubdf4_trunc"
......@@ -3147,7 +2858,7 @@
(match_operand:DF 2 "fr_register_operand" "f"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"fms.s %0 = %1, %2, %F3%B0"
"fms.s %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmuldf3"
......@@ -3155,7 +2866,7 @@
(neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f"))))]
""
"fnmpy.d %0 = %1, %2%B0"
"fnmpy.d %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmuldf3_trunc"
......@@ -3164,7 +2875,7 @@
(neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f")))))]
""
"fnmpy.s %0 = %1, %2%B0"
"fnmpy.s %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
......@@ -3176,7 +2887,7 @@
(match_operand:DF 2 "fr_register_operand" "f")))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fnma.d %0 = %1, %2, %F3%B0"
"fnma.d %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_alts"
......@@ -3187,7 +2898,7 @@
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fnma.d.s%4 %0 = %1, %2, %F3%B0"
"fnma.d.s%4 %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_trunc"
......@@ -3198,7 +2909,7 @@
(match_operand:DF 2 "fr_register_operand" "f")))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"fnma.s %0 = %1, %2, %F3%B0"
"fnma.s %0 = %1, %2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_expand "divdf3"
......@@ -3369,7 +3080,7 @@
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fadd %0 = %F1, %F2%B0"
"fadd %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*addtf3_truncsf"
......@@ -3378,7 +3089,7 @@
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fadd.s %0 = %F1, %F2%B0"
"fadd.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*addtf3_truncdf"
......@@ -3387,7 +3098,7 @@
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fadd.d %0 = %F1, %F2%B0"
"fadd.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "subtf3"
......@@ -3395,7 +3106,7 @@
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fsub %0 = %F1, %F2%B0"
"fsub %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*subtf3_truncsf"
......@@ -3404,7 +3115,7 @@
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fsub.s %0 = %F1, %F2%B0"
"fsub.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*subtf3_truncdf"
......@@ -3413,7 +3124,7 @@
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fsub.d %0 = %F1, %F2%B0"
"fsub.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "multf3"
......@@ -3421,7 +3132,7 @@
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fmpy %0 = %F1, %F2%B0"
"fmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncsf"
......@@ -3430,7 +3141,7 @@
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fmpy.s %0 = %F1, %F2%B0"
"fmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncdf"
......@@ -3439,7 +3150,7 @@
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fmpy.d %0 = %F1, %F2%B0"
"fmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_alts"
......@@ -3448,7 +3159,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 3 "const_int_operand" ""))]
""
"fmpy.s%3 %0 = %F1, %F2%B0"
"fmpy.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncsf_alts"
......@@ -3458,7 +3169,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
""
"fmpy.s.s%3 %0 = %F1, %F2%B0"
"fmpy.s.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncdf_alts"
......@@ -3468,28 +3179,28 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
""
"fmpy.d.s%3 %0 = %F1, %F2%B0"
"fmpy.d.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "abstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
""
"fabs %0 = %F1%B0"
"fabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negtf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
""
"fneg %0 = %F1%B0"
"fneg %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
""
"fnegabs %0 = %F1%B0"
"fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "mintf3"
......@@ -3497,7 +3208,7 @@
(smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fmin %0 = %F1, %F2%B0"
"fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "maxtf3"
......@@ -3505,7 +3216,7 @@
(smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fmax %0 = %F1, %F2%B0"
"fmax %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*maddtf4"
......@@ -3514,7 +3225,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
""
"fma %0 = %F1, %F2, %F3%B0"
"fma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_truncsf"
......@@ -3524,7 +3235,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fma.s %0 = %F1, %F2, %F3%B0"
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_truncdf"
......@@ -3534,7 +3245,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fma.d %0 = %F1, %F2, %F3%B0"
"fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_alts"
......@@ -3544,7 +3255,7 @@
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fma.s%4 %0 = %F1, %F2, %F3%B0"
"fma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_alts_truncdf"
......@@ -3555,7 +3266,7 @@
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fma.d.s%4 %0 = %F1, %F2, %F3%B0"
"fma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubtf4"
......@@ -3564,7 +3275,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
""
"fms %0 = %F1, %F2, %F3%B0"
"fms %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubtf4_truncsf"
......@@ -3574,7 +3285,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fms.s %0 = %F1, %F2, %F3%B0"
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubtf4_truncdf"
......@@ -3584,7 +3295,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fms.d %0 = %F1, %F2, %F3%B0"
"fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmultf3"
......@@ -3592,7 +3303,7 @@
(neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fnmpy %0 = %F1, %F2%B0"
"fnmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmultf3_truncsf"
......@@ -3602,7 +3313,7 @@
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
""
"fnmpy.s %0 = %F1, %F2%B0"
"fnmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmultf3_truncdf"
......@@ -3612,7 +3323,7 @@
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
""
"fnmpy.d %0 = %F1, %F2%B0"
"fnmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
......@@ -3624,7 +3335,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
""
"fnma %0 = %F1, %F2, %F3%B0"
"fnma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_truncsf"
......@@ -3635,7 +3346,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fnma.s %0 = %F1, %F2, %F3%B0"
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_truncdf"
......@@ -3646,7 +3357,7 @@
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fnma.d %0 = %F1, %F2, %F3%B0"
"fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_alts"
......@@ -3657,7 +3368,7 @@
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fnma.s%4 %0 = %F1, %F2, %F3%B0"
"fnma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_truncdf_alts"
......@@ -3670,7 +3381,7 @@
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fnma.d.s%4 %0 = %F1, %F2, %F3%B0"
"fnma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_expand "divtf3"
......@@ -4156,7 +3867,7 @@
""
"@
and %0 = %2, %1
fand %0 = %2, %1%B0"
fand %0 = %2, %1"
[(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "*andnot"
......@@ -4166,7 +3877,7 @@
""
"@
andcm %0 = %2, %1
fandcm %0 = %2, %1%B0"
fandcm %0 = %2, %1"
[(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "iordi3"
......@@ -4176,7 +3887,7 @@
""
"@
or %0 = %2, %1
for %0 = %2, %1%B0"
for %0 = %2, %1"
[(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "xordi3"
......@@ -4186,7 +3897,7 @@
""
"@
xor %0 = %2, %1
fxor %0 = %2, %1%B0"
fxor %0 = %2, %1"
[(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "one_cmpldi2"
......@@ -4636,25 +4347,6 @@
;; DImode if_then_else patterns.
;;
;; Errata 72 workaround.
(define_insn "*cmovdi_internal_astep"
[(set (match_operand:DI 0 "register_operand"
"=r, r, r, r, r, r, r, r, r, r,*f,*b,*d*e")
(if_then_else:DI
(match_operator 4 "predicate_operator"
[(match_operand:BI 1 "register_operand"
" c, c, c, c, c, c, c, c, c, c, c, c, c")
(const_int 0)])
(match_operand:DI 2 "move_operand"
"ri,*f,*b,*d*e,ri,ri, ri,*f,*b,*d*e,rO,rO, rK")
(match_operand:DI 3 "move_operand"
"ri,ri,ri, ri,*f,*b,*d*e,*f,*b,*d*e,rO,rO, rK")))]
"TARGET_A_STEP
&& ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])"
"* abort ();"
[(set_attr "predicable" "no")])
(define_insn "*cmovdi_internal"
[(set (match_operand:DI 0 "destination_operand"
"= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
......@@ -4667,8 +4359,7 @@
"rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
(match_operand:DI 3 "move_operand"
"rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
"! TARGET_A_STEP
&& ia64_move_ok (operands[0], operands[2])
"ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])"
"* abort ();"
[(set_attr "predicable" "no")])
......@@ -4759,20 +4450,6 @@
;; SImode if_then_else patterns.
;;
(define_insn "*cmovsi_internal_astep"
[(set (match_operand:SI 0 "register_operand" "=r,*f,r,*f,r,*f")
(if_then_else:SI
(match_operator 4 "predicate_operator"
[(match_operand:BI 1 "register_operand" "c,c,c,c,c,c")
(const_int 0)])
(match_operand:SI 2 "move_operand" "0,0,ri*f,rO,ri*f,rO")
(match_operand:SI 3 "move_operand" "ri*f,rO,0,0,ri*f,rO")))]
"TARGET_A_STEP
&& ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])"
"* abort ();"
[(set_attr "predicable" "no")])
(define_insn "*cmovsi_internal"
[(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
(if_then_else:SI
......@@ -4783,8 +4460,7 @@
"0,0,0,rim*f,rO,rO,rim*f,rO,rO")
(match_operand:SI 3 "move_operand"
"rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
"! TARGET_A_STEP
&& ia64_move_ok (operands[0], operands[2])
"ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])"
"* abort ();"
[(set_attr "predicable" "no")])
......
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