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lvzhengyang
riscv-gcc-1
Commits
ad2c71b7
Commit
ad2c71b7
authored
Jun 29, 1998
by
Jeffrey A Law
Committed by
Jeff Law
Jun 29, 1998
Browse files
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Browse Files
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Plain Diff
* pa.c, pa.h, pa.md: Convert to gen_rtx_FOO.
From-SVN: r20806
parent
2880d0aa
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4 changed files
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220 additions
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206 deletions
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-206
gcc/ChangeLog
+4
-0
gcc/config/pa/pa.c
+180
-168
gcc/config/pa/pa.h
+11
-11
gcc/config/pa/pa.md
+25
-27
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gcc/ChangeLog
View file @
ad2c71b7
Mon Jun 29 22:12:06 1998 Jeffrey A Law (law@cygnus.com)
* pa.c, pa.h, pa.md: Convert to gen_rtx_FOO.
Mon Jun 29 20:12:41 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
Mon Jun 29 20:12:41 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* Makefile.in (fix-header): Don't needlessly depend on cpperror.o.
* Makefile.in (fix-header): Don't needlessly depend on cpperror.o.
...
...
gcc/config/pa/pa.c
View file @
ad2c71b7
...
@@ -613,13 +613,17 @@ legitimize_pic_address (orig, mode, reg)
...
@@ -613,13 +613,17 @@ legitimize_pic_address (orig, mode, reg)
if
(
flag_pic
==
2
)
if
(
flag_pic
==
2
)
{
{
emit_insn
(
gen_pic2_highpart
(
reg
,
pic_offset_table_rtx
,
orig
));
emit_insn
(
gen_pic2_highpart
(
reg
,
pic_offset_table_rtx
,
orig
));
pic_ref
=
gen_rtx
(
MEM
,
Pmode
,
pic_ref
gen_rtx
(
LO_SUM
,
Pmode
,
reg
,
=
gen_rtx_MEM
(
Pmode
,
gen_rtx
(
UNSPEC
,
SImode
,
gen_rtvec
(
1
,
orig
),
0
)));
gen_rtx_LO_SUM
(
Pmode
,
reg
,
gen_rtx_UNSPEC
(
SImode
,
gen_rtvec
(
1
,
orig
),
0
)));
}
}
else
else
pic_ref
=
gen_rtx
(
MEM
,
Pmode
,
pic_ref
=
gen_rtx_MEM
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
pic_offset_table_rtx
,
orig
));
gen_rtx_PLUS
(
Pmode
,
pic_offset_table_rtx
,
orig
));
current_function_uses_pic_offset_table
=
1
;
current_function_uses_pic_offset_table
=
1
;
RTX_UNCHANGING_P
(
pic_ref
)
=
1
;
RTX_UNCHANGING_P
(
pic_ref
)
=
1
;
emit_move_insn
(
reg
,
pic_ref
);
emit_move_insn
(
reg
,
pic_ref
);
...
@@ -649,7 +653,7 @@ legitimize_pic_address (orig, mode, reg)
...
@@ -649,7 +653,7 @@ legitimize_pic_address (orig, mode, reg)
return
plus_constant_for_output
(
base
,
INTVAL
(
orig
));
return
plus_constant_for_output
(
base
,
INTVAL
(
orig
));
orig
=
force_reg
(
Pmode
,
orig
);
orig
=
force_reg
(
Pmode
,
orig
);
}
}
pic_ref
=
gen_rtx
(
PLUS
,
Pmode
,
base
,
orig
);
pic_ref
=
gen_rtx
_PLUS
(
Pmode
,
base
,
orig
);
/* Likewise, should we set special REG_NOTEs here? */
/* Likewise, should we set special REG_NOTEs here? */
}
}
return
pic_ref
;
return
pic_ref
;
...
@@ -727,7 +731,7 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -727,7 +731,7 @@ hppa_legitimize_address (x, oldx, mode)
&&
GET_CODE
(
XEXP
(
x
,
1
))
==
SYMBOL_REF
)
&&
GET_CODE
(
XEXP
(
x
,
1
))
==
SYMBOL_REF
)
{
{
rtx
reg
=
force_reg
(
SImode
,
XEXP
(
x
,
1
));
rtx
reg
=
force_reg
(
SImode
,
XEXP
(
x
,
1
));
return
force_reg
(
SImode
,
gen_rtx
(
PLUS
,
SImode
,
reg
,
XEXP
(
x
,
0
)));
return
force_reg
(
SImode
,
gen_rtx
_PLUS
(
SImode
,
reg
,
XEXP
(
x
,
0
)));
}
}
/* Note we must reject symbols which represent function addresses
/* Note we must reject symbols which represent function addresses
...
@@ -759,17 +763,16 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -759,17 +763,16 @@ hppa_legitimize_address (x, oldx, mode)
if
(
!
VAL_14_BITS_P
(
newoffset
)
if
(
!
VAL_14_BITS_P
(
newoffset
)
&&
GET_CODE
(
XEXP
(
x
,
0
))
==
SYMBOL_REF
)
&&
GET_CODE
(
XEXP
(
x
,
0
))
==
SYMBOL_REF
)
{
{
rtx
const_part
=
gen_rtx
(
CONST
,
VOIDmode
,
rtx
const_part
gen_rtx
(
PLUS
,
Pmode
,
=
gen_rtx_CONST
(
VOIDmode
,
gen_rtx_PLUS
(
Pmode
,
XEXP
(
x
,
0
),
XEXP
(
x
,
0
),
GEN_INT
(
newoffset
)));
GEN_INT
(
newoffset
)));
rtx
tmp_reg
rtx
tmp_reg
=
force_reg
(
Pmode
,
=
force_reg
(
Pmode
,
gen_rtx
(
HIGH
,
Pmode
,
const_part
));
gen_rtx
_HIGH
(
Pmode
,
const_part
));
ptr_reg
ptr_reg
=
force_reg
(
Pmode
,
=
force_reg
(
Pmode
,
gen_rtx
(
LO_SUM
,
Pmode
,
gen_rtx_LO_SUM
(
Pmode
,
tmp_reg
,
const_part
));
tmp_reg
,
const_part
));
}
}
else
else
{
{
...
@@ -779,7 +782,7 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -779,7 +782,7 @@ hppa_legitimize_address (x, oldx, mode)
int_part
=
GEN_INT
(
newoffset
);
int_part
=
GEN_INT
(
newoffset
);
ptr_reg
=
force_reg
(
Pmode
,
ptr_reg
=
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
gen_rtx
_PLUS
(
Pmode
,
force_reg
(
Pmode
,
XEXP
(
x
,
0
)),
force_reg
(
Pmode
,
XEXP
(
x
,
0
)),
int_part
));
int_part
));
}
}
...
@@ -806,9 +809,9 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -806,9 +809,9 @@ hppa_legitimize_address (x, oldx, mode)
if
(
GET_CODE
(
reg2
)
!=
REG
)
if
(
GET_CODE
(
reg2
)
!=
REG
)
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
return
force_reg
(
Pmode
,
gen_rtx
_PLUS
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
gen_rtx_MULT
(
Pmode
,
reg2
,
reg2
,
GEN_INT
(
val
)),
GEN_INT
(
val
)),
reg1
));
reg1
));
}
}
...
@@ -848,8 +851,8 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -848,8 +851,8 @@ hppa_legitimize_address (x, oldx, mode)
{
{
base
=
reg1
;
base
=
reg1
;
orig_base
=
XEXP
(
XEXP
(
x
,
0
),
1
);
orig_base
=
XEXP
(
XEXP
(
x
,
0
),
1
);
idx
=
gen_rtx
(
PLUS
,
Pmode
,
idx
=
gen_rtx
_PLUS
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
gen_rtx_MULT
(
Pmode
,
XEXP
(
XEXP
(
XEXP
(
x
,
0
),
0
),
0
),
XEXP
(
XEXP
(
XEXP
(
x
,
0
),
0
),
0
),
XEXP
(
XEXP
(
XEXP
(
x
,
0
),
0
),
1
)),
XEXP
(
XEXP
(
XEXP
(
x
,
0
),
0
),
1
)),
XEXP
(
x
,
1
));
XEXP
(
x
,
1
));
...
@@ -880,11 +883,12 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -880,11 +883,12 @@ hppa_legitimize_address (x, oldx, mode)
if
(
GET_CODE
(
reg1
)
!=
REG
)
if
(
GET_CODE
(
reg1
)
!=
REG
)
reg1
=
force_reg
(
Pmode
,
force_operand
(
reg1
,
0
));
reg1
=
force_reg
(
Pmode
,
force_operand
(
reg1
,
0
));
reg1
=
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
reg1
,
GEN_INT
(
val
)));
reg1
=
force_reg
(
Pmode
,
gen_rtx
_PLUS
(
Pmode
,
reg1
,
GEN_INT
(
val
)));
/* We can now generate a simple scaled indexed address. */
/* We can now generate a simple scaled indexed address. */
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
return
force_reg
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
reg1
,
gen_rtx_PLUS
(
Pmode
,
gen_rtx_MULT
(
Pmode
,
reg1
,
XEXP
(
XEXP
(
idx
,
0
),
1
)),
XEXP
(
XEXP
(
idx
,
0
),
1
)),
base
));
base
));
}
}
...
@@ -897,15 +901,15 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -897,15 +901,15 @@ hppa_legitimize_address (x, oldx, mode)
int
val
=
INTVAL
(
XEXP
(
XEXP
(
idx
,
0
),
1
));
int
val
=
INTVAL
(
XEXP
(
XEXP
(
idx
,
0
),
1
));
rtx
reg1
,
reg2
;
rtx
reg1
,
reg2
;
reg1
=
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
base
,
XEXP
(
idx
,
1
)));
reg1
=
force_reg
(
Pmode
,
gen_rtx
_PLUS
(
Pmode
,
base
,
XEXP
(
idx
,
1
)));
reg2
=
XEXP
(
XEXP
(
idx
,
0
),
0
);
reg2
=
XEXP
(
XEXP
(
idx
,
0
),
0
);
if
(
GET_CODE
(
reg2
)
!=
CONST_INT
)
if
(
GET_CODE
(
reg2
)
!=
CONST_INT
)
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
return
force_reg
(
Pmode
,
gen_rtx
_PLUS
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
gen_rtx_MULT
(
Pmode
,
reg2
,
reg2
,
GEN_INT
(
val
)),
GEN_INT
(
val
)),
reg1
));
reg1
));
}
}
...
@@ -922,13 +926,14 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -922,13 +926,14 @@ hppa_legitimize_address (x, oldx, mode)
if
(
GET_CODE
(
reg2
)
!=
REG
)
if
(
GET_CODE
(
reg2
)
!=
REG
)
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
reg1
=
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
reg1
=
force_reg
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
reg1
,
gen_rtx_PLUS
(
Pmode
,
gen_rtx_MULT
(
Pmode
,
reg1
,
XEXP
(
XEXP
(
idx
,
0
),
1
)),
XEXP
(
XEXP
(
idx
,
0
),
1
)),
reg2
));
reg2
));
/* Add the result to our base register and return. */
/* Add the result to our base register and return. */
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
base
,
reg1
));
return
force_reg
(
Pmode
,
gen_rtx
_PLUS
(
Pmode
,
base
,
reg1
));
}
}
...
@@ -987,9 +992,10 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -987,9 +992,10 @@ hppa_legitimize_address (x, oldx, mode)
if
(
GET_CODE
(
reg2
)
!=
REG
)
if
(
GET_CODE
(
reg2
)
!=
REG
)
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
reg2
=
force_reg
(
Pmode
,
force_operand
(
reg2
,
0
));
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
return
force_reg
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
gen_rtx_PLUS
(
Pmode
,
reg2
,
GEN_INT
(
val
)),
gen_rtx_MULT
(
Pmode
,
reg2
,
GEN_INT
(
val
)),
reg1
));
reg1
));
}
}
else
if
((
mode
==
DFmode
||
mode
==
SFmode
)
else
if
((
mode
==
DFmode
||
mode
==
SFmode
)
...
@@ -1006,12 +1012,13 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -1006,12 +1012,13 @@ hppa_legitimize_address (x, oldx, mode)
regx2
=
XEXP
(
XEXP
(
x
,
0
),
0
);
regx2
=
XEXP
(
XEXP
(
x
,
0
),
0
);
if
(
GET_CODE
(
regx2
)
!=
REG
)
if
(
GET_CODE
(
regx2
)
!=
REG
)
regx2
=
force_reg
(
Pmode
,
force_operand
(
regx2
,
0
));
regx2
=
force_reg
(
Pmode
,
force_operand
(
regx2
,
0
));
regx2
=
force_reg
(
Pmode
,
gen_rtx
(
GET_CODE
(
y
),
Pmode
,
regx2
=
force_reg
(
Pmode
,
gen_rtx
_fmt_ee
(
GET_CODE
(
y
),
Pmode
,
regx2
,
regx1
));
regx2
,
regx1
));
return
force_reg
(
Pmode
,
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
gen_rtx_PLUS
(
Pmode
,
gen_rtx
(
MULT
,
Pmode
,
regx2
,
gen_rtx_MULT
(
Pmode
,
regx2
,
XEXP
(
XEXP
(
x
,
0
),
1
)),
XEXP
(
XEXP
(
x
,
0
),
1
)),
force_reg
(
Pmode
,
XEXP
(
y
,
0
))));
force_reg
(
Pmode
,
XEXP
(
y
,
0
))));
}
}
else
if
(
GET_CODE
(
XEXP
(
y
,
1
))
==
CONST_INT
else
if
(
GET_CODE
(
XEXP
(
y
,
1
))
==
CONST_INT
...
@@ -1030,8 +1037,9 @@ hppa_legitimize_address (x, oldx, mode)
...
@@ -1030,8 +1037,9 @@ hppa_legitimize_address (x, oldx, mode)
regy1
=
force_reg
(
Pmode
,
force_operand
(
XEXP
(
y
,
0
),
0
));
regy1
=
force_reg
(
Pmode
,
force_operand
(
XEXP
(
y
,
0
),
0
));
regy2
=
force_reg
(
Pmode
,
force_operand
(
XEXP
(
y
,
1
),
0
));
regy2
=
force_reg
(
Pmode
,
force_operand
(
XEXP
(
y
,
1
),
0
));
regx1
=
force_reg
(
Pmode
,
regx1
=
force_reg
(
Pmode
,
gen_rtx
(
GET_CODE
(
y
),
Pmode
,
regx1
,
regy2
));
gen_rtx_fmt_ee
(
GET_CODE
(
y
),
Pmode
,
return
force_reg
(
Pmode
,
gen_rtx
(
PLUS
,
Pmode
,
regx1
,
regy1
));
regx1
,
regy2
));
return
force_reg
(
Pmode
,
gen_rtx_PLUS
(
Pmode
,
regx1
,
regy1
));
}
}
}
}
}
}
...
@@ -1100,11 +1108,11 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1100,11 +1108,11 @@ emit_move_sequence (operands, mode, scratch_reg)
if
(
reload_in_progress
&&
GET_CODE
(
operand0
)
==
MEM
if
(
reload_in_progress
&&
GET_CODE
(
operand0
)
==
MEM
&&
((
tem
=
find_replacement
(
&
XEXP
(
operand0
,
0
)))
&&
((
tem
=
find_replacement
(
&
XEXP
(
operand0
,
0
)))
!=
XEXP
(
operand0
,
0
)))
!=
XEXP
(
operand0
,
0
)))
operand0
=
gen_rtx
(
MEM
,
GET_MODE
(
operand0
),
tem
);
operand0
=
gen_rtx
_MEM
(
GET_MODE
(
operand0
),
tem
);
if
(
reload_in_progress
&&
GET_CODE
(
operand1
)
==
MEM
if
(
reload_in_progress
&&
GET_CODE
(
operand1
)
==
MEM
&&
((
tem
=
find_replacement
(
&
XEXP
(
operand1
,
0
)))
&&
((
tem
=
find_replacement
(
&
XEXP
(
operand1
,
0
)))
!=
XEXP
(
operand1
,
0
)))
!=
XEXP
(
operand1
,
0
)))
operand1
=
gen_rtx
(
MEM
,
GET_MODE
(
operand1
),
tem
);
operand1
=
gen_rtx
_MEM
(
GET_MODE
(
operand1
),
tem
);
/* Handle secondary reloads for loads/stores of FP registers from
/* Handle secondary reloads for loads/stores of FP registers from
REG+D addresses where D does not fit in 5 bits, including
REG+D addresses where D does not fit in 5 bits, including
...
@@ -1120,21 +1128,21 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1120,21 +1128,21 @@ emit_move_sequence (operands, mode, scratch_reg)
if
(
GET_CODE
(
operand1
)
==
SUBREG
)
if
(
GET_CODE
(
operand1
)
==
SUBREG
)
operand1
=
XEXP
(
operand1
,
0
);
operand1
=
XEXP
(
operand1
,
0
);
scratch_reg
=
gen_rtx
(
REG
,
SImode
,
REGNO
(
scratch_reg
));
scratch_reg
=
gen_rtx
_REG
(
SImode
,
REGNO
(
scratch_reg
));
/* D might not fit in 14 bits either; for such cases load D into
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
scratch reg. */
if
(
!
memory_address_p
(
SImode
,
XEXP
(
operand1
,
0
)))
if
(
!
memory_address_p
(
SImode
,
XEXP
(
operand1
,
0
)))
{
{
emit_move_insn
(
scratch_reg
,
XEXP
(
XEXP
(
operand1
,
0
),
1
));
emit_move_insn
(
scratch_reg
,
XEXP
(
XEXP
(
operand1
,
0
),
1
));
emit_move_insn
(
scratch_reg
,
gen_rtx
(
GET_CODE
(
XEXP
(
operand1
,
0
)),
emit_move_insn
(
scratch_reg
,
gen_rtx
_fmt_ee
(
GET_CODE
(
XEXP
(
operand1
,
0
)),
SImode
,
SImode
,
XEXP
(
XEXP
(
operand1
,
0
),
0
),
XEXP
(
XEXP
(
operand1
,
0
),
0
),
scratch_reg
));
scratch_reg
));
}
}
else
else
emit_move_insn
(
scratch_reg
,
XEXP
(
operand1
,
0
));
emit_move_insn
(
scratch_reg
,
XEXP
(
operand1
,
0
));
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
operand0
,
gen_rtx
(
MEM
,
mode
,
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
operand0
,
gen_rtx_MEM
(
mode
,
scratch_reg
)));
scratch_reg
)));
return
1
;
return
1
;
}
}
...
@@ -1149,20 +1157,22 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1149,20 +1157,22 @@ emit_move_sequence (operands, mode, scratch_reg)
if
(
GET_CODE
(
operand0
)
==
SUBREG
)
if
(
GET_CODE
(
operand0
)
==
SUBREG
)
operand0
=
XEXP
(
operand0
,
0
);
operand0
=
XEXP
(
operand0
,
0
);
scratch_reg
=
gen_rtx
(
REG
,
SImode
,
REGNO
(
scratch_reg
));
scratch_reg
=
gen_rtx
_REG
(
SImode
,
REGNO
(
scratch_reg
));
/* D might not fit in 14 bits either; for such cases load D into
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
scratch reg. */
if
(
!
memory_address_p
(
SImode
,
XEXP
(
operand0
,
0
)))
if
(
!
memory_address_p
(
SImode
,
XEXP
(
operand0
,
0
)))
{
{
emit_move_insn
(
scratch_reg
,
XEXP
(
XEXP
(
operand0
,
0
),
1
));
emit_move_insn
(
scratch_reg
,
XEXP
(
XEXP
(
operand0
,
0
),
1
));
emit_move_insn
(
scratch_reg
,
gen_rtx
(
GET_CODE
(
XEXP
(
operand0
,
0
)),
emit_move_insn
(
scratch_reg
,
gen_rtx_fmt_ee
(
GET_CODE
(
XEXP
(
operand0
,
0
)),
SImode
,
SImode
,
XEXP
(
XEXP
(
operand0
,
0
),
0
),
XEXP
(
XEXP
(
operand0
,
0
),
0
),
scratch_reg
));
scratch_reg
));
}
}
else
else
emit_move_insn
(
scratch_reg
,
XEXP
(
operand0
,
0
));
emit_move_insn
(
scratch_reg
,
XEXP
(
operand0
,
0
));
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
gen_rtx
(
MEM
,
mode
,
scratch_reg
),
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
gen_rtx_MEM
(
mode
,
scratch_reg
),
operand1
));
operand1
));
return
1
;
return
1
;
}
}
...
@@ -1188,8 +1198,7 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1188,8 +1198,7 @@ emit_move_sequence (operands, mode, scratch_reg)
emit_move_sequence
(
xoperands
,
Pmode
,
0
);
emit_move_sequence
(
xoperands
,
Pmode
,
0
);
/* Now load the destination register. */
/* Now load the destination register. */
emit_insn
(
gen_rtx
(
SET
,
mode
,
operand0
,
emit_insn
(
gen_rtx_SET
(
mode
,
operand0
,
gen_rtx_MEM
(
mode
,
scratch_reg
)));
gen_rtx
(
MEM
,
mode
,
scratch_reg
)));
return
1
;
return
1
;
}
}
/* Handle secondary reloads for SAR. These occur when trying to load
/* Handle secondary reloads for SAR. These occur when trying to load
...
@@ -1208,11 +1217,13 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1208,11 +1217,13 @@ emit_move_sequence (operands, mode, scratch_reg)
&&
!
memory_address_p
(
SImode
,
XEXP
(
operand1
,
0
)))
&&
!
memory_address_p
(
SImode
,
XEXP
(
operand1
,
0
)))
{
{
emit_move_insn
(
scratch_reg
,
XEXP
(
XEXP
(
operand1
,
0
),
1
));
emit_move_insn
(
scratch_reg
,
XEXP
(
XEXP
(
operand1
,
0
),
1
));
emit_move_insn
(
scratch_reg
,
gen_rtx
(
GET_CODE
(
XEXP
(
operand1
,
0
)),
emit_move_insn
(
scratch_reg
,
gen_rtx_fmt_ee
(
GET_CODE
(
XEXP
(
operand1
,
0
)),
SImode
,
SImode
,
XEXP
(
XEXP
(
operand1
,
0
),
0
),
XEXP
(
XEXP
(
operand1
,
0
),
0
),
scratch_reg
));
scratch_reg
));
emit_move_insn
(
scratch_reg
,
gen_rtx
(
MEM
,
GET_MODE
(
operand1
),
emit_move_insn
(
scratch_reg
,
gen_rtx
_MEM
(
GET_MODE
(
operand1
),
scratch_reg
));
scratch_reg
));
}
}
else
else
...
@@ -1232,7 +1243,7 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1232,7 +1243,7 @@ emit_move_sequence (operands, mode, scratch_reg)
||
GET_CODE
(
operand1
)
==
MEM
)
||
GET_CODE
(
operand1
)
==
MEM
)
{
{
/* Run this case quickly. */
/* Run this case quickly. */
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
operand0
,
operand1
));
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
operand0
,
operand1
));
return
1
;
return
1
;
}
}
}
}
...
@@ -1243,14 +1254,14 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1243,14 +1254,14 @@ emit_move_sequence (operands, mode, scratch_reg)
{
{
rtx
temp
=
gen_reg_rtx
(
DFmode
);
rtx
temp
=
gen_reg_rtx
(
DFmode
);
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
temp
,
operand1
));
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
temp
,
operand1
));
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
operand0
,
temp
));
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
operand0
,
temp
));
return
1
;
return
1
;
}
}
if
(
register_operand
(
operand1
,
mode
)
||
operand1
==
CONST0_RTX
(
mode
))
if
(
register_operand
(
operand1
,
mode
)
||
operand1
==
CONST0_RTX
(
mode
))
{
{
/* Run this case quickly. */
/* Run this case quickly. */
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
operand0
,
operand1
));
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
operand0
,
operand1
));
return
1
;
return
1
;
}
}
if
(
!
(
reload_in_progress
||
reload_completed
))
if
(
!
(
reload_in_progress
||
reload_completed
))
...
@@ -1329,7 +1340,7 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1329,7 +1340,7 @@ emit_move_sequence (operands, mode, scratch_reg)
/* Now load from the memory location into our destination
/* Now load from the memory location into our destination
register. */
register. */
operands
[
1
]
=
gen_rtx
(
MEM
,
Pmode
,
operands
[
0
]);
operands
[
1
]
=
gen_rtx
_MEM
(
Pmode
,
operands
[
0
]);
emit_move_sequence
(
operands
,
mode
,
scratch_reg
);
emit_move_sequence
(
operands
,
mode
,
scratch_reg
);
/* And add back in the constant part. */
/* And add back in the constant part. */
...
@@ -1366,7 +1377,7 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1366,7 +1377,7 @@ emit_move_sequence (operands, mode, scratch_reg)
else
else
{
{
operands
[
1
]
=
legitimize_pic_address
(
operand1
,
mode
,
temp
);
operands
[
1
]
=
legitimize_pic_address
(
operand1
,
mode
,
temp
);
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
operand0
,
operands
[
1
]));
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
operand0
,
operands
[
1
]));
}
}
}
}
/* On the HPPA, references to data space are supposed to use dp,
/* On the HPPA, references to data space are supposed to use dp,
...
@@ -1391,15 +1402,14 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1391,15 +1402,14 @@ emit_move_sequence (operands, mode, scratch_reg)
if
(
REGNO
(
temp
)
>=
FIRST_PSEUDO_REGISTER
)
if
(
REGNO
(
temp
)
>=
FIRST_PSEUDO_REGISTER
)
REGNO_POINTER_FLAG
(
REGNO
(
temp
))
=
1
;
REGNO_POINTER_FLAG
(
REGNO
(
temp
))
=
1
;
if
(
ishighonly
)
if
(
ishighonly
)
set
=
gen_rtx
(
SET
,
mode
,
operand0
,
temp
);
set
=
gen_rtx
_SET
(
mode
,
operand0
,
temp
);
else
else
set
=
gen_rtx
(
SET
,
VOIDmode
,
set
=
gen_rtx_SET
(
VOIDmode
,
operand0
,
operand0
,
gen_rtx_LO_SUM
(
mode
,
temp
,
operand1
));
gen_rtx
(
LO_SUM
,
mode
,
temp
,
operand1
));
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
temp
,
temp
,
gen_rtx
(
HIGH
,
mode
,
operand1
)));
gen_rtx_HIGH
(
mode
,
operand1
)));
emit_insn
(
set
);
emit_insn
(
set
);
}
}
...
@@ -1415,9 +1425,9 @@ emit_move_sequence (operands, mode, scratch_reg)
...
@@ -1415,9 +1425,9 @@ emit_move_sequence (operands, mode, scratch_reg)
else
else
temp
=
gen_reg_rtx
(
mode
);
temp
=
gen_reg_rtx
(
mode
);
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
temp
,
emit_insn
(
gen_rtx
_SET
(
VOIDmode
,
temp
,
gen_rtx
(
HIGH
,
mode
,
operand1
)));
gen_rtx_HIGH
(
mode
,
operand1
)));
operands
[
1
]
=
gen_rtx
(
LO_SUM
,
mode
,
temp
,
operand1
);
operands
[
1
]
=
gen_rtx
_LO_SUM
(
mode
,
temp
,
operand1
);
}
}
}
}
/* Now have insn-emit do whatever it normally does. */
/* Now have insn-emit do whatever it normally does. */
...
@@ -1629,7 +1639,7 @@ output_move_double (operands)
...
@@ -1629,7 +1639,7 @@ output_move_double (operands)
rtx
addr
=
XEXP
(
operands
[
0
],
0
);
rtx
addr
=
XEXP
(
operands
[
0
],
0
);
if
(
GET_CODE
(
addr
)
==
POST_INC
||
GET_CODE
(
addr
)
==
POST_DEC
)
if
(
GET_CODE
(
addr
)
==
POST_INC
||
GET_CODE
(
addr
)
==
POST_DEC
)
{
{
rtx
high_reg
=
gen_rtx
(
SUBREG
,
SImode
,
operands
[
1
],
0
);
rtx
high_reg
=
gen_rtx
_SUBREG
(
SImode
,
operands
[
1
],
0
);
operands
[
0
]
=
XEXP
(
addr
,
0
);
operands
[
0
]
=
XEXP
(
addr
,
0
);
if
(
GET_CODE
(
operands
[
1
])
!=
REG
||
GET_CODE
(
operands
[
0
])
!=
REG
)
if
(
GET_CODE
(
operands
[
1
])
!=
REG
||
GET_CODE
(
operands
[
0
])
!=
REG
)
...
@@ -1649,7 +1659,7 @@ output_move_double (operands)
...
@@ -1649,7 +1659,7 @@ output_move_double (operands)
}
}
else
if
(
GET_CODE
(
addr
)
==
PRE_INC
||
GET_CODE
(
addr
)
==
PRE_DEC
)
else
if
(
GET_CODE
(
addr
)
==
PRE_INC
||
GET_CODE
(
addr
)
==
PRE_DEC
)
{
{
rtx
high_reg
=
gen_rtx
(
SUBREG
,
SImode
,
operands
[
1
],
0
);
rtx
high_reg
=
gen_rtx
_SUBREG
(
SImode
,
operands
[
1
],
0
);
operands
[
0
]
=
XEXP
(
addr
,
0
);
operands
[
0
]
=
XEXP
(
addr
,
0
);
if
(
GET_CODE
(
operands
[
1
])
!=
REG
||
GET_CODE
(
operands
[
0
])
!=
REG
)
if
(
GET_CODE
(
operands
[
1
])
!=
REG
||
GET_CODE
(
operands
[
0
])
!=
REG
)
...
@@ -1676,7 +1686,7 @@ output_move_double (operands)
...
@@ -1676,7 +1686,7 @@ output_move_double (operands)
rtx
addr
=
XEXP
(
operands
[
1
],
0
);
rtx
addr
=
XEXP
(
operands
[
1
],
0
);
if
(
GET_CODE
(
addr
)
==
POST_INC
||
GET_CODE
(
addr
)
==
POST_DEC
)
if
(
GET_CODE
(
addr
)
==
POST_INC
||
GET_CODE
(
addr
)
==
POST_DEC
)
{
{
rtx
high_reg
=
gen_rtx
(
SUBREG
,
SImode
,
operands
[
0
],
0
);
rtx
high_reg
=
gen_rtx
_SUBREG
(
SImode
,
operands
[
0
],
0
);
operands
[
1
]
=
XEXP
(
addr
,
0
);
operands
[
1
]
=
XEXP
(
addr
,
0
);
if
(
GET_CODE
(
operands
[
0
])
!=
REG
||
GET_CODE
(
operands
[
1
])
!=
REG
)
if
(
GET_CODE
(
operands
[
0
])
!=
REG
||
GET_CODE
(
operands
[
1
])
!=
REG
)
...
@@ -1703,7 +1713,7 @@ output_move_double (operands)
...
@@ -1703,7 +1713,7 @@ output_move_double (operands)
}
}
else
if
(
GET_CODE
(
addr
)
==
PRE_INC
||
GET_CODE
(
addr
)
==
PRE_DEC
)
else
if
(
GET_CODE
(
addr
)
==
PRE_INC
||
GET_CODE
(
addr
)
==
PRE_DEC
)
{
{
rtx
high_reg
=
gen_rtx
(
SUBREG
,
SImode
,
operands
[
0
],
0
);
rtx
high_reg
=
gen_rtx
_SUBREG
(
SImode
,
operands
[
0
],
0
);
operands
[
1
]
=
XEXP
(
addr
,
0
);
operands
[
1
]
=
XEXP
(
addr
,
0
);
if
(
GET_CODE
(
operands
[
0
])
!=
REG
||
GET_CODE
(
operands
[
1
])
!=
REG
)
if
(
GET_CODE
(
operands
[
0
])
!=
REG
||
GET_CODE
(
operands
[
1
])
!=
REG
)
...
@@ -1731,7 +1741,7 @@ output_move_double (operands)
...
@@ -1731,7 +1741,7 @@ output_move_double (operands)
else
if
(
GET_CODE
(
addr
)
==
PLUS
else
if
(
GET_CODE
(
addr
)
==
PLUS
&&
GET_CODE
(
XEXP
(
addr
,
0
))
==
MULT
)
&&
GET_CODE
(
XEXP
(
addr
,
0
))
==
MULT
)
{
{
rtx
high_reg
=
gen_rtx
(
SUBREG
,
SImode
,
operands
[
0
],
0
);
rtx
high_reg
=
gen_rtx
_SUBREG
(
SImode
,
operands
[
0
],
0
);
if
(
!
reg_overlap_mentioned_p
(
high_reg
,
addr
))
if
(
!
reg_overlap_mentioned_p
(
high_reg
,
addr
))
{
{
...
@@ -1776,14 +1786,14 @@ output_move_double (operands)
...
@@ -1776,14 +1786,14 @@ output_move_double (operands)
operands in OPERANDS to be suitable for the low-numbered word. */
operands in OPERANDS to be suitable for the low-numbered word. */
if
(
optype0
==
REGOP
)
if
(
optype0
==
REGOP
)
latehalf
[
0
]
=
gen_rtx
(
REG
,
SImode
,
REGNO
(
operands
[
0
])
+
1
);
latehalf
[
0
]
=
gen_rtx
_REG
(
SImode
,
REGNO
(
operands
[
0
])
+
1
);
else
if
(
optype0
==
OFFSOP
)
else
if
(
optype0
==
OFFSOP
)
latehalf
[
0
]
=
adj_offsettable_operand
(
operands
[
0
],
4
);
latehalf
[
0
]
=
adj_offsettable_operand
(
operands
[
0
],
4
);
else
else
latehalf
[
0
]
=
operands
[
0
];
latehalf
[
0
]
=
operands
[
0
];
if
(
optype1
==
REGOP
)
if
(
optype1
==
REGOP
)
latehalf
[
1
]
=
gen_rtx
(
REG
,
SImode
,
REGNO
(
operands
[
1
])
+
1
);
latehalf
[
1
]
=
gen_rtx
_REG
(
SImode
,
REGNO
(
operands
[
1
])
+
1
);
else
if
(
optype1
==
OFFSOP
)
else
if
(
optype1
==
OFFSOP
)
latehalf
[
1
]
=
adj_offsettable_operand
(
operands
[
1
],
4
);
latehalf
[
1
]
=
adj_offsettable_operand
(
operands
[
1
],
4
);
else
if
(
optype1
==
CNSTOP
)
else
if
(
optype1
==
CNSTOP
)
...
@@ -1874,7 +1884,7 @@ output_fp_move_double (operands)
...
@@ -1874,7 +1884,7 @@ output_fp_move_double (operands)
if
(
GET_CODE
(
operands
[
0
])
==
REG
)
if
(
GET_CODE
(
operands
[
0
])
==
REG
)
{
{
rtx
xoperands
[
2
];
rtx
xoperands
[
2
];
xoperands
[
1
]
=
gen_rtx
(
REG
,
SImode
,
REGNO
(
operands
[
0
])
+
1
);
xoperands
[
1
]
=
gen_rtx
_REG
(
SImode
,
REGNO
(
operands
[
0
])
+
1
);
xoperands
[
0
]
=
operands
[
0
];
xoperands
[
0
]
=
operands
[
0
];
output_asm_insn
(
"copy %%r0,%0
\n\t
copy %%r0,%1"
,
xoperands
);
output_asm_insn
(
"copy %%r0,%0
\n\t
copy %%r0,%1"
,
xoperands
);
}
}
...
@@ -2420,22 +2430,22 @@ store_reg (reg, disp, base)
...
@@ -2420,22 +2430,22 @@ store_reg (reg, disp, base)
{
{
if
(
VAL_14_BITS_P
(
disp
))
if
(
VAL_14_BITS_P
(
disp
))
{
{
emit_move_insn
(
gen_rtx
(
MEM
,
SImode
,
emit_move_insn
(
gen_rtx
_MEM
(
SImode
,
gen_rtx
(
PLUS
,
SImode
,
gen_rtx_PLUS
(
SImode
,
gen_rtx
(
REG
,
SImode
,
base
),
gen_rtx_REG
(
SImode
,
base
),
GEN_INT
(
disp
))),
GEN_INT
(
disp
))),
gen_rtx
(
REG
,
SImode
,
reg
));
gen_rtx_REG
(
SImode
,
reg
));
}
}
else
else
{
{
emit_insn
(
gen_add_high_const
(
gen_rtx
(
REG
,
SImode
,
1
),
emit_insn
(
gen_add_high_const
(
gen_rtx
_REG
(
SImode
,
1
),
gen_rtx
(
REG
,
SImode
,
base
),
gen_rtx
_REG
(
SImode
,
base
),
GEN_INT
(
disp
)));
GEN_INT
(
disp
)));
emit_move_insn
(
gen_rtx
(
MEM
,
SImode
,
emit_move_insn
(
gen_rtx
_MEM
(
SImode
,
gen_rtx
(
LO_SUM
,
SImode
,
gen_rtx_LO_SUM
(
SImode
,
gen_rtx
(
REG
,
SImode
,
1
),
gen_rtx_REG
(
SImode
,
1
),
GEN_INT
(
disp
))),
GEN_INT
(
disp
))),
gen_rtx
(
REG
,
SImode
,
reg
));
gen_rtx
_REG
(
SImode
,
reg
));
}
}
}
}
...
@@ -2450,21 +2460,21 @@ load_reg (reg, disp, base)
...
@@ -2450,21 +2460,21 @@ load_reg (reg, disp, base)
{
{
if
(
VAL_14_BITS_P
(
disp
))
if
(
VAL_14_BITS_P
(
disp
))
{
{
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
reg
),
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
reg
),
gen_rtx
(
MEM
,
SImode
,
gen_rtx
_MEM
(
SImode
,
gen_rtx
(
PLUS
,
SImode
,
gen_rtx_PLUS
(
SImode
,
gen_rtx
(
REG
,
SImode
,
base
),
gen_rtx_REG
(
SImode
,
base
),
GEN_INT
(
disp
))));
GEN_INT
(
disp
))));
}
}
else
else
{
{
emit_insn
(
gen_add_high_const
(
gen_rtx
(
REG
,
SImode
,
1
),
emit_insn
(
gen_add_high_const
(
gen_rtx
_REG
(
SImode
,
1
),
gen_rtx
(
REG
,
SImode
,
base
),
gen_rtx
_REG
(
SImode
,
base
),
GEN_INT
(
disp
)));
GEN_INT
(
disp
)));
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
reg
),
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
reg
),
gen_rtx
(
MEM
,
SImode
,
gen_rtx
_MEM
(
SImode
,
gen_rtx
(
LO_SUM
,
SImode
,
gen_rtx_LO_SUM
(
SImode
,
gen_rtx
(
REG
,
SImode
,
1
),
gen_rtx_REG
(
SImode
,
1
),
GEN_INT
(
disp
))));
GEN_INT
(
disp
))));
}
}
}
}
...
@@ -2480,19 +2490,19 @@ set_reg_plus_d(reg, base, disp)
...
@@ -2480,19 +2490,19 @@ set_reg_plus_d(reg, base, disp)
{
{
if
(
VAL_14_BITS_P
(
disp
))
if
(
VAL_14_BITS_P
(
disp
))
{
{
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
reg
),
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
reg
),
gen_rtx
(
PLUS
,
SImode
,
gen_rtx
_PLUS
(
SImode
,
gen_rtx
(
REG
,
SImode
,
base
),
gen_rtx_REG
(
SImode
,
base
),
GEN_INT
(
disp
)));
GEN_INT
(
disp
)));
}
}
else
else
{
{
emit_insn
(
gen_add_high_const
(
gen_rtx
(
REG
,
SImode
,
1
),
emit_insn
(
gen_add_high_const
(
gen_rtx
_REG
(
SImode
,
1
),
gen_rtx
(
REG
,
SImode
,
base
),
gen_rtx
_REG
(
SImode
,
base
),
GEN_INT
(
disp
)));
GEN_INT
(
disp
)));
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
reg
),
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
reg
),
gen_rtx
(
LO_SUM
,
SImode
,
gen_rtx
_LO_SUM
(
SImode
,
gen_rtx
(
REG
,
SImode
,
1
),
gen_rtx_REG
(
SImode
,
1
),
GEN_INT
(
disp
)));
GEN_INT
(
disp
)));
}
}
}
}
...
@@ -2635,7 +2645,7 @@ hppa_expand_prologue()
...
@@ -2635,7 +2645,7 @@ hppa_expand_prologue()
actual_fsize
=
compute_frame_size
(
size
,
&
save_fregs
);
actual_fsize
=
compute_frame_size
(
size
,
&
save_fregs
);
/* Compute a few things we will use often. */
/* Compute a few things we will use often. */
tmpreg
=
gen_rtx
(
REG
,
SImode
,
1
);
tmpreg
=
gen_rtx
_REG
(
SImode
,
1
);
size_rtx
=
GEN_INT
(
actual_fsize
);
size_rtx
=
GEN_INT
(
actual_fsize
);
/* Handle out of line prologues and epilogues. */
/* Handle out of line prologues and epilogues. */
...
@@ -2698,16 +2708,16 @@ hppa_expand_prologue()
...
@@ -2698,16 +2708,16 @@ hppa_expand_prologue()
if
(
inline_insn_count
>
outline_insn_count
)
if
(
inline_insn_count
>
outline_insn_count
)
{
{
/* Put the local_fisze into %r19. */
/* Put the local_fisze into %r19. */
operands
[
0
]
=
gen_rtx
(
REG
,
SImode
,
19
);
operands
[
0
]
=
gen_rtx
_REG
(
SImode
,
19
);
operands
[
1
]
=
GEN_INT
(
local_fsize
);
operands
[
1
]
=
GEN_INT
(
local_fsize
);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
/* Put the stack size into %r21. */
/* Put the stack size into %r21. */
operands
[
0
]
=
gen_rtx
(
REG
,
SImode
,
21
);
operands
[
0
]
=
gen_rtx
_REG
(
SImode
,
21
);
operands
[
1
]
=
size_rtx
;
operands
[
1
]
=
size_rtx
;
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
operands
[
0
]
=
gen_rtx
(
REG
,
SImode
,
22
);
operands
[
0
]
=
gen_rtx
_REG
(
SImode
,
22
);
operands
[
1
]
=
GEN_INT
(
saves
);
operands
[
1
]
=
GEN_INT
(
saves
);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
...
@@ -2814,8 +2824,7 @@ hppa_expand_prologue()
...
@@ -2814,8 +2824,7 @@ hppa_expand_prologue()
place to get the expected results. sprintf here is just to
place to get the expected results. sprintf here is just to
put something in the name. */
put something in the name. */
sprintf
(
hp_profile_label_name
,
"LP$%04d"
,
-
1
);
sprintf
(
hp_profile_label_name
,
"LP$%04d"
,
-
1
);
hp_profile_label_rtx
=
gen_rtx
(
SYMBOL_REF
,
SImode
,
hp_profile_label_rtx
=
gen_rtx_SYMBOL_REF
(
SImode
,
hp_profile_label_name
);
hp_profile_label_name
);
if
(
current_function_returns_struct
)
if
(
current_function_returns_struct
)
store_reg
(
STRUCT_VALUE_REGNUM
,
-
12
-
offsetadj
,
basereg
);
store_reg
(
STRUCT_VALUE_REGNUM
,
-
12
-
offsetadj
,
basereg
);
...
@@ -2827,10 +2836,10 @@ hppa_expand_prologue()
...
@@ -2827,10 +2836,10 @@ hppa_expand_prologue()
pc_offset
+=
VAL_14_BITS_P
(
arg_offset
)
?
4
:
8
;
pc_offset
+=
VAL_14_BITS_P
(
arg_offset
)
?
4
:
8
;
}
}
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
26
),
gen_rtx
(
REG
,
SImode
,
2
));
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
26
),
gen_rtx_REG
(
SImode
,
2
));
emit_move_insn
(
tmpreg
,
gen_rtx
(
HIGH
,
SImode
,
hp_profile_label_rtx
));
emit_move_insn
(
tmpreg
,
gen_rtx
_HIGH
(
SImode
,
hp_profile_label_rtx
));
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
24
),
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
24
),
gen_rtx
(
LO_SUM
,
SImode
,
tmpreg
,
hp_profile_label_rtx
));
gen_rtx
_LO_SUM
(
SImode
,
tmpreg
,
hp_profile_label_rtx
));
/* %r25 is set from within the output pattern. */
/* %r25 is set from within the output pattern. */
emit_insn
(
gen_call_profiler
(
GEN_INT
(
-
pc_offset
-
20
)));
emit_insn
(
gen_call_profiler
(
GEN_INT
(
-
pc_offset
-
20
)));
...
@@ -2872,7 +2881,7 @@ hppa_expand_prologue()
...
@@ -2872,7 +2881,7 @@ hppa_expand_prologue()
{
{
merge_sp_adjust_with_store
=
0
;
merge_sp_adjust_with_store
=
0
;
emit_insn
(
gen_post_stwm
(
stack_pointer_rtx
,
emit_insn
(
gen_post_stwm
(
stack_pointer_rtx
,
gen_rtx
(
REG
,
SImode
,
i
),
gen_rtx
_REG
(
SImode
,
i
),
GEN_INT
(
-
offset
)));
GEN_INT
(
-
offset
)));
}
}
else
else
...
@@ -2907,9 +2916,9 @@ hppa_expand_prologue()
...
@@ -2907,9 +2916,9 @@ hppa_expand_prologue()
{
{
if
(
regs_ever_live
[
i
]
||
regs_ever_live
[
i
+
1
])
if
(
regs_ever_live
[
i
]
||
regs_ever_live
[
i
+
1
])
{
{
emit_move_insn
(
gen_rtx
(
MEM
,
DFmode
,
emit_move_insn
(
gen_rtx
_MEM
(
DFmode
,
gen_rtx
(
POST_INC
,
DFmode
,
tmpreg
)),
gen_rtx_POST_INC
(
DFmode
,
tmpreg
)),
gen_rtx
(
REG
,
DFmode
,
i
));
gen_rtx
_REG
(
DFmode
,
i
));
fr_saved
++
;
fr_saved
++
;
}
}
}
}
...
@@ -2933,8 +2942,8 @@ hppa_expand_prologue()
...
@@ -2933,8 +2942,8 @@ hppa_expand_prologue()
Avoid this if the callee saved register wasn't used (these are
Avoid this if the callee saved register wasn't used (these are
leaf functions). */
leaf functions). */
if
(
flag_pic
&&
regs_ever_live
[
PIC_OFFSET_TABLE_REGNUM_SAVED
])
if
(
flag_pic
&&
regs_ever_live
[
PIC_OFFSET_TABLE_REGNUM_SAVED
])
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
PIC_OFFSET_TABLE_REGNUM_SAVED
),
emit_move_insn
(
gen_rtx
_REG
(
SImode
,
PIC_OFFSET_TABLE_REGNUM_SAVED
),
gen_rtx
(
REG
,
SImode
,
PIC_OFFSET_TABLE_REGNUM
));
gen_rtx
_REG
(
SImode
,
PIC_OFFSET_TABLE_REGNUM
));
}
}
...
@@ -3006,16 +3015,16 @@ hppa_expand_epilogue ()
...
@@ -3006,16 +3015,16 @@ hppa_expand_epilogue ()
emit_insn
(
gen_blockage
());
emit_insn
(
gen_blockage
());
/* Put the local_fisze into %r19. */
/* Put the local_fisze into %r19. */
operands
[
0
]
=
gen_rtx
(
REG
,
SImode
,
19
);
operands
[
0
]
=
gen_rtx
_REG
(
SImode
,
19
);
operands
[
1
]
=
GEN_INT
(
local_fsize
);
operands
[
1
]
=
GEN_INT
(
local_fsize
);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
/* Put the stack size into %r21. */
/* Put the stack size into %r21. */
operands
[
0
]
=
gen_rtx
(
REG
,
SImode
,
21
);
operands
[
0
]
=
gen_rtx
_REG
(
SImode
,
21
);
operands
[
1
]
=
GEN_INT
(
actual_fsize
);
operands
[
1
]
=
GEN_INT
(
actual_fsize
);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
operands
[
0
]
=
gen_rtx
(
REG
,
SImode
,
22
);
operands
[
0
]
=
gen_rtx
_REG
(
SImode
,
22
);
operands
[
1
]
=
GEN_INT
(
saves
);
operands
[
1
]
=
GEN_INT
(
saves
);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
emit_move_insn
(
operands
[
0
],
operands
[
1
]);
...
@@ -3025,7 +3034,7 @@ hppa_expand_epilogue ()
...
@@ -3025,7 +3034,7 @@ hppa_expand_epilogue ()
}
}
/* We will use this often. */
/* We will use this often. */
tmpreg
=
gen_rtx
(
REG
,
SImode
,
1
);
tmpreg
=
gen_rtx
_REG
(
SImode
,
1
);
/* Try to restore RP early to avoid load/use interlocks when
/* Try to restore RP early to avoid load/use interlocks when
RP gets used in the return (bv) instruction. This appears to still
RP gets used in the return (bv) instruction. This appears to still
...
@@ -3087,9 +3096,9 @@ hppa_expand_epilogue ()
...
@@ -3087,9 +3096,9 @@ hppa_expand_epilogue ()
{
{
if
(
regs_ever_live
[
i
]
||
regs_ever_live
[
i
+
1
])
if
(
regs_ever_live
[
i
]
||
regs_ever_live
[
i
+
1
])
{
{
emit_move_insn
(
gen_rtx
(
REG
,
DFmode
,
i
),
emit_move_insn
(
gen_rtx
_REG
(
DFmode
,
i
),
gen_rtx
(
MEM
,
DFmode
,
gen_rtx
_MEM
(
DFmode
,
gen_rtx
(
POST_INC
,
DFmode
,
tmpreg
)));
gen_rtx_POST_INC
(
DFmode
,
tmpreg
)));
}
}
}
}
}
}
...
@@ -3131,8 +3140,7 @@ hppa_expand_epilogue ()
...
@@ -3131,8 +3140,7 @@ hppa_expand_epilogue ()
}
}
/* If we were deferring a callee register restore, do it now. */
/* If we were deferring a callee register restore, do it now. */
else
if
(
!
frame_pointer_needed
&&
merge_sp_adjust_with_load
)
else
if
(
!
frame_pointer_needed
&&
merge_sp_adjust_with_load
)
emit_insn
(
gen_pre_ldwm
(
gen_rtx
(
REG
,
SImode
,
emit_insn
(
gen_pre_ldwm
(
gen_rtx_REG
(
SImode
,
merge_sp_adjust_with_load
),
merge_sp_adjust_with_load
),
stack_pointer_rtx
,
stack_pointer_rtx
,
GEN_INT
(
-
actual_fsize
)));
GEN_INT
(
-
actual_fsize
)));
else
if
(
actual_fsize
!=
0
)
else
if
(
actual_fsize
!=
0
)
...
@@ -3188,8 +3196,8 @@ return_addr_rtx (count, frameaddr)
...
@@ -3188,8 +3196,8 @@ return_addr_rtx (count, frameaddr)
privilege level from the two low order bits of the return address
privilege level from the two low order bits of the return address
pointer here so that ins will point to the start of the first
pointer here so that ins will point to the start of the first
instruction that would have been executed if we returned. */
instruction that would have been executed if we returned. */
ins
=
copy_to_reg
(
gen_rtx
(
AND
,
Pmode
,
ins
=
copy_to_reg
(
gen_rtx
_AND
(
Pmode
,
copy_to_reg
(
gen_rtx
(
MEM
,
Pmode
,
saved_rp
)),
copy_to_reg
(
gen_rtx_MEM
(
Pmode
,
saved_rp
)),
MASK_RETURN_ADDR
));
MASK_RETURN_ADDR
));
label
=
gen_label_rtx
();
label
=
gen_label_rtx
();
...
@@ -3204,22 +3212,22 @@ return_addr_rtx (count, frameaddr)
...
@@ -3204,22 +3212,22 @@ return_addr_rtx (count, frameaddr)
If it is an export stub, than our return address is really in
If it is an export stub, than our return address is really in
-24[frameaddr]. */
-24[frameaddr]. */
emit_cmp_insn
(
gen_rtx
(
MEM
,
SImode
,
ins
),
emit_cmp_insn
(
gen_rtx
_MEM
(
SImode
,
ins
),
GEN_INT
(
0x4bc23fd1
),
GEN_INT
(
0x4bc23fd1
),
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
emit_jump_insn
(
gen_bne
(
label
));
emit_jump_insn
(
gen_bne
(
label
));
emit_cmp_insn
(
gen_rtx
(
MEM
,
SImode
,
plus_constant
(
ins
,
4
)),
emit_cmp_insn
(
gen_rtx
_MEM
(
SImode
,
plus_constant
(
ins
,
4
)),
GEN_INT
(
0x004010a1
),
GEN_INT
(
0x004010a1
),
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
emit_jump_insn
(
gen_bne
(
label
));
emit_jump_insn
(
gen_bne
(
label
));
emit_cmp_insn
(
gen_rtx
(
MEM
,
SImode
,
plus_constant
(
ins
,
8
)),
emit_cmp_insn
(
gen_rtx
_MEM
(
SImode
,
plus_constant
(
ins
,
8
)),
GEN_INT
(
0x00011820
),
GEN_INT
(
0x00011820
),
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
emit_jump_insn
(
gen_bne
(
label
));
emit_jump_insn
(
gen_bne
(
label
));
emit_cmp_insn
(
gen_rtx
(
MEM
,
SImode
,
plus_constant
(
ins
,
12
)),
emit_cmp_insn
(
gen_rtx
_MEM
(
SImode
,
plus_constant
(
ins
,
12
)),
GEN_INT
(
0xe0400002
),
GEN_INT
(
0xe0400002
),
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
NE
,
NULL_RTX
,
SImode
,
1
,
0
);
...
@@ -3236,7 +3244,7 @@ return_addr_rtx (count, frameaddr)
...
@@ -3236,7 +3244,7 @@ return_addr_rtx (count, frameaddr)
emit_move_insn
(
saved_rp
,
plus_constant
(
frameaddr
,
-
6
*
UNITS_PER_WORD
));
emit_move_insn
(
saved_rp
,
plus_constant
(
frameaddr
,
-
6
*
UNITS_PER_WORD
));
emit_label
(
label
);
emit_label
(
label
);
return
gen_rtx
(
MEM
,
Pmode
,
memory_address
(
Pmode
,
saved_rp
));
return
gen_rtx
_MEM
(
Pmode
,
memory_address
(
Pmode
,
saved_rp
));
}
}
/* This is only valid once reload has completed because it depends on
/* This is only valid once reload has completed because it depends on
...
@@ -3261,12 +3269,13 @@ emit_bcond_fp (code, operand0)
...
@@ -3261,12 +3269,13 @@ emit_bcond_fp (code, operand0)
enum
rtx_code
code
;
enum
rtx_code
code
;
rtx
operand0
;
rtx
operand0
;
{
{
emit_jump_insn
(
gen_rtx
(
SET
,
VOIDmode
,
pc_rtx
,
emit_jump_insn
(
gen_rtx_SET
(
VOIDmode
,
pc_rtx
,
gen_rtx
(
IF_THEN_ELSE
,
VOIDmode
,
gen_rtx_IF_THEN_ELSE
(
VOIDmode
,
gen_rtx
(
code
,
VOIDmode
,
gen_rtx_fmt_ee
(
code
,
gen_rtx
(
REG
,
CCFPmode
,
0
),
VOIDmode
,
gen_rtx_REG
(
CCFPmode
,
0
),
const0_rtx
),
const0_rtx
),
gen_rtx
(
LABEL_REF
,
VOIDmode
,
operand0
),
gen_rtx_LABEL_REF
(
VOIDmode
,
operand0
),
pc_rtx
)));
pc_rtx
)));
}
}
...
@@ -3276,8 +3285,8 @@ gen_cmp_fp (code, operand0, operand1)
...
@@ -3276,8 +3285,8 @@ gen_cmp_fp (code, operand0, operand1)
enum
rtx_code
code
;
enum
rtx_code
code
;
rtx
operand0
,
operand1
;
rtx
operand0
,
operand1
;
{
{
return
gen_rtx
(
SET
,
VOIDmode
,
gen_rtx
(
REG
,
CCFPmode
,
0
),
return
gen_rtx
_SET
(
VOIDmode
,
gen_rtx_REG
(
CCFPmode
,
0
),
gen_rtx
(
code
,
CCFPmode
,
operand0
,
operand1
));
gen_rtx_fmt_ee
(
code
,
CCFPmode
,
operand0
,
operand1
));
}
}
/* Adjust the cost of a scheduling dependency. Return the new cost of
/* Adjust the cost of a scheduling dependency. Return the new cost of
...
@@ -3980,7 +3989,7 @@ output_deferred_plabels (file)
...
@@ -3980,7 +3989,7 @@ output_deferred_plabels (file)
for
(
i
=
0
;
i
<
n_deferred_plabels
;
i
++
)
for
(
i
=
0
;
i
<
n_deferred_plabels
;
i
++
)
{
{
ASM_OUTPUT_INTERNAL_LABEL
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
deferred_plabels
[
i
].
internal_label
));
ASM_OUTPUT_INTERNAL_LABEL
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
deferred_plabels
[
i
].
internal_label
));
assemble_integer
(
gen_rtx
(
SYMBOL_REF
,
VOIDmode
,
assemble_integer
(
gen_rtx
_SYMBOL_REF
(
VOIDmode
,
deferred_plabels
[
i
].
name
),
4
,
1
);
deferred_plabels
[
i
].
name
),
4
,
1
);
}
}
}
}
...
@@ -4018,7 +4027,7 @@ output_mul_insn (unsignedp, insn)
...
@@ -4018,7 +4027,7 @@ output_mul_insn (unsignedp, insn)
rtx
insn
;
rtx
insn
;
{
{
import_milli
(
mulI
);
import_milli
(
mulI
);
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
"$$mulI"
));
return
output_millicode_call
(
insn
,
gen_rtx
_SYMBOL_REF
(
SImode
,
"$$mulI"
));
}
}
/* Emit the rtl for doing a division by a constant. */
/* Emit the rtl for doing a division by a constant. */
...
@@ -4054,19 +4063,20 @@ emit_hpdiv_const (operands, unsignedp)
...
@@ -4054,19 +4063,20 @@ emit_hpdiv_const (operands, unsignedp)
&&
INTVAL
(
operands
[
2
])
<
16
&&
INTVAL
(
operands
[
2
])
<
16
&&
magic_milli
[
INTVAL
(
operands
[
2
])])
&&
magic_milli
[
INTVAL
(
operands
[
2
])])
{
{
emit_move_insn
(
gen_rtx
(
REG
,
SImode
,
26
),
operands
[
1
]);
emit_move_insn
(
gen_rtx_REG
(
SImode
,
26
),
operands
[
1
]);
emit
emit
(
gen_rtx
(
gen_rtx
(
PARALLEL
,
VOIDmode
,
(
PARALLEL
,
VOIDmode
,
gen_rtvec
(
5
,
gen_rtx
(
SET
,
VOIDmode
,
gen_rtx
(
REG
,
SImode
,
29
),
gen_rtvec
(
5
,
gen_rtx_SET
(
VOIDmode
,
gen_rtx_REG
(
SImode
,
29
),
gen_rtx
(
unsignedp
?
UDIV
:
DIV
,
SImode
,
gen_rtx_fmt_ee
(
unsignedp
?
UDIV
:
DIV
,
gen_rtx
(
REG
,
SImode
,
26
),
SImode
,
gen_rtx_REG
(
SImode
,
26
),
operands
[
2
])),
operands
[
2
])),
gen_rtx
(
CLOBBER
,
VOIDmode
,
operands
[
3
]),
gen_rtx
_CLOBBER
(
VOIDmode
,
operands
[
3
]),
gen_rtx
(
CLOBBER
,
VOIDmode
,
gen_rtx
(
REG
,
SImode
,
26
)),
gen_rtx
_CLOBBER
(
VOIDmode
,
gen_rtx_REG
(
SImode
,
26
)),
gen_rtx
(
CLOBBER
,
VOIDmode
,
gen_rtx
(
REG
,
SImode
,
25
)),
gen_rtx
_CLOBBER
(
VOIDmode
,
gen_rtx_REG
(
SImode
,
25
)),
gen_rtx
(
CLOBBER
,
VOIDmode
,
gen_rtx
(
REG
,
SImode
,
31
)))));
gen_rtx
_CLOBBER
(
VOIDmode
,
gen_rtx_REG
(
SImode
,
31
)))));
emit_move_insn
(
operands
[
0
],
gen_rtx
(
REG
,
SImode
,
29
));
emit_move_insn
(
operands
[
0
],
gen_rtx
_REG
(
SImode
,
29
));
return
1
;
return
1
;
}
}
return
0
;
return
0
;
...
@@ -4098,13 +4108,13 @@ output_div_insn (operands, unsignedp, insn)
...
@@ -4098,13 +4108,13 @@ output_div_insn (operands, unsignedp, insn)
{
{
sprintf
(
buf
,
"$$divU_%d"
,
INTVAL
(
operands
[
0
]));
sprintf
(
buf
,
"$$divU_%d"
,
INTVAL
(
operands
[
0
]));
return
output_millicode_call
(
insn
,
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
buf
));
gen_rtx
_SYMBOL_REF
(
SImode
,
buf
));
}
}
else
else
{
{
sprintf
(
buf
,
"$$divI_%d"
,
INTVAL
(
operands
[
0
]));
sprintf
(
buf
,
"$$divI_%d"
,
INTVAL
(
operands
[
0
]));
return
output_millicode_call
(
insn
,
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
buf
));
gen_rtx
_SYMBOL_REF
(
SImode
,
buf
));
}
}
}
}
/* Divisor isn't a special constant. */
/* Divisor isn't a special constant. */
...
@@ -4114,13 +4124,13 @@ output_div_insn (operands, unsignedp, insn)
...
@@ -4114,13 +4124,13 @@ output_div_insn (operands, unsignedp, insn)
{
{
import_milli
(
divU
);
import_milli
(
divU
);
return
output_millicode_call
(
insn
,
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
"$$divU"
));
gen_rtx
_SYMBOL_REF
(
SImode
,
"$$divU"
));
}
}
else
else
{
{
import_milli
(
divI
);
import_milli
(
divI
);
return
output_millicode_call
(
insn
,
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
"$$divI"
));
gen_rtx
_SYMBOL_REF
(
SImode
,
"$$divI"
));
}
}
}
}
}
}
...
@@ -4136,13 +4146,13 @@ output_mod_insn (unsignedp, insn)
...
@@ -4136,13 +4146,13 @@ output_mod_insn (unsignedp, insn)
{
{
import_milli
(
remU
);
import_milli
(
remU
);
return
output_millicode_call
(
insn
,
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
"$$remU"
));
gen_rtx
_SYMBOL_REF
(
SImode
,
"$$remU"
));
}
}
else
else
{
{
import_milli
(
remI
);
import_milli
(
remI
);
return
output_millicode_call
(
insn
,
return
output_millicode_call
(
insn
,
gen_rtx
(
SYMBOL_REF
,
SImode
,
"$$remI"
));
gen_rtx
_SYMBOL_REF
(
SImode
,
"$$remI"
));
}
}
}
}
...
@@ -4358,8 +4368,9 @@ hppa_builtin_saveregs (arglist)
...
@@ -4358,8 +4368,9 @@ hppa_builtin_saveregs (arglist)
offset
=
current_function_arg_offset_rtx
;
offset
=
current_function_arg_offset_rtx
;
/* Store general registers on the stack. */
/* Store general registers on the stack. */
dest
=
gen_rtx
(
MEM
,
BLKmode
,
dest
=
gen_rtx_MEM
(
BLKmode
,
plus_constant
(
current_function_internal_arg_pointer
,
-
16
));
plus_constant
(
current_function_internal_arg_pointer
,
-
16
));
move_block_from_reg
(
23
,
dest
,
4
,
4
*
UNITS_PER_WORD
);
move_block_from_reg
(
23
,
dest
,
4
,
4
*
UNITS_PER_WORD
);
/* move_block_from_reg will emit code to store the argument registers
/* move_block_from_reg will emit code to store the argument registers
...
@@ -5294,14 +5305,14 @@ output_call (insn, call_dest)
...
@@ -5294,14 +5305,14 @@ output_call (insn, call_dest)
if
(
arg_mode
==
SFmode
)
if
(
arg_mode
==
SFmode
)
{
{
xoperands
[
0
]
=
XEXP
(
use
,
0
);
xoperands
[
0
]
=
XEXP
(
use
,
0
);
xoperands
[
1
]
=
gen_rtx
(
REG
,
SImode
,
26
-
(
regno
-
32
)
/
2
);
xoperands
[
1
]
=
gen_rtx
_REG
(
SImode
,
26
-
(
regno
-
32
)
/
2
);
output_asm_insn
(
"fstws %0,-16(%%sr0,%%r30)"
,
xoperands
);
output_asm_insn
(
"fstws %0,-16(%%sr0,%%r30)"
,
xoperands
);
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
);
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
);
}
}
else
else
{
{
xoperands
[
0
]
=
XEXP
(
use
,
0
);
xoperands
[
0
]
=
XEXP
(
use
,
0
);
xoperands
[
1
]
=
gen_rtx
(
REG
,
DImode
,
25
-
(
regno
-
34
)
/
2
);
xoperands
[
1
]
=
gen_rtx
_REG
(
DImode
,
25
-
(
regno
-
34
)
/
2
);
output_asm_insn
(
"fstds %0,-16(%%sr0,%%r30)"
,
xoperands
);
output_asm_insn
(
"fstds %0,-16(%%sr0,%%r30)"
,
xoperands
);
output_asm_insn
(
"ldw -12(%%sr0,%%r30),%R1"
,
xoperands
);
output_asm_insn
(
"ldw -12(%%sr0,%%r30),%R1"
,
xoperands
);
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
);
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
);
...
@@ -6151,7 +6162,7 @@ pa_combine_instructions (insns)
...
@@ -6151,7 +6162,7 @@ pa_combine_instructions (insns)
may be combined with "floating" insns. As the name implies,
may be combined with "floating" insns. As the name implies,
"anchor" instructions don't move, while "floating" insns may
"anchor" instructions don't move, while "floating" insns may
move around. */
move around. */
new
=
gen_rtx
(
PARALLEL
,
VOIDmode
,
gen_rtvec
(
2
,
NULL_RTX
,
NULL_RTX
));
new
=
gen_rtx
_PARALLEL
(
VOIDmode
,
gen_rtvec
(
2
,
NULL_RTX
,
NULL_RTX
));
new
=
make_insn_raw
(
new
);
new
=
make_insn_raw
(
new
);
for
(
anchor
=
get_insns
();
anchor
;
anchor
=
NEXT_INSN
(
anchor
))
for
(
anchor
=
get_insns
();
anchor
;
anchor
=
NEXT_INSN
(
anchor
))
...
@@ -6286,8 +6297,9 @@ pa_combine_instructions (insns)
...
@@ -6286,8 +6297,9 @@ pa_combine_instructions (insns)
||
anchor_attr
==
PA_COMBINE_TYPE_FMPY
))
||
anchor_attr
==
PA_COMBINE_TYPE_FMPY
))
{
{
/* Emit the new instruction and delete the old anchor. */
/* Emit the new instruction and delete the old anchor. */
emit_insn_before
(
gen_rtx
(
PARALLEL
,
VOIDmode
,
emit_insn_before
(
gen_rtx_PARALLEL
(
VOIDmode
,
gen_rtvec
(
2
,
PATTERN
(
anchor
),
gen_rtvec
(
2
,
PATTERN
(
anchor
),
PATTERN
(
floater
))),
PATTERN
(
floater
))),
anchor
);
anchor
);
PUT_CODE
(
anchor
,
NOTE
);
PUT_CODE
(
anchor
,
NOTE
);
...
@@ -6296,7 +6308,7 @@ pa_combine_instructions (insns)
...
@@ -6296,7 +6308,7 @@ pa_combine_instructions (insns)
/* Emit a special USE insn for FLOATER, then delete
/* Emit a special USE insn for FLOATER, then delete
the floating insn. */
the floating insn. */
emit_insn_before
(
gen_rtx
(
USE
,
VOIDmode
,
floater
),
floater
);
emit_insn_before
(
gen_rtx
_USE
(
VOIDmode
,
floater
),
floater
);
delete_insn
(
floater
);
delete_insn
(
floater
);
continue
;
continue
;
...
@@ -6306,7 +6318,7 @@ pa_combine_instructions (insns)
...
@@ -6306,7 +6318,7 @@ pa_combine_instructions (insns)
{
{
rtx
temp
;
rtx
temp
;
/* Emit the new_jump instruction and delete the old anchor. */
/* Emit the new_jump instruction and delete the old anchor. */
temp
=
emit_jump_insn_before
(
gen_rtx
(
PARALLEL
,
VOIDmode
,
temp
=
emit_jump_insn_before
(
gen_rtx
_PARALLEL
(
VOIDmode
,
gen_rtvec
(
2
,
PATTERN
(
anchor
),
gen_rtvec
(
2
,
PATTERN
(
anchor
),
PATTERN
(
floater
))),
PATTERN
(
floater
))),
anchor
);
anchor
);
...
@@ -6317,7 +6329,7 @@ pa_combine_instructions (insns)
...
@@ -6317,7 +6329,7 @@ pa_combine_instructions (insns)
/* Emit a special USE insn for FLOATER, then delete
/* Emit a special USE insn for FLOATER, then delete
the floating insn. */
the floating insn. */
emit_insn_before
(
gen_rtx
(
USE
,
VOIDmode
,
floater
),
floater
);
emit_insn_before
(
gen_rtx
_USE
(
VOIDmode
,
floater
),
floater
);
delete_insn
(
floater
);
delete_insn
(
floater
);
continue
;
continue
;
}
}
...
...
gcc/config/pa/pa.h
View file @
ad2c71b7
...
@@ -803,7 +803,7 @@ int zdepi_cint_p ();
...
@@ -803,7 +803,7 @@ int zdepi_cint_p ();
/* Return the stack location to use for secondary memory needed reloads. */
/* Return the stack location to use for secondary memory needed reloads. */
#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
gen_rtx
(MEM, MODE, gen_rtx (PLUS,
Pmode, stack_pointer_rtx, GEN_INT (-16)))
gen_rtx
_MEM (MODE, gen_rtx_PLUS (
Pmode, stack_pointer_rtx, GEN_INT (-16)))
/* Return the maximum number of consecutive registers
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
needed to represent mode MODE in a register of class CLASS. */
...
@@ -909,7 +909,7 @@ int zdepi_cint_p ();
...
@@ -909,7 +909,7 @@ int zdepi_cint_p ();
#define FUNCTION_VALUE(VALTYPE, FUNC) \
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx
(REG,
TYPE_MODE (VALTYPE), ((! TARGET_SOFT_FLOAT \
gen_rtx
_REG (
TYPE_MODE (VALTYPE), ((! TARGET_SOFT_FLOAT \
&& (TYPE_MODE (VALTYPE) == SFmode || \
&& (TYPE_MODE (VALTYPE) == SFmode || \
TYPE_MODE (VALTYPE) == DFmode)) ? \
TYPE_MODE (VALTYPE) == DFmode)) ? \
32 : 28))
32 : 28))
...
@@ -918,7 +918,7 @@ int zdepi_cint_p ();
...
@@ -918,7 +918,7 @@ int zdepi_cint_p ();
assuming the value has mode MODE. */
assuming the value has mode MODE. */
#define LIBCALL_VALUE(MODE) \
#define LIBCALL_VALUE(MODE) \
gen_rtx
(REG,
MODE, \
gen_rtx
_REG (
MODE, \
(! TARGET_SOFT_FLOAT \
(! TARGET_SOFT_FLOAT \
&& ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
&& ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
...
@@ -1044,7 +1044,7 @@ struct hppa_args {int words, nargs_prototype, indirect; };
...
@@ -1044,7 +1044,7 @@ struct hppa_args {int words, nargs_prototype, indirect; };
? (!TARGET_PORTABLE_RUNTIME || (TYPE) == 0 \
? (!TARGET_PORTABLE_RUNTIME || (TYPE) == 0 \
|| !FLOAT_MODE_P (MODE) || TARGET_SOFT_FLOAT \
|| !FLOAT_MODE_P (MODE) || TARGET_SOFT_FLOAT \
|| (CUM).nargs_prototype > 0) \
|| (CUM).nargs_prototype > 0) \
? gen_rtx
(REG,
(MODE), \
? gen_rtx
_REG (
(MODE), \
(FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
(FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
? (((!(CUM).indirect \
? (((!(CUM).indirect \
|| TARGET_PORTABLE_RUNTIME) \
|| TARGET_PORTABLE_RUNTIME) \
...
@@ -1061,17 +1061,17 @@ struct hppa_args {int words, nargs_prototype, indirect; };
...
@@ -1061,17 +1061,17 @@ struct hppa_args {int words, nargs_prototype, indirect; };
(TYPE))))))\
(TYPE))))))\
/* We are calling a non-prototyped function with floating point \
/* We are calling a non-prototyped function with floating point \
arguments using the portable conventions. */
\
arguments using the portable conventions. */
\
: gen_rtx
(PARALLEL,
(MODE), \
: gen_rtx
_PARALLEL (
(MODE), \
gen_rtvec \
gen_rtvec \
(2, \
(2, \
gen_rtx
(EXPR_LIST,
VOIDmode, \
gen_rtx
_EXPR_LIST (
VOIDmode, \
gen_rtx
(REG,
(MODE), \
gen_rtx
_REG (
(MODE), \
(FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
(FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
? ((CUM).words ? 38 : 34) \
? ((CUM).words ? 38 : 34) \
: (32 + 2 * (CUM).words))), \
: (32 + 2 * (CUM).words))), \
const0_rtx), \
const0_rtx), \
gen_rtx
(EXPR_LIST,
VOIDmode, \
gen_rtx
_EXPR_LIST (
VOIDmode, \
gen_rtx
(REG,
(MODE), \
gen_rtx
_REG (
(MODE), \
(FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
(FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
? ((CUM).words ? 23 : 25) \
? ((CUM).words ? 23 : 25) \
: (27 - (CUM).words - \
: (27 - (CUM).words - \
...
@@ -1343,9 +1343,9 @@ extern union tree_node *current_function_decl;
...
@@ -1343,9 +1343,9 @@ extern union tree_node *current_function_decl;
rtx start_addr, end_addr; \
rtx start_addr, end_addr; \
\
\
start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
emit_move_insn (gen_rtx
(MEM,
Pmode, start_addr), (FNADDR)); \
emit_move_insn (gen_rtx
_MEM (
Pmode, start_addr), (FNADDR)); \
start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
emit_move_insn (gen_rtx
(MEM,
Pmode, start_addr), (CXT)); \
emit_move_insn (gen_rtx
_MEM (
Pmode, start_addr), (CXT)); \
/* fdc and fic only use registers for the address to flush, \
/* fdc and fic only use registers for the address to flush, \
they do not accept integer displacements. */
\
they do not accept integer displacements. */
\
start_addr = force_reg (SImode, (TRAMP)); \
start_addr = force_reg (SImode, (TRAMP)); \
...
...
gcc/config/pa/pa.md
View file @
ad2c71b7
...
@@ -808,7 +808,7 @@
...
@@ -808,7 +808,7 @@
/
*
operands
[
1
]
is currently the result of compare_from_rtx. We want to
/
*
operands
[
1
]
is currently the result of compare_from_rtx. We want to
emit a compare of the original operands.
*
/
emit a compare of the original operands.
*
/
operands
[
1
]
= gen_rtx (code, SImode, hppa_compare_op0, hppa_compare_op1);
operands
[
1
]
= gen_rtx
_fmt_ee
(code, SImode, hppa_compare_op0, hppa_compare_op1);
operands
[
4
]
= hppa_compare_op0;
operands
[
4
]
= hppa_compare_op0;
operands
[
5
]
= hppa_compare_op1;
operands
[
5
]
= hppa_compare_op1;
}")
}")
...
@@ -1316,7 +1316,7 @@
...
@@ -1316,7 +1316,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -1331,7 +1331,7 @@
...
@@ -1331,7 +1331,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2190,7 +2190,7 @@
...
@@ -2190,7 +2190,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2205,7 +2205,7 @@
...
@@ -2205,7 +2205,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2341,7 +2341,7 @@
...
@@ -2341,7 +2341,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2356,7 +2356,7 @@
...
@@ -2356,7 +2356,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2495,7 +2495,7 @@
...
@@ -2495,7 +2495,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2510,7 +2510,7 @@
...
@@ -2510,7 +2510,7 @@
DONE;
DONE;
/
* We don't want the clobber emitted, so handle this ourselves. *
/
/
* We don't want the clobber emitted, so handle this ourselves. *
/
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
0
]
, operands
[
1
]
));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
0
]
, operands
[
1
]
));
DONE;
DONE;
}")
}")
...
@@ -2937,7 +2937,7 @@
...
@@ -2937,7 +2937,7 @@
}
}
else if (cint_ok_for_move (-intval))
else if (cint_ok_for_move (-intval))
{
{
emit_insn (gen_rtx
(SET,
VOIDmode, operands
[
4
]
, GEN_INT (-intval)));
emit_insn (gen_rtx
_SET (
VOIDmode, operands
[
4
]
, GEN_INT (-intval)));
emit_insn (gen_subsi3 (operands
[
0
]
, operands
[
1
]
, operands
[
4
]
));
emit_insn (gen_subsi3 (operands
[
0
]
, operands
[
1
]
, operands
[
4
]
));
DONE;
DONE;
}
}
...
@@ -3019,9 +3019,9 @@
...
@@ -3019,9 +3019,9 @@
operands
[
1
]
= force_reg (SImode, operands
[
1
]
);
operands
[
1
]
= force_reg (SImode, operands
[
1
]
);
operands
[
2
]
= force_reg (SImode, operands
[
2
]
);
operands
[
2
]
= force_reg (SImode, operands
[
2
]
);
emit_insn (gen_umulsidi3 (scratch, operands
[
1
]
, operands
[
2
]
));
emit_insn (gen_umulsidi3 (scratch, operands
[
1
]
, operands
[
2
]
));
emit_insn (gen_rtx
(SET,
VOIDmode,
emit_insn (gen_rtx
_SET (
VOIDmode,
operands
[
0
]
,
operands
[
0
]
,
gen_rtx (SUBREG,
SImode, scratch, 1)));
gen_rtx_SUBREG (
SImode, scratch, 1)));
DONE;
DONE;
}
}
operands
[
3
]
= gen_reg_rtx (SImode);
operands
[
3
]
= gen_reg_rtx (SImode);
...
@@ -4029,7 +4029,7 @@
...
@@ -4029,7 +4029,7 @@
if (TARGET_BIG_SWITCH)
if (TARGET_BIG_SWITCH)
{
{
rtx temp = gen_reg_rtx (SImode);
rtx temp = gen_reg_rtx (SImode);
emit_move_insn (temp, gen_rtx
(PLUS,
SImode, operands
[
0
]
, operands
[
0
]
));
emit_move_insn (temp, gen_rtx
_PLUS (
SImode, operands
[
0
]
, operands
[
0
]
));
operands
[
0
]
= temp;
operands
[
0
]
= temp;
}
}
emit_jump_insn (gen_casesi0 (operands
[
0
]
, operands
[
3
]
));
emit_jump_insn (gen_casesi0 (operands
[
0
]
, operands
[
3
]
));
...
@@ -4074,7 +4074,7 @@
...
@@ -4074,7 +4074,7 @@
call_insn = emit_call_insn (gen_call_internal_symref (op, operands
[
1
]
));
call_insn = emit_call_insn (gen_call_internal_symref (op, operands
[
1
]
));
else
else
{
{
rtx tmpreg = gen_rtx
(REG,
SImode, 22);
rtx tmpreg = gen_rtx
_REG (
SImode, 22);
emit_move_insn (tmpreg, force_reg (SImode, op));
emit_move_insn (tmpreg, force_reg (SImode, op));
call_insn = emit_call_insn (gen_call_internal_reg (operands
[
1
]
));
call_insn = emit_call_insn (gen_call_internal_reg (operands
[
1
]
));
}
}
...
@@ -4089,8 +4089,8 @@
...
@@ -4089,8 +4089,8 @@
This will set regs_ever_live for the callee saved register we
This will set regs_ever_live for the callee saved register we
stored the PIC register in. */
stored the PIC register in. */
emit_move_insn (pic_offset_table_rtx,
emit_move_insn (pic_offset_table_rtx,
gen_rtx
(REG,
SImode, PIC_OFFSET_TABLE_REGNUM_SAVED));
gen_rtx
_REG (
SImode, PIC_OFFSET_TABLE_REGNUM_SAVED));
emit_insn (gen_rtx
(USE,
VOIDmode, pic_offset_table_rtx));
emit_insn (gen_rtx
_USE (
VOIDmode, pic_offset_table_rtx));
/* Gross. We have to keep the scheduler from moving the restore
/* Gross. We have to keep the scheduler from moving the restore
of the PIC register away from the call. SCHED_GROUP_P is
of the PIC register away from the call. SCHED_GROUP_P is
...
@@ -4114,7 +4114,7 @@
...
@@ -4114,7 +4114,7 @@
"
*
"
*
{
{
output_arg_descriptor (insn);
output_arg_descriptor (insn);
return output_call (insn, operands
[
0
]
, gen_rtx
(REG,
SImode, 2));
return output_call (insn, operands
[
0
]
, gen_rtx
_REG (
SImode, 2));
}"
}"
[
(set_attr "type" "call")
[
(set_attr "type" "call")
(set (attr "length")
(set (attr "length")
...
@@ -4231,7 +4231,7 @@
...
@@ -4231,7 +4231,7 @@
operands
[
2
]
));
operands
[
2
]
));
else
else
{
{
rtx tmpreg = gen_rtx
(REG,
SImode, 22);
rtx tmpreg = gen_rtx
_REG (
SImode, 22);
emit_move_insn (tmpreg, force_reg (SImode, op));
emit_move_insn (tmpreg, force_reg (SImode, op));
call_insn = emit_call_insn (gen_call_value_internal_reg (operands
[
0
]
,
call_insn = emit_call_insn (gen_call_value_internal_reg (operands
[
0
]
,
operands
[
2
]
));
operands
[
2
]
));
...
@@ -4246,8 +4246,8 @@
...
@@ -4246,8 +4246,8 @@
This will set regs_ever_live for the callee saved register we
This will set regs_ever_live for the callee saved register we
stored the PIC register in. */
stored the PIC register in. */
emit_move_insn (pic_offset_table_rtx,
emit_move_insn (pic_offset_table_rtx,
gen_rtx
(REG,
SImode, PIC_OFFSET_TABLE_REGNUM_SAVED));
gen_rtx
_REG (
SImode, PIC_OFFSET_TABLE_REGNUM_SAVED));
emit_insn (gen_rtx
(USE,
VOIDmode, pic_offset_table_rtx));
emit_insn (gen_rtx
_USE (
VOIDmode, pic_offset_table_rtx));
/* Gross. We have to keep the scheduler from moving the restore
/* Gross. We have to keep the scheduler from moving the restore
of the PIC register away from the call. SCHED_GROUP_P is
of the PIC register away from the call. SCHED_GROUP_P is
...
@@ -4273,7 +4273,7 @@
...
@@ -4273,7 +4273,7 @@
"
*
"
*
{
{
output_arg_descriptor (insn);
output_arg_descriptor (insn);
return output_call (insn, operands
[
1
]
, gen_rtx
(REG,
SImode, 2));
return output_call (insn, operands
[
1
]
, gen_rtx
_REG (
SImode, 2));
}"
}"
[
(set_attr "type" "call")
[
(set_attr "type" "call")
(set (attr "length")
(set (attr "length")
...
@@ -4508,7 +4508,7 @@
...
@@ -4508,7 +4508,7 @@
;; This insn is used for some loop tests, typically loops reversed when
;; This insn is used for some loop tests, typically loops reversed when
;; strength reduction is used. It is actually created when the instruction
;; strength reduction is used. It is actually created when the instruction
;; combination phase combines the special loop test. Since this insn
;; combination phase combines the special loop test. Since this insn
;; is both a jump insn and has an output, it must deal with it
'
s own
;; is both a jump insn and has an output, it must deal with its own
;; reloads, hence the
`m' constraints. The `
!' constraints direct reload
;; reloads, hence the
`m' constraints. The `
!' constraints direct reload
;; to not choose the register alternatives in the event a reload is needed.
;; to not choose the register alternatives in the event a reload is needed.
(define_insn "decrement_and_branch_until_zero"
(define_insn "decrement_and_branch_until_zero"
...
@@ -5112,8 +5112,7 @@
...
@@ -5112,8 +5112,7 @@
/
* Else call $$sh_func_adrs to extract the function's real add24. *
/
/
* Else call $$sh_func_adrs to extract the function's real add24. *
/
return output_millicode_call (insn,
return output_millicode_call (insn,
gen_rtx (SYMBOL_REF, SImode,
gen_rtx_SYMBOL_REF (SImode,
\"
$$sh_func_adrs
\"
));
\"
$$sh_func_adrs
\"
));
}"
}"
[
(set_attr "type" "multi")
[
(set_attr "type" "multi")
(set (attr "length")
(set (attr "length")
...
@@ -5159,9 +5158,8 @@
...
@@ -5159,9 +5158,8 @@
/
*
Load the PIC register from the stack slot (in our caller's
/
*
Load the PIC register from the stack slot (in our caller's
frame).
*
/
frame).
*
/
emit_move_insn (pic_offset_table_rtx,
emit_move_insn (pic_offset_table_rtx,
gen_rtx (MEM, SImode,
gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, -32)));
plus_constant (stack_pointer_rtx, -32)));
emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
emit_insn (gen_blockage ());
emit_insn (gen_blockage ());
DONE;
DONE;
}")
}")
...
...
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