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riscv-gcc-1
Commit ad0e4f77 by Tom Wood
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(type attributes): Delete unused mbit and mfp types. 

	(ffsi2 insn): Define.
	(negdf2 and absdf2 insns): Improve.

From-SVN: r1307
parent f5902869
Showing with 44 additions and 34 deletions
gcc/config/m88k/m88k.md
......@@ -28,7 +28,7 @@
(define_expand "m88k_sccs_id"
[(match_operand:SI 0 "" "")]
""
"{ static char sccs_id[] = \"@(#)m88k.md 2.1.11.6 29 May 1992 10:55:49\";
"{ static char sccs_id[] = \"@(#)m88k.md 2.2.3.6 27 Jun 1992 06:29:32\";
FAIL; }")
;; Attribute specifications
......@@ -45,31 +45,31 @@
; spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions
; spmul,dpmul,imul, ; FPU multiply instructions
; arith,bit,mov ; integer unit instructions
; marith,mbit,mfp,weird" ; multi-word instructions
; marith,weird" ; multi-word instructions
; Classification of each insn. Some insns of TYPE_BRANCH are multi-word.
(define_attr "type"
"branch,jump,call,load,store,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,mbit,mfp,weird"
"branch,jump,call,load,store,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,weird"
(const_string "arith"))
; Convenience attributes.
(define_attr "unit" "bit,memory,multiply,divide,fpadd,other"
(cond [(eq_attr "type" "bit,mbit") (const_string "bit")
(cond [(eq_attr "type" "bit") (const_string "bit")
(eq_attr "type" "load,store") (const_string "memory")
(eq_attr "type" "spmul,dpmul,imul") (const_string "multiply")
(eq_attr "type" "spdiv,dpdiv,idiv") (const_string "divide")
(eq_attr "type" "spadd,dpadd,spcmp,dpcmp,mfp") (const_string "fpadd")]
(eq_attr "type" "spadd,dpadd,spcmp,dpcmp") (const_string "fpadd")]
(const_string "other")))
(define_attr "fpu" "yes,no"
(if_then_else
(eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,mfp")
(eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv")
(const_string "yes") (const_string "no")))
; Length in # of instructions of each insn. The values are not exact, but
; are safe.
(define_attr "length" ""
(cond [(eq_attr "type" "marith,mbit,mfp")
(cond [(eq_attr "type" "marith")
(const_int 2)]
(const_int 1)))
......@@ -88,7 +88,7 @@
(define_delay (eq_attr "type" "branch,jump")
[(and
(and
(eq_attr "type" "!branch,jump,call,marith,mbit,mfp,weird") ; required.
(eq_attr "type" "!branch,jump,call,marith,weird") ; required.
(eq_attr "type" "!load")) ; issue as-soon-as-possible.
(eq_attr "fpu" "no")) ; issue as-soon-as-possible.
(eq_attr "type" "!call,branch,jump") (nil)]) ; @@ was (const_int 1)
......@@ -97,7 +97,7 @@
; a call. (@@ Support for this case is expected in reorg.c soon.)
(define_delay (eq_attr "type" "call")
[(eq_attr "type" "!branch,call,marith,mbit,mfp,weird") ; required.
[(eq_attr "type" "!branch,call,marith,weird") ; required.
(nil) (nil)])
; An abstract block diagram of the function units for the m88100.
......@@ -145,13 +145,13 @@
; Describing the alu is currently not useful.
;(define_function_unit "alu" 1 0 (eq_attr "type"
; "!store,marith,mbit,mfp,weird") 1 0)
;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,mbit,weird") 2 0)
; "!store,marith,weird") 1 0)
;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0)
(define_function_unit "alu" 1 0
(and (eq_attr "type" "loada,arith,bit,mov") (eq_attr "cpu" "!m88100")) 2 0)
(define_function_unit "alu" 1 0
(and (eq_attr "type" "marith,mbit,weird") (eq_attr "cpu" "!m88100")) 4 0)
(and (eq_attr "type" "marith,weird") (eq_attr "cpu" "!m88100")) 4 0)
(define_function_unit "memory" 1 3
(and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 2)
......@@ -168,12 +168,12 @@
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 2) ; 6-8
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "dpmul,mfp") (eq_attr "cpu" "m88100")) 7 2) ; 9-10
(and (eq_attr "type" "dpmul") (eq_attr "cpu" "m88100")) 7 2) ; 9-10
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 2) ; 4
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "imul,spmul,dpmul,mfp")
(and (eq_attr "type" "imul,spmul,dpmul")
(eq_attr "cpu" "!m88100")) 6 2) ; 3
(define_function_unit "fpadd" 1 3
......@@ -2764,6 +2764,24 @@
"rot %0,%1,%2"
[(set_attr "type" "bit")])
;; find first set.
;; The ff1 instruction searches from the most significant bit while ffs
;; searches from the least significant bit. The bit index and treatment of
;; zero also differ. This amazing sequence was discovered using the GNU
;; Superoptimizer.
(define_insn "ffssi2"
[(set (match_operand:SI 0 "register_operand" "=r,&r")
(ffs:SI (match_operand:SI 1 "register_operand" "0,r")))
(clobber (match_scratch:SI 2 "=r,X"))]
""
"@
subu.co %2,%#r0,%1\;and %2,%2,%1\;addu.ci %2,%2,%2\;ff1 %0,%2
subu.co %0,%#r0,%1\;and %0,%0,%1\;addu.ci %0,%0,%0\;ff1 %0,%0"
[(set_attr "type" "marith")
(set_attr "length" "4")])
;; Bit field instructions.
(define_insn ""
......@@ -2883,18 +2901,14 @@
fsub.ssd %0,%#x0,%1"
[(set_attr "type" "dpadd")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "+r")
(neg:DF (match_dup 0)))]
""
"xor.u %0,%0,0x8000")
(define_insn "negdf2"
[(set (match_operand:DF 0 "register_operand" "=&r")
(neg:DF (match_operand:DF 1 "register_operand" "r")))]
[(set (match_operand:DF 0 "register_operand" "=&r,r")
(neg:DF (match_operand:DF 1 "register_operand" "r,0")))]
""
"xor.u %0,%1,0x8000\;or %d0,%#r0,%d1"
[(set_attr "type" "marith")])
"@
xor.u %0,%1,0x8000\;or %d0,%#r0,%d1
xor.u %0,%0,0x8000"
[(set_attr "type" "marith,arith")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=r")
......@@ -2905,18 +2919,14 @@
;; absolute value insns for floating-point (integer abs can be done using the
;; machine-independent sequence).
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "+r")
(abs:DF (match_dup 0)))]
""
"and.u %0,%0,0x7fff")
(define_insn "absdf2"
[(set (match_operand:DF 0 "register_operand" "=&r")
(abs:DF (match_operand:DF 1 "register_operand" "r")))]
[(set (match_operand:DF 0 "register_operand" "=&r,r")
(abs:DF (match_operand:DF 1 "register_operand" "r,0")))]
""
"and.u %0,%1,0x7fff\;or %d0,%#r0,%d1"
[(set_attr "type" "marith")])
"@
and.u %0,%1,0x7fff\;or %d0,%#r0,%d1
and.u %0,%0,0x7fff"
[(set_attr "type" "marith,arith")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=r")
......
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