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riscv-gcc-1
Commit ab950374 by Alan Modra
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[RS6000] Ignore "c", "l" and "h" for register preference 

This catches a few places where move insn patterns don't slightly
disparage CTR, LR and VRSAVE regs.  Also fixes the doc for the rs6000
h constraint, and removes an r->cl alternative covered by r->h.

	* gcc/doc/md.texi (Machine Constraints): Correct rs6000 h constraint
	description.
	* config/rs6000/rs6000.md (movsi_internal1): Delete MT%0 case
	covered by alternative.
	(movcc_internal1): Ignore h for register preference.
	(mov<mode>_hardfloat64): Likewise.
	(mov<mode>_softfloat): Ignore c, l, h for register preference.

From-SVN: r266044
parent 37e5eefb
Showing with 23 additions and 14 deletions
gcc/ChangeLog
2018-11-13 Alan Modra <amodra@gmail.com>
* gcc/doc/md.texi (Machine Constraints): Correct rs6000 h constraint
description.
* config/rs6000/rs6000.md (movsi_internal1): Delete MT%0 case
covered by alternative.
(movcc_internal1): Ignore h for register preference.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat): Ignore c, l, h for register preference.
2018-11-12 Sandra Loosemore <sandra@codesourcery.com>
PR preprocessor/47823
gcc/config/rs6000/rs6000.md
......@@ -6839,21 +6839,21 @@
;; STW STFIWX STXSIWX LI LIS
;; # XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW
;; XXLXOR 0 XXLORC -1 P9 const MTVSRWZ MFVSRWZ
;; MF%1 MT%0 MT%0 NOP
;; MF%1 MT%0 NOP
(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r, r, ?*wI, ?*wH,
m, ?Z, ?Z, r, r,
r, ?*wIwH, ?*wJwK, ?*wJwK, ?*wu,
?*wJwK, ?*wH, ?*wK, ?*wIwH, ?r,
r, *c*l, *h, *h")
r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U, m, Z, Z,
r, wI, wH, I, L,
n, wIwH, O, wM, wB,
O, wM, wS, r, wIwH,
*h, r, r, 0"))]
*h, r, 0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
......@@ -6880,21 +6880,20 @@
mfvsrwz %0,%x1
mf%1 %0
mt%0 %1
mt%0 %1
nop"
[(set_attr "type"
"*, *, load, fpload, fpload,
store, fpstore, fpstore, *, *,
*, veclogical, vecsimple, vecsimple, vecsimple,
veclogical, veclogical, vecsimple, mffgpr, mftgpr,
*, *, *, *")
*, *, *")
(set_attr "length"
"4, 4, 4, 4, 4,
4, 4, 4, 4, 4,
8, 4, 4, 4, 4,
4, 4, 8, 4, 4,
4, 4, 4, 4")])
4, 4, 4")])
;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0))
......@@ -7172,9 +7171,9 @@
(define_insn "*movcc_internal1"
[(set (match_operand:CC 0 "nonimmediate_operand"
"=y,x,?y,y,r,r,r,r,r,*c*l,r,m")
"=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
(match_operand:CC 1 "general_operand"
" y,r, r,O,x,y,r,I,h, r,m,r"))]
" y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], CCmode)
|| register_operand (operands[1], CCmode)"
"@
......@@ -7326,11 +7325,11 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
"=r, cl, r, r, m, r,
"=r, *c*l, r, r, m, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
"r, r, h, m, r, I,
"r, r, *h, m, r, I,
L, G, Fn, 0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
......@@ -7597,7 +7596,7 @@
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, h,
r, YZ, r, r, *h,
0, wg, r, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
......@@ -7638,11 +7637,11 @@
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=Y, r, r, cl, r, r,
"=Y, r, r, *c*l, r, r,
r, r, *h")
(match_operand:FMOVE64 1 "input_operand"
"r, Y, r, r, h, G,
"r, Y, r, r, *h, G,
H, F, 0"))]
"TARGET_POWERPC64 && TARGET_SOFT_FLOAT
......
gcc/doc/md.texi
......@@ -3273,7 +3273,7 @@ instructions.
Vector constant that can be loaded with XXSPLTIB & sign extension.
@item h
@samp{MQ}, @samp{CTR}, or @samp{LINK} register
@samp{VRSAVE}, @samp{CTR}, or @samp{LINK} register
@item c
@samp{CTR} register
......
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