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riscv-gcc-1
Commit ab51eb25 by Nick Clifton Committed by Nick Clifton
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Change output contraint on post inc load/store multiple patterns to be a 

read/write contraint.

From-SVN: r39566
parent 929408ba
Showing with 14 additions and 9 deletions
gcc/ChangeLog
2001-02-09 Nick Clifton <nickc@redhat.com>
* config/arm/arm.md: Change output contraint on post inc
load/store multiple patterns to be a read/write contraint.
2001-02-09 Neil Booth <neil@daikokuya.demon.co.uk>
* gcc.c (cpp_options): Delete .d files on error. Don't delete
......
gcc/config/arm/arm.md
......@@ -3949,8 +3949,7 @@
(define_insn "*arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>")
(match_operand:DI 1 "di_operand" "rIK,mi,r"))]
"TARGET_ARM
"
"TARGET_ARM"
"*
return (output_move_double (operands));
"
......@@ -5240,7 +5239,7 @@
(define_insn "*ldmsi_postinc4"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 16)))
(set (match_operand:SI 3 "arm_hard_register_operand" "")
......@@ -5259,7 +5258,7 @@
(define_insn "*ldmsi_postinc3"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 12)))
(set (match_operand:SI 3 "arm_hard_register_operand" "")
......@@ -5276,7 +5275,7 @@
(define_insn "*ldmsi_postinc2"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 8)))
(set (match_operand:SI 3 "arm_hard_register_operand" "")
......@@ -5362,7 +5361,7 @@
(define_insn "*stmsi_postinc4"
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 16)))
(set (mem:SI (match_dup 2))
......@@ -5381,7 +5380,7 @@
(define_insn "*stmsi_postinc3"
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 12)))
(set (mem:SI (match_dup 2))
......@@ -5398,7 +5397,7 @@
(define_insn "*stmsi_postinc2"
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "=r")
[(set (match_operand:SI 1 "s_register_operand" "+r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 8)))
(set (mem:SI (match_dup 2))
......@@ -8615,7 +8614,8 @@
(match_operand:SI 1 "s_register_operand" ""))
(set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (const_int 0)))]
"TARGET_ARM"
"TARGET_ARM
"
[(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
(set (match_dup 0) (match_dup 1))])]
""
......
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