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riscv-gcc-1
Commit a95d4000 by Uros Bizjak
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sse.md (AVXMODEDCVTDQ2PS): Remove. 

	* config/i386/sse.md (AVXMODEDCVTDQ2PS): Remove.
	(AVXMODEDCVTPS2DQ): Ditto.
	(VEC_FLOAT_MODE): Ditto.
	(<sse>_andnot<mode>3): Merge with avx_andnot<mode>3.  Use VF mode
	iterator.  Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
	(<any_logic:code><mode>3): Use VF mode iterator.
	(*<any_logic:code><mode>3): Merge with *avx_<any_logic:code><mode>3.
	Use VF mode iterator.
	(copysign<mode>3): Use VF mode iterator.
	(*andnot<MODEF:mode>3): Merge with *avx_andnot<MODEF:mode>3.  Handle
	TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
	(*<any_logic:code><MODEF:mode>3): Merge with
	*avx_<any_logic:code><MODEF:mode>3.
	(sse_cvtsi2ss): Merge with *avx_cvtsi2ss.
	(sse_cvtsi2ssq): Merge with *avx_cvtsi2ssq.
	(avx_cvtdq2ps256): Split from avx_cvtdq2ps<avxmodesuffix>.
	(avx_cvtdq2ps<avxmodesuffix>): Remove.
	(sse2_cvtdq2ps): Use %v modifier.
	(avx_cvtps2dq256): Split from avx_cvtps2dq<avxmodesuffix>.
	(avx_cvtps2dq<avxmodesuffix>): Remove.
	(sse2_cvtps2dq): Use %v modifier.
	(avx_cvttps2dq256): Split from avx_cvttps2dq<avxmodesuffix>.
	(avx_cvttps2dq<avxmodesuffix>): Remove.
	(sse2_cvttps2dq): Use %v modifier.
	(sse2_cvtsi2sd): Merge with *avx_cvtsi2sd.
	(sse2_cvtsi2sdq): Merge with *avx_cvtsi2sdq.
	(sse2_cvtsd2siq): Fix insn template.
	(sse2_cvtsd2siq_2): Ditto.
	(sse2_cvttsd2siq): Ditto.
	(sse2_cvtsd2ss): Merge with *avx_cvtsd2ss.
	(sse2_cvtss2sd): Merge with *avx_cvtss2sd.

From-SVN: r172058
parent 4e927875
Showing with 332 additions and 329 deletions
gcc/ChangeLog
2011-04-06 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (AVXMODEDCVTDQ2PS): Remove.
(AVXMODEDCVTPS2DQ): Ditto.
(VEC_FLOAT_MODE): Ditto.
(<sse>_andnot<mode>3): Merge with avx_andnot<mode>3. Use VF mode
iterator. Handle TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
(<any_logic:code><mode>3): Use VF mode iterator.
(*<any_logic:code><mode>3): Merge with *avx_<any_logic:code><mode>3.
Use VF mode iterator.
(copysign<mode>3): Use VF mode iterator.
(*andnot<MODEF:mode>3): Merge with *avx_andnot<MODEF:mode>3. Handle
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL target flag.
(*<any_logic:code><MODEF:mode>3): Merge with
*avx_<any_logic:code><MODEF:mode>3.
(sse_cvtsi2ss): Merge with *avx_cvtsi2ss.
(sse_cvtsi2ssq): Merge with *avx_cvtsi2ssq.
(avx_cvtdq2ps256): Split from avx_cvtdq2ps<avxmodesuffix>.
(avx_cvtdq2ps<avxmodesuffix>): Remove.
(sse2_cvtdq2ps): Use %v modifier.
(avx_cvtps2dq256): Split from avx_cvtps2dq<avxmodesuffix>.
(avx_cvtps2dq<avxmodesuffix>): Remove.
(sse2_cvtps2dq): Use %v modifier.
(avx_cvttps2dq256): Split from avx_cvttps2dq<avxmodesuffix>.
(avx_cvttps2dq<avxmodesuffix>): Remove.
(sse2_cvttps2dq): Use %v modifier.
(sse2_cvtsi2sd): Merge with *avx_cvtsi2sd.
(sse2_cvtsi2sdq): Merge with *avx_cvtsi2sdq.
(sse2_cvtsd2siq): Fix insn template.
(sse2_cvtsd2siq_2): Ditto.
(sse2_cvttsd2siq): Ditto.
(sse2_cvtsd2ss): Merge with *avx_cvtsd2ss.
(sse2_cvtss2sd): Merge with *avx_cvtss2sd.
2011-04-06 Joseph Myers <joseph@codesourcery.com> 2011-04-06 Joseph Myers <joseph@codesourcery.com>
* gcov-io.c: Use GCC Runtime Library Exception. * gcov-io.c: Use GCC Runtime Library Exception.
...@@ -48,8 +82,7 @@ ...@@ -48,8 +82,7 @@
declare. declare.
* config/darwin.h (TARGET_OBJC_CONSTRUCT_STRING_OBJECT, * config/darwin.h (TARGET_OBJC_CONSTRUCT_STRING_OBJECT,
TARGET_STRING_OBJECT_REF_TYPE_P, TARGET_STRING_OBJECT_REF_TYPE_P,
TARGET_CHECK_STRING_OBJECT_FORMAT_ARG, TARGET_HAS_TARGETCM): TARGET_CHECK_STRING_OBJECT_FORMAT_ARG, TARGET_HAS_TARGETCM): Remove.
Remove.
* config/t-darwin (darwin-c.o): Update dependencies. * config/t-darwin (darwin-c.o): Update dependencies.
* system.h (TARGET_HAS_TARGETCM): Poison. * system.h (TARGET_HAS_TARGETCM): Poison.
* Makefile.in (TARGET_H): Update. * Makefile.in (TARGET_H): Update.
...@@ -57,8 +90,7 @@ ...@@ -57,8 +90,7 @@
(c-family/c-format.o, c-family/c-opts.o): Update dependencies. (c-family/c-format.o, c-family/c-opts.o): Update dependencies.
(default-c.o): New target. (default-c.o): New target.
(s-target-hooks-def-h): Pass "Target Hook" string to genhooks. (s-target-hooks-def-h): Pass "Target Hook" string to genhooks.
(c-family/c-target-hooks-def.h, s-c-target-hooks-def-h): New (c-family/c-target-hooks-def.h, s-c-target-hooks-def-h): New targets.
targets.
(s-tm-texi): Pass -d option to genhooks. Also test timestamp on (s-tm-texi): Pass -d option to genhooks. Also test timestamp on
c-target.def. c-target.def.
(build/genhooks.o): Update dependencies. (build/genhooks.o): Update dependencies.
......
gcc/config/i386/sse.md
...@@ -84,8 +84,6 @@ ...@@ -84,8 +84,6 @@
(define_mode_iterator AVXMODEF4P [V4SF V4DF]) (define_mode_iterator AVXMODEF4P [V4SF V4DF])
(define_mode_iterator AVXMODEFDP [V2DF V4DF]) (define_mode_iterator AVXMODEFDP [V2DF V4DF])
(define_mode_iterator AVXMODEFSP [V4SF V8SF]) (define_mode_iterator AVXMODEFSP [V4SF V8SF])
(define_mode_iterator AVXMODEDCVTDQ2PS [V4SF V8SF])
(define_mode_iterator AVXMODEDCVTPS2DQ [V4SI V8SI])
(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF]) (define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
...@@ -112,11 +110,6 @@ ...@@ -112,11 +110,6 @@
(V4SF "TARGET_SSE") (V4SF "TARGET_SSE")
(V4DF "TARGET_AVX") (V8SF "TARGET_AVX")]) (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
;; Modes handled by vector float patterns.
(define_mode_iterator VEC_FLOAT_MODE
[(V2DF "TARGET_SSE2") (V4SF "TARGET_SSE")
(V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
;; Modes handled by vector extract patterns. ;; Modes handled by vector extract patterns.
(define_mode_iterator VEC_EXTRACT_MODE (define_mode_iterator VEC_EXTRACT_MODE
[(V2DI "TARGET_SSE") (V4SI "TARGET_SSE") [(V2DI "TARGET_SSE") (V4SI "TARGET_SSE")
...@@ -1384,88 +1377,89 @@ ...@@ -1384,88 +1377,89 @@
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn "avx_andnot<mode>3"
[(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
(and:AVXMODEF2P
(not:AVXMODEF2P
(match_operand:AVXMODEF2P 1 "register_operand" "x"))
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
"vandn<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
(define_insn "<sse>_andnot<mode>3" (define_insn "<sse>_andnot<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:VF 0 "register_operand" "=x,x")
(and:SSEMODEF2P (and:VF
(not:SSEMODEF2P (not:VF
(match_operand:SSEMODEF2P 1 "register_operand" "0")) (match_operand:VF 1 "register_operand" "0,x"))
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" ""
"andn<ssemodesuffix>\t{%2, %0|%0, %2}" {
[(set_attr "type" "sselog") static char buf[32];
(set_attr "mode" "<MODE>")]) const char *insn;
const char *suffix
= TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
(define_expand "<code><mode>3" switch (which_alternative)
[(set (match_operand:AVX256MODEF2P 0 "register_operand" "") {
(any_logic:AVX256MODEF2P case 0:
(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "") insn = "andn%s\t{%%2, %%0|%%0, %%2}";
(match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))] break;
"AVX256_VEC_FLOAT_MODE_P (<MODE>mode)" case 1:
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
(define_insn "*avx_<code><mode>3" snprintf (buf, sizeof (buf), insn, suffix);
[(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") return buf;
(any_logic:AVXMODEF2P
(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
else
return "v<logic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}";
} }
[(set_attr "type" "sselog") [(set_attr "isa" "noavx,avx")
(set_attr "prefix" "vex") (set_attr "type" "sselog")
(set_attr "mode" "<avxvecmode>")]) (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
(define_expand "<code><mode>3" (define_expand "<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "") [(set (match_operand:VF 0 "register_operand" "")
(any_logic:SSEMODEF2P (any_logic:VF
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") (match_operand:VF 1 "nonimmediate_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] (match_operand:VF 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" ""
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<code><mode>3" (define_insn "*<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:VF 0 "register_operand" "=x,x")
(any_logic:SSEMODEF2P (any_logic:VF
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") (match_operand:VF 1 "nonimmediate_operand" "%0,x")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{ {
if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) static char buf[32];
return "<logic>ps\t{%2, %0|%0, %2}"; const char *insn;
else const char *suffix
return "<logic><ssemodesuffix>\t{%2, %0|%0, %2}"; = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
switch (which_alternative)
{
case 0:
insn = "<logic>%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
snprintf (buf, sizeof (buf), insn, suffix);
return buf;
} }
[(set_attr "type" "sselog") [(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_expand "copysign<mode>3" (define_expand "copysign<mode>3"
[(set (match_dup 4) [(set (match_dup 4)
(and:VEC_FLOAT_MODE (and:VF
(not:VEC_FLOAT_MODE (match_dup 3)) (not:VF (match_dup 3))
(match_operand:VEC_FLOAT_MODE 1 "nonimmediate_operand" ""))) (match_operand:VF 1 "nonimmediate_operand" "")))
(set (match_dup 5) (set (match_dup 5)
(and:VEC_FLOAT_MODE (match_dup 3) (and:VF (match_dup 3)
(match_operand:VEC_FLOAT_MODE 2 "nonimmediate_operand" ""))) (match_operand:VF 2 "nonimmediate_operand" "")))
(set (match_operand:VEC_FLOAT_MODE 0 "register_operand" "") (set (match_operand:VF 0 "register_operand" "")
(ior:VEC_FLOAT_MODE (match_dup 4) (match_dup 5)))] (ior:VF (match_dup 4) (match_dup 5)))]
"" ""
{ {
operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0); operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0);
...@@ -1479,58 +1473,69 @@ ...@@ -1479,58 +1473,69 @@
;; allocation lossage. These patterns do not allow memory operands ;; allocation lossage. These patterns do not allow memory operands
;; because the native instructions read the full 128-bits. ;; because the native instructions read the full 128-bits.
(define_insn "*avx_andnot<mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(and:MODEF
(not:MODEF
(match_operand:MODEF 1 "register_operand" "x"))
(match_operand:MODEF 2 "register_operand" "x")))]
"AVX_FLOAT_MODE_P (<MODE>mode)"
"vandnp<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssevecmode>")])
(define_insn "*andnot<mode>3" (define_insn "*andnot<mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x") [(set (match_operand:MODEF 0 "register_operand" "=x,x")
(and:MODEF (and:MODEF
(not:MODEF (not:MODEF
(match_operand:MODEF 1 "register_operand" "0")) (match_operand:MODEF 1 "register_operand" "0,x"))
(match_operand:MODEF 2 "register_operand" "x")))] (match_operand:MODEF 2 "register_operand" "x,x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)" "SSE_FLOAT_MODE_P (<MODE>mode)"
"andnp<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])
(define_insn "*avx_<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(any_logic:MODEF
(match_operand:MODEF 1 "register_operand" "x")
(match_operand:MODEF 2 "register_operand" "x")))]
"AVX_FLOAT_MODE_P (<MODE>mode)"
{ {
if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) static char buf[32];
return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"; const char *insn;
else const char *suffix
return "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"; = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "s" : "<ssemodefsuffix>";
switch (which_alternative)
{
case 0:
insn = "andnp%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
insn = "vandnp%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
snprintf (buf, sizeof (buf), insn, suffix);
return buf;
} }
[(set_attr "type" "sselog") [(set_attr "isa" "noavx,avx")
(set_attr "prefix" "vex") (set_attr "type" "sselog")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssevecmode>")]) (set_attr "mode" "<ssevecmode>")])
(define_insn "*<code><mode>3" (define_insn "*<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x") [(set (match_operand:MODEF 0 "register_operand" "=x,x")
(any_logic:MODEF (any_logic:MODEF
(match_operand:MODEF 1 "register_operand" "0") (match_operand:MODEF 1 "register_operand" "%0,x")
(match_operand:MODEF 2 "register_operand" "x")))] (match_operand:MODEF 2 "register_operand" "x,x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)" "SSE_FLOAT_MODE_P (<MODE>mode)"
{ {
if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) static char buf[32];
return "<logic>ps\t{%2, %0|%0, %2}"; const char *insn;
else const char *suffix
return "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}"; = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "s" : "<ssemodefsuffix>";
switch (which_alternative)
{
case 0:
insn = "<logic>p%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
insn = "v<logic>p%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
snprintf (buf, sizeof (buf), insn, suffix);
return buf;
} }
[(set_attr "type" "sselog") [(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssevecmode>")]) (set_attr "mode" "<ssevecmode>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
...@@ -1919,62 +1924,46 @@ ...@@ -1919,62 +1924,46 @@
(set_attr "prefix_rep" "0") (set_attr "prefix_rep" "0")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*avx_cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
(vec_duplicate:V4SF
(float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
(match_operand:V4SF 1 "register_operand" "x")
(const_int 1)))]
"TARGET_AVX"
"vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "vex")
(set_attr "mode" "SF")])
(define_insn "sse_cvtsi2ss" (define_insn "sse_cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x,x") [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_merge:V4SF (vec_merge:V4SF
(vec_duplicate:V4SF (vec_duplicate:V4SF
(float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m"))) (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
(match_operand:V4SF 1 "register_operand" "0,0") (match_operand:V4SF 1 "register_operand" "0,0,x")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE" "TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}" "@
[(set_attr "type" "sseicvt") cvtsi2ss\t{%2, %0|%0, %2}
(set_attr "athlon_decode" "vector,double") cvtsi2ss\t{%2, %0|%0, %2}
(set_attr "amdfam10_decode" "vector,double") vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
(set_attr "bdver1_decode" "double,direct") [(set_attr "isa" "noavx,noavx,avx")
(set_attr "mode" "SF")]) (set_attr "type" "sseicvt")
(set_attr "athlon_decode" "vector,double,*")
(define_insn "*avx_cvtsi2ssq" (set_attr "amdfam10_decode" "vector,double,*")
[(set (match_operand:V4SF 0 "register_operand" "=x") (set_attr "bdver1_decode" "double,direct,*")
(vec_merge:V4SF (set_attr "prefix" "orig,orig,vex")
(vec_duplicate:V4SF
(float:SF (match_operand:DI 2 "nonimmediate_operand" "rm")))
(match_operand:V4SF 1 "register_operand" "x")
(const_int 1)))]
"TARGET_AVX && TARGET_64BIT"
"vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseicvt")
(set_attr "length_vex" "4")
(set_attr "prefix" "vex")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "sse_cvtsi2ssq" (define_insn "sse_cvtsi2ssq"
[(set (match_operand:V4SF 0 "register_operand" "=x,x") [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_merge:V4SF (vec_merge:V4SF
(vec_duplicate:V4SF (vec_duplicate:V4SF
(float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm"))) (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
(match_operand:V4SF 1 "register_operand" "0,0") (match_operand:V4SF 1 "register_operand" "0,0,x")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE && TARGET_64BIT" "TARGET_SSE && TARGET_64BIT"
"cvtsi2ssq\t{%2, %0|%0, %2}" "@
[(set_attr "type" "sseicvt") cvtsi2ssq\t{%2, %0|%0, %2}
(set_attr "prefix_rex" "1") cvtsi2ssq\t{%2, %0|%0, %2}
(set_attr "athlon_decode" "vector,double") vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
(set_attr "amdfam10_decode" "vector,double") [(set_attr "isa" "noavx,noavx,avx")
(set_attr "bdver1_decode" "double,direct") (set_attr "type" "sseicvt")
(set_attr "athlon_decode" "vector,double,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
(set_attr "length_vex" "*,*,4")
(set_attr "prefix_rex" "1,1,*")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "sse_cvtss2si" (define_insn "sse_cvtss2si"
...@@ -2069,22 +2058,22 @@ ...@@ -2069,22 +2058,22 @@
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "avx_cvtdq2ps<avxmodesuffix>" (define_insn "avx_cvtdq2ps256"
[(set (match_operand:AVXMODEDCVTDQ2PS 0 "register_operand" "=x") [(set (match_operand:V8SF 0 "register_operand" "=x")
(float:AVXMODEDCVTDQ2PS (float:V8SF (match_operand:V8SI 1 "nonimmediate_operand" "xm")))]
(match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX" "TARGET_AVX"
"vcvtdq2ps\t{%1, %0|%0, %1}" "vcvtdq2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "vex") (set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")]) (set_attr "mode" "V8SF")])
(define_insn "sse2_cvtdq2ps" (define_insn "sse2_cvtdq2ps"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))] (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtdq2ps\t{%1, %0|%0, %1}" "%vcvtdq2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
(define_expand "sse2_cvtudq2ps" (define_expand "sse2_cvtudq2ps"
...@@ -2113,45 +2102,58 @@ ...@@ -2113,45 +2102,58 @@
operands[i] = gen_reg_rtx (V4SFmode); operands[i] = gen_reg_rtx (V4SFmode);
}) })
(define_insn "avx_cvtps2dq<avxmodesuffix>" (define_insn "avx_cvtps2dq256"
[(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x") [(set (match_operand:V8SI 0 "register_operand" "=x")
(unspec:AVXMODEDCVTPS2DQ (unspec:V8SI [(match_operand:V8SF 1 "nonimmediate_operand" "xm")]
[(match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC))] UNSPEC_FIX_NOTRUNC))]
"TARGET_AVX" "TARGET_AVX"
"vcvtps2dq\t{%1, %0|%0, %1}" "vcvtps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "vex") (set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")]) (set_attr "mode" "OI")])
(define_insn "sse2_cvtps2dq" (define_insn "sse2_cvtps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC))] UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtps2dq\t{%1, %0|%0, %1}" "%vcvtps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix_data16" "1") (set (attr "prefix_data16")
(if_then_else
(ne (symbol_ref "TARGET_AVX") (const_int 0))
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "avx_cvttps2dq<avxmodesuffix>" (define_insn "avx_cvttps2dq256"
[(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x") [(set (match_operand:V8SI 0 "register_operand" "=x")
(fix:AVXMODEDCVTPS2DQ (fix:V8SI (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
(match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX" "TARGET_AVX"
"vcvttps2dq\t{%1, %0|%0, %1}" "vcvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "vex") (set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")]) (set_attr "mode" "OI")])
(define_insn "sse2_cvttps2dq" (define_insn "sse2_cvttps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))] (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttps2dq\t{%1, %0|%0, %1}" "%vcvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix_rep" "1") (set (attr "prefix_rep")
(if_then_else
(ne (symbol_ref "TARGET_AVX") (const_int 0))
(const_string "*")
(const_string "1")))
(set (attr "prefix_data16")
(if_then_else
(ne (symbol_ref "TARGET_AVX") (const_int 0))
(const_string "*")
(const_string "0")))
(set_attr "prefix_data16" "0") (set_attr "prefix_data16" "0")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
...@@ -2178,9 +2180,9 @@ ...@@ -2178,9 +2180,9 @@
"cvtpd2pi\t{%1, %0|%0, %1}" "cvtpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "unit" "mmx") (set_attr "unit" "mmx")
(set_attr "bdver1_decode" "double")
(set_attr "prefix_data16" "1") (set_attr "prefix_data16" "1")
(set_attr "mode" "DI") (set_attr "mode" "DI")])
(set_attr "bdver1_decode" "double")])
(define_insn "sse2_cvttpd2pi" (define_insn "sse2_cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y") [(set (match_operand:V2SI 0 "register_operand" "=y")
...@@ -2189,67 +2191,51 @@ ...@@ -2189,67 +2191,51 @@
"cvttpd2pi\t{%1, %0|%0, %1}" "cvttpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "unit" "mmx") (set_attr "unit" "mmx")
(set_attr "bdver1_decode" "double")
(set_attr "prefix_data16" "1") (set_attr "prefix_data16" "1")
(set_attr "mode" "TI") (set_attr "mode" "TI")])
(set_attr "bdver1_decode" "double")])
(define_insn "*avx_cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_merge:V2DF
(vec_duplicate:V2DF
(float:DF (match_operand:SI 2 "nonimmediate_operand" "rm")))
(match_operand:V2DF 1 "register_operand" "x")
(const_int 1)))]
"TARGET_AVX"
"vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "vex")
(set_attr "mode" "DF")])
(define_insn "sse2_cvtsi2sd" (define_insn "sse2_cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x,x") [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
(vec_merge:V2DF (vec_merge:V2DF
(vec_duplicate:V2DF (vec_duplicate:V2DF
(float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m"))) (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
(match_operand:V2DF 1 "register_operand" "0,0") (match_operand:V2DF 1 "register_operand" "0,0,x")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsi2sd\t{%2, %0|%0, %2}" "@
[(set_attr "type" "sseicvt") cvtsi2sd\t{%2, %0|%0, %2}
(set_attr "mode" "DF") cvtsi2sd\t{%2, %0|%0, %2}
(set_attr "athlon_decode" "double,direct") vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
(set_attr "amdfam10_decode" "vector,double") [(set_attr "isa" "noavx,noavx,avx")
(set_attr "bdver1_decode" "double,direct")]) (set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,direct,*")
(define_insn "*avx_cvtsi2sdq" (set_attr "amdfam10_decode" "vector,double,*")
[(set (match_operand:V2DF 0 "register_operand" "=x") (set_attr "bdver1_decode" "double,direct,*")
(vec_merge:V2DF (set_attr "prefix" "orig,orig,vex")
(vec_duplicate:V2DF
(float:DF (match_operand:DI 2 "nonimmediate_operand" "rm")))
(match_operand:V2DF 1 "register_operand" "x")
(const_int 1)))]
"TARGET_AVX && TARGET_64BIT"
"vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseicvt")
(set_attr "length_vex" "4")
(set_attr "prefix" "vex")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
(define_insn "sse2_cvtsi2sdq" (define_insn "sse2_cvtsi2sdq"
[(set (match_operand:V2DF 0 "register_operand" "=x,x") [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
(vec_merge:V2DF (vec_merge:V2DF
(vec_duplicate:V2DF (vec_duplicate:V2DF
(float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m"))) (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
(match_operand:V2DF 1 "register_operand" "0,0") (match_operand:V2DF 1 "register_operand" "0,0,x")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE2 && TARGET_64BIT" "TARGET_SSE2 && TARGET_64BIT"
"cvtsi2sdq\t{%2, %0|%0, %2}" "@
[(set_attr "type" "sseicvt") cvtsi2sdq\t{%2, %0|%0, %2}
(set_attr "prefix_rex" "1") cvtsi2sdq\t{%2, %0|%0, %2}
(set_attr "mode" "DF") vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
(set_attr "athlon_decode" "double,direct") [(set_attr "isa" "noavx,noavx,avx")
(set_attr "amdfam10_decode" "vector,double") (set_attr "type" "sseicvt")
(set_attr "bdver1_decode" "double,direct")]) (set_attr "athlon_decode" "double,direct,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
(set_attr "length_vex" "*,*,4")
(set_attr "prefix_rex" "1,1,*")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "DF")])
(define_insn "sse2_cvtsd2si" (define_insn "sse2_cvtsd2si"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
...@@ -2289,7 +2275,7 @@ ...@@ -2289,7 +2275,7 @@
(parallel [(const_int 0)]))] (parallel [(const_int 0)]))]
UNSPEC_FIX_NOTRUNC))] UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2 && TARGET_64BIT" "TARGET_SSE2 && TARGET_64BIT"
"%vcvtsd2siq\t{%1, %0|%0, %1}" "%vcvtsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector") (set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double") (set_attr "bdver1_decode" "double,double")
...@@ -2302,7 +2288,7 @@ ...@@ -2302,7 +2288,7 @@
(unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")] (unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
UNSPEC_FIX_NOTRUNC))] UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2 && TARGET_64BIT" "TARGET_SSE2 && TARGET_64BIT"
"%vcvtsd2siq\t{%1, %0|%0, %1}" "%vcvtsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector") (set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double") (set_attr "amdfam10_decode" "double,double")
...@@ -2320,12 +2306,12 @@ ...@@ -2320,12 +2306,12 @@
"TARGET_SSE2" "TARGET_SSE2"
"%vcvttsd2si\t{%1, %0|%0, %1}" "%vcvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")
(set_attr "athlon_decode" "double,vector") (set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double") (set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")]) (set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
(define_insn "sse2_cvttsd2siq" (define_insn "sse2_cvttsd2siq"
[(set (match_operand:DI 0 "register_operand" "=r,r") [(set (match_operand:DI 0 "register_operand" "=r,r")
...@@ -2334,14 +2320,14 @@ ...@@ -2334,14 +2320,14 @@
(match_operand:V2DF 1 "nonimmediate_operand" "x,m") (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
(parallel [(const_int 0)]))))] (parallel [(const_int 0)]))))]
"TARGET_SSE2 && TARGET_64BIT" "TARGET_SSE2 && TARGET_64BIT"
"%vcvttsd2siq\t{%1, %0|%0, %1}" "%vcvttsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt") [(set_attr "type" "sseicvt")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")
(set_attr "athlon_decode" "double,vector") (set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double") (set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")]) (set_attr "bdver1_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
(define_insn "avx_cvtdq2pd256" (define_insn "avx_cvtdq2pd256"
[(set (match_operand:V4DF 0 "register_operand" "=x") [(set (match_operand:V4DF 0 "register_operand" "=x")
...@@ -2357,7 +2343,8 @@ ...@@ -2357,7 +2343,8 @@
(float:V4DF (float:V4DF
(vec_select:V4SI (vec_select:V4SI
(match_operand:V8SI 1 "nonimmediate_operand" "xm") (match_operand:V8SI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] (parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX" "TARGET_AVX"
"vcvtdq2pd\t{%x1, %0|%0, %x1}" "vcvtdq2pd\t{%x1, %0|%0, %x1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -2402,8 +2389,12 @@ ...@@ -2402,8 +2389,12 @@
UNSPEC_FIX_NOTRUNC) UNSPEC_FIX_NOTRUNC)
(match_operand:V2SI 2 "const0_operand" "")))] (match_operand:V2SI 2 "const0_operand" "")))]
"TARGET_SSE2" "TARGET_SSE2"
"* return TARGET_AVX ? \"vcvtpd2dq{x}\t{%1, %0|%0, %1}\" {
: \"cvtpd2dq\t{%1, %0|%0, %1}\";" if (TARGET_AVX)
return "vcvtpd2dq{x}\t{%1, %0|%0, %1}";
else
return "cvtpd2dq\t{%1, %0|%0, %1}";
}
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix_rep" "1") (set_attr "prefix_rep" "1")
(set_attr "prefix_data16" "0") (set_attr "prefix_data16" "0")
...@@ -2436,75 +2427,60 @@ ...@@ -2436,75 +2427,60 @@
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")) (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
(match_operand:V2SI 2 "const0_operand" "")))] (match_operand:V2SI 2 "const0_operand" "")))]
"TARGET_SSE2" "TARGET_SSE2"
"* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\" {
: \"cvttpd2dq\t{%1, %0|%0, %1}\";" if (TARGET_AVX)
return "vcvttpd2dq{x}\t{%1, %0|%0, %1}";
else
return "cvttpd2dq\t{%1, %0|%0, %1}";
}
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double") (set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector") (set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")]) (set_attr "bdver1_decode" "double")
(set_attr "prefix" "maybe_vex")
(define_insn "*avx_cvtsd2ss" (set_attr "mode" "TI")])
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
(vec_duplicate:V4SF
(float_truncate:V2SF
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))
(match_operand:V4SF 1 "register_operand" "x")
(const_int 1)))]
"TARGET_AVX"
"vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
(set_attr "mode" "SF")])
(define_insn "sse2_cvtsd2ss" (define_insn "sse2_cvtsd2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x,x") [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_merge:V4SF (vec_merge:V4SF
(vec_duplicate:V4SF (vec_duplicate:V4SF
(float_truncate:V2SF (float_truncate:V2SF
(match_operand:V2DF 2 "nonimmediate_operand" "x,m"))) (match_operand:V2DF 2 "nonimmediate_operand" "x,m,xm")))
(match_operand:V4SF 1 "register_operand" "0,0") (match_operand:V4SF 1 "register_operand" "0,0,x")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsd2ss\t{%2, %0|%0, %2}" "@
[(set_attr "type" "ssecvt") cvtsd2ss\t{%2, %0|%0, %2}
(set_attr "athlon_decode" "vector,double") cvtsd2ss\t{%2, %0|%0, %2}
(set_attr "amdfam10_decode" "vector,double") vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
(set_attr "bdver1_decode" "direct,direct") [(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssecvt")
(set_attr "athlon_decode" "vector,double,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "direct,direct,*")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*avx_cvtss2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_merge:V2DF
(float_extend:V2DF
(vec_select:V2SF
(match_operand:V4SF 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 1)])))
(match_operand:V2DF 1 "register_operand" "x")
(const_int 1)))]
"TARGET_AVX"
"vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
(set_attr "mode" "DF")])
(define_insn "sse2_cvtss2sd" (define_insn "sse2_cvtss2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x,x") [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
(vec_merge:V2DF (vec_merge:V2DF
(float_extend:V2DF (float_extend:V2DF
(vec_select:V2SF (vec_select:V2SF
(match_operand:V4SF 2 "nonimmediate_operand" "x,m") (match_operand:V4SF 2 "nonimmediate_operand" "x,m,xm")
(parallel [(const_int 0) (const_int 1)]))) (parallel [(const_int 0) (const_int 1)])))
(match_operand:V2DF 1 "register_operand" "0,0") (match_operand:V2DF 1 "register_operand" "0,0,x")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtss2sd\t{%2, %0|%0, %2}" "@
[(set_attr "type" "ssecvt") cvtss2sd\t{%2, %0|%0, %2}
(set_attr "amdfam10_decode" "vector,double") cvtss2sd\t{%2, %0|%0, %2}
(set_attr "athlon_decode" "direct,direct") vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
(set_attr "bdver1_decode" "direct,direct") [(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssecvt")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "athlon_decode" "direct,direct,*")
(set_attr "bdver1_decode" "direct,direct,*")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
(define_insn "avx_cvtpd2ps256" (define_insn "avx_cvtpd2ps256"
...@@ -2533,15 +2509,19 @@ ...@@ -2533,15 +2509,19 @@
(match_operand:V2DF 1 "nonimmediate_operand" "xm")) (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
(match_operand:V2SF 2 "const0_operand" "")))] (match_operand:V2SF 2 "const0_operand" "")))]
"TARGET_SSE2" "TARGET_SSE2"
"* return TARGET_AVX ? \"vcvtpd2ps{x}\t{%1, %0|%0, %1}\" {
: \"cvtpd2ps\t{%1, %0|%0, %1}\";" if (TARGET_AVX)
return "vcvtpd2ps{x}\t{%1, %0|%0, %1}";
else
return "cvtpd2ps\t{%1, %0|%0, %1}";
}
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix_data16" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")
(set_attr "amdfam10_decode" "double") (set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector") (set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")]) (set_attr "bdver1_decode" "double")
(set_attr "prefix_data16" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")])
(define_insn "avx_cvtps2pd256" (define_insn "avx_cvtps2pd256"
[(set (match_operand:V4DF 0 "register_operand" "=x") [(set (match_operand:V4DF 0 "register_operand" "=x")
...@@ -2558,7 +2538,8 @@ ...@@ -2558,7 +2538,8 @@
(float_extend:V4DF (float_extend:V4DF
(vec_select:V4SF (vec_select:V4SF
(match_operand:V8SF 1 "nonimmediate_operand" "xm") (match_operand:V8SF 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] (parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX" "TARGET_AVX"
"vcvtps2pd\t{%x1, %0|%0, %x1}" "vcvtps2pd\t{%x1, %0|%0, %x1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -2574,12 +2555,12 @@ ...@@ -2574,12 +2555,12 @@
"TARGET_SSE2" "TARGET_SSE2"
"%vcvtps2pd\t{%1, %0|%0, %1}" "%vcvtps2pd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V2DF")
(set_attr "prefix_data16" "0")
(set_attr "amdfam10_decode" "direct") (set_attr "amdfam10_decode" "direct")
(set_attr "athlon_decode" "double") (set_attr "athlon_decode" "double")
(set_attr "bdver1_decode" "double")]) (set_attr "bdver1_decode" "double")
(set_attr "prefix_data16" "0")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V2DF")])
(define_expand "vec_unpacks_hi_v4sf" (define_expand "vec_unpacks_hi_v4sf"
[(set (match_dup 2) [(set (match_dup 2)
...@@ -2587,10 +2568,8 @@ ...@@ -2587,10 +2568,8 @@
(vec_concat:V8SF (vec_concat:V8SF
(match_dup 2) (match_dup 2)
(match_operand:V4SF 1 "nonimmediate_operand" "")) (match_operand:V4SF 1 "nonimmediate_operand" ""))
(parallel [(const_int 6) (parallel [(const_int 6) (const_int 7)
(const_int 7) (const_int 2) (const_int 3)])))
(const_int 2)
(const_int 3)])))
(set (match_operand:V2DF 0 "register_operand" "") (set (match_operand:V2DF 0 "register_operand" "")
(float_extend:V2DF (float_extend:V2DF
(vec_select:V2SF (vec_select:V2SF
...@@ -2603,17 +2582,13 @@ ...@@ -2603,17 +2582,13 @@
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V4SF (vec_select:V4SF
(match_operand:V8SF 1 "nonimmediate_operand" "") (match_operand:V8SF 1 "nonimmediate_operand" "")
(parallel [(const_int 4) (parallel [(const_int 4) (const_int 5)
(const_int 5) (const_int 6) (const_int 7)])))
(const_int 6)
(const_int 7)])))
(set (match_operand:V4DF 0 "register_operand" "") (set (match_operand:V4DF 0 "register_operand" "")
(float_extend:V4DF (float_extend:V4DF
(match_dup 2)))] (match_dup 2)))]
"TARGET_AVX" "TARGET_AVX"
{ "operands[2] = gen_reg_rtx (V4SFmode);")
operands[2] = gen_reg_rtx (V4SFmode);
})
(define_expand "vec_unpacks_lo_v4sf" (define_expand "vec_unpacks_lo_v4sf"
[(set (match_operand:V2DF 0 "register_operand" "") [(set (match_operand:V2DF 0 "register_operand" "")
...@@ -2628,7 +2603,8 @@ ...@@ -2628,7 +2603,8 @@
(float_extend:V4DF (float_extend:V4DF
(vec_select:V4SF (vec_select:V4SF
(match_operand:V8SF 1 "nonimmediate_operand" "") (match_operand:V8SF 1 "nonimmediate_operand" "")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] (parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX") "TARGET_AVX")
(define_expand "vec_unpacks_float_hi_v8hi" (define_expand "vec_unpacks_float_hi_v8hi"
...@@ -2683,10 +2659,8 @@ ...@@ -2683,10 +2659,8 @@
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V4SI (vec_select:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "") (match_operand:V4SI 1 "nonimmediate_operand" "")
(parallel [(const_int 2) (parallel [(const_int 2) (const_int 3)
(const_int 3) (const_int 2) (const_int 3)])))
(const_int 2)
(const_int 3)])))
(set (match_operand:V2DF 0 "register_operand" "") (set (match_operand:V2DF 0 "register_operand" "")
(float:V2DF (float:V2DF
(vec_select:V2SI (vec_select:V2SI
...@@ -2707,10 +2681,8 @@ ...@@ -2707,10 +2681,8 @@
[(set (match_dup 2) [(set (match_dup 2)
(vec_select:V4SI (vec_select:V4SI
(match_operand:V8SI 1 "nonimmediate_operand" "") (match_operand:V8SI 1 "nonimmediate_operand" "")
(parallel [(const_int 4) (parallel [(const_int 4) (const_int 5)
(const_int 5) (const_int 6) (const_int 7)])))
(const_int 6)
(const_int 7)])))
(set (match_operand:V4DF 0 "register_operand" "") (set (match_operand:V4DF 0 "register_operand" "")
(float:V4DF (float:V4DF
(match_dup 2)))] (match_dup 2)))]
...@@ -2722,17 +2694,16 @@ ...@@ -2722,17 +2694,16 @@
(float:V4DF (float:V4DF
(vec_select:V4SI (vec_select:V4SI
(match_operand:V8SI 1 "nonimmediate_operand" "") (match_operand:V8SI 1 "nonimmediate_operand" "")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] (parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX") "TARGET_AVX")
(define_expand "vec_unpacku_float_hi_v4si" (define_expand "vec_unpacku_float_hi_v4si"
[(set (match_dup 5) [(set (match_dup 5)
(vec_select:V4SI (vec_select:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "") (match_operand:V4SI 1 "nonimmediate_operand" "")
(parallel [(const_int 2) (parallel [(const_int 2) (const_int 3)
(const_int 3) (const_int 2) (const_int 3)])))
(const_int 2)
(const_int 3)])))
(set (match_dup 6) (set (match_dup 6)
(float:V2DF (float:V2DF
(vec_select:V2SI (vec_select:V2SI
......
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