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riscv-gcc-1
Commit a94a76a7 by Ulrich Weigand Committed by Andreas Krebbel
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s390.c (s390_expand_addcc): Emit canonical alc pattern. 

2007-08-30  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>

	* config/s390/s390.c (s390_expand_addcc): Emit canonical alc
	pattern.
	* config/s390/s390.md ("*add<mode>3_alc_cc", "*add<mode>3_alc",
	"addti3", "*adddi3_31z", "*scond<mode>"): Make alc pattern canonical.

From-SVN: r127920
parent e3c58a3a
Showing with 23 additions and 14 deletions
gcc/ChangeLog
2007-08-30 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/s390/s390.c (s390_expand_addcc): Emit canonical alc
pattern.
* config/s390/s390.md ("*add<mode>3_alc_cc", "*add<mode>3_alc",
"addti3", "*adddi3_31z", "*scond<mode>"): Make alc pattern canonical.
2007-08-29 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* system.h: Activate -Wcast-qual as warning-only.
......
gcc/config/s390/s390.c
......@@ -3927,8 +3927,8 @@ s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
if (!register_operand (src, GET_MODE (dst)))
src = force_reg (GET_MODE (dst), src);
src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
}
p = rtvec_alloc (2);
......
gcc/config/s390/s390.md
......@@ -3635,8 +3635,9 @@
(match_dup 7)))
(set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
(ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
[(set (match_dup 3) (plus:DI
(plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
(match_dup 4)) (match_dup 5)))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
......@@ -3719,8 +3720,9 @@
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
(ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
[(set (match_dup 3) (plus:SI
(plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
(match_dup 4)) (match_dup 5)))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
......@@ -4308,12 +4310,12 @@
(define_insn "*add<mode>3_alc_cc"
[(set (reg CC_REGNUM)
(compare
(plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,m"))
(match_operand:GPR 3 "s390_alc_comparison" ""))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
alc<g>r\t%0,%2
......@@ -4323,9 +4325,9 @@
; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
(match_operand:GPR 2 "general_operand" "d,m"))
(match_operand:GPR 3 "s390_alc_comparison" "")))
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,m")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
......@@ -4386,8 +4388,8 @@
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
[(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
(match_dup 1)))
[(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
(match_dup 0)))
(clobber (reg:CC CC_REGNUM))])]
"")
......
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