Commit a8e17e9e by Paul Brook Committed by Paul Brook

vfp.md: Document fmul{s,d} and fmac{s,d} types.

2008-08-28  Paul Brook  <paul@codesourcery.com>

	* config/arm/vfp.md: Document fmul{s,d} and fmac{s,d} types.
	Remove documentation entry for fmul type.
	Use fmuls to annotate single-precision multiplication patterns,
	fmuld to annotate double-precision multiplication patterns,
	fmacs to annotate single-precision multiply-accumulate patterns
	and fmacd to annotate double-precision multiply-accumulate patterns.
	* config/arm/vfp11.md: Update reservations accordingly.
	* config/arm/arm.md: Note that certain values of the "type"
	attribute are documented in vfp.md.
	* config/arm/arm1020e.md: Remove out of date duplicate comment.
	(v10_cvt): Use new fmul types.

From-SVN: r139604
parent f08d75a9
2008-08-28 Paul Brook <paul@codesourcery.com>
* config/arm/vfp.md: Document fmul{s,d} and fmac{s,d} types.
Remove documentation entry for fmul type.
Use fmuls to annotate single-precision multiplication patterns,
fmuld to annotate double-precision multiplication patterns,
fmacs to annotate single-precision multiply-accumulate patterns
and fmacd to annotate double-precision multiply-accumulate patterns.
* config/arm/vfp11.md: Update reservations accordingly.
* config/arm/arm.md: Note that certain values of the "type"
attribute are documented in vfp.md.
* config/arm/arm1020e.md: Remove out of date duplicate comment.
(v10_cvt): Use new fmul types.
2008-08-26 Paul Brook <paul@codesourcery.com>
* config/arm/vfp.md: Move pipeline description for VFP11 to...
......
......@@ -193,6 +193,8 @@
; scheduling of writes.
; Classification of each insn
; Note: vfp.md has different meanings for some of these, and some further
; types as well. See that file for details.
; alu any alu instruction that doesn't hit memory or fp
; regs or have a shifted source operand
; alu_shift any data instruction that doesn't hit memory or fp
......
......@@ -265,18 +265,6 @@
(eq_attr "fpu" "vfp"))
(const_string "yes") (const_string "no"))))
;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
;; farith Most arithmetic insns.
;; fmul Double precision multiply.
;; fdivs Single precision sqrt or division.
;; fdivd Double precision sqrt or division.
;; f_flag fmstat operation
;; f_load Floating point load from memory.
;; f_store Floating point store to memory.
;; f_2_r Transfer vfp to arm reg.
;; r_2_f Transfer arm to vfp reg.
;; Note, no instruction can issue to the VFP if the core is stalled in the
;; first execute state. We model this by using 1020a_e in the first cycle.
(define_insn_reservation "v10_ffarith" 5
......@@ -296,7 +284,7 @@
(define_insn_reservation "v10_fmul" 6
(and (eq_attr "vfp10" "yes")
(eq_attr "type" "fmul"))
(eq_attr "type" "fmuls,fmacs,fmuld,fmacd"))
"1020a_e+v10_fmac*2")
(define_insn_reservation "v10_fdivs" 18
......
......@@ -26,7 +26,10 @@
;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
;; farith Most arithmetic insns.
;; fmul Double precision multiply.
;; fmuls Single precision multiply.
;; fmuld Double precision multiply.
;; fmacs Single precision multiply-accumulate.
;; fmacd Double precision multiply-accumulate.
;; fdivs Single precision sqrt or division.
;; fdivd Double precision sqrt or division.
;; f_flag fmstat operation
......@@ -573,7 +576,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmuls%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "fmuls")]
)
(define_insn "*muldf3_vfp"
......@@ -583,7 +586,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmuld%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "type" "fmul")]
(set_attr "type" "fmuld")]
)
......@@ -594,7 +597,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmuls%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "fmuls")]
)
(define_insn "*muldf3negdf_vfp"
......@@ -604,7 +607,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmuld%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "type" "fmul")]
(set_attr "type" "fmuld")]
)
......@@ -619,7 +622,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmacs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "fmacs")]
)
(define_insn "*muldf3adddf_vfp"
......@@ -630,7 +633,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmacd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "type" "fmul")]
(set_attr "type" "fmacd")]
)
;; 0 = 1 * 2 - 0
......@@ -642,7 +645,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmscs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "fmacs")]
)
(define_insn "*muldf3subdf_vfp"
......@@ -653,7 +656,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmscd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "type" "fmul")]
(set_attr "type" "fmacd")]
)
;; 0 = -(1 * 2) + 0
......@@ -665,7 +668,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmacs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "fmacs")]
)
(define_insn "*fmuldf3negdfadddf_vfp"
......@@ -676,7 +679,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmacd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "type" "fmul")]
(set_attr "type" "fmacd")]
)
......@@ -690,7 +693,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmscs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "type" "farith")]
(set_attr "type" "fmacs")]
)
(define_insn "*muldf3negdfsubdf_vfp"
......@@ -702,7 +705,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmscd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "type" "fmul")]
(set_attr "type" "fmacd")]
)
......
......@@ -57,12 +57,12 @@
(define_insn_reservation "vfp_farith" 8
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "farith,f_cvt"))
(eq_attr "type" "farith,f_cvt,fmuls,fmacs"))
"fmac")
(define_insn_reservation "vfp_fmul" 9
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fmul"))
(eq_attr "type" "fmuld,fmacd"))
"fmac*2")
(define_insn_reservation "vfp_fdivs" 19
......
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