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Commit a8cdbec0 by Richard Sandiford Committed by Richard Sandiford
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* config/mips/sr71k.md, config/mips/7000.md: Reformat. 

From-SVN: r99591
parent f8535b4d
Showing with 50 additions and 68 deletions
gcc/ChangeLog
2005-05-11 Richard Sandiford <rsandifo@redhat.com>
* config/mips/sr71k.md, config/mips/7000.md: Reformat.
2005-05-11 Kazu Hirata <kazu@cs.umass.edu>
PR tree-optimizer/18472
......
gcc/config/mips/7000.md
......@@ -91,20 +91,24 @@
(eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
"rm7_iaddsub")
(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_ld" 2
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "load,fpload,fpidxload"))
"rm7_imem")
(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_st" 1
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "store,fpstore,fpidxstore"))
"rm7_imem")
(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_idiv_si" 36
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
"rm7_impydiv+(rm7_impydiv_iter*36)")
(define_insn_reservation "rm7_idiv_di" 68 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_idiv_di" 68
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*68)")
......@@ -124,7 +128,8 @@
(not (match_operand 0 "hilo_operand")))))
"rm7_impydiv")
(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_impy_di" 9
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*8)")
......@@ -141,11 +146,13 @@
"rm7_impydiv")
;; Move to/from fp coprocessor.
(define_insn_reservation "rm7_ixfer" 2 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_ixfer" 2
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "xfer"))
"rm7_iaddsub")
(define_insn_reservation "rm7_ibr" 3 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_ibr" 3
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "branch,jump,call"))
"rm7_branch")
......@@ -204,6 +211,7 @@
"rm7_fpmpy+(rm7_fpmpy_iter*2)")
;; Force single-dispatch for unknown or multi.
(define_insn_reservation "rm7_unknown" 1 (and (eq_attr "cpu" "r7000")
(define_insn_reservation "rm7_unknown" 1
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "unknown,multi"))
"rm7_single_dispatch")
gcc/config/mips/sr71k.md
......@@ -124,28 +124,24 @@
;;
(define_insn_reservation "ir_sr70_unknown"
1
(define_insn_reservation "ir_sr70_unknown" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "unknown"))
"serial_dispatch")
;; Assume prediction fails.
(define_insn_reservation "ir_sr70_branch"
6
(define_insn_reservation "ir_sr70_branch" 6
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "branch,jump,call"))
"ri_branch")
(define_insn_reservation "ir_sr70_load"
2
(define_insn_reservation "ir_sr70_load" 2
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "load"))
"ri_mem")
(define_insn_reservation "ir_sr70_store"
1
(define_insn_reservation "ir_sr70_store" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "store"))
"ri_mem")
......@@ -154,14 +150,12 @@
;;
;; float loads/stores flow through both cpu and cp1...
;;
(define_insn_reservation "ir_sr70_fload"
9
(define_insn_reservation "ir_sr70_fload" 9
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "fpload,fpidxload"))
"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
(define_insn_reservation "ir_sr70_fstore"
1
(define_insn_reservation "ir_sr70_fstore" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "fpstore,fpidxstore"))
"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
......@@ -169,8 +163,7 @@
;; This reservation is for conditional move based on integer
;; or floating point CC.
(define_insn_reservation "ir_sr70_condmove"
4
(define_insn_reservation "ir_sr70_condmove" 4
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "condmove"))
"ri_insns")
......@@ -178,43 +171,37 @@
;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
;; are different. Like float load/store, these insns use multiple
;; resources simultaneously
(define_insn_reservation "ir_sr70_xfer_from"
6
(define_insn_reservation "ir_sr70_xfer_from" 6
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "xfer")
(eq_attr "mode" "!SF,DF,FPSW")))
"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
(define_insn_reservation "ir_sr70_xfer_to"
9
(define_insn_reservation "ir_sr70_xfer_to" 9
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "xfer")
(eq_attr "mode" "SF,DF")))
"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
(define_insn_reservation "ir_sr70_hilo"
1
(define_insn_reservation "ir_sr70_hilo" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "mthilo,mfhilo"))
"ri_insns")
(define_insn_reservation "ir_sr70_arith"
1
(define_insn_reservation "ir_sr70_arith" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "arith,shift,slt,clz,const,trap"))
"ri_insns")
;; emulate repeat (dispatch stall) by spending extra cycle(s) in
;; in iter unit
(define_insn_reservation "ir_sr70_imul_si"
4
(define_insn_reservation "ir_sr70_imul_si" 4
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"ri_alux,ipu_alux,ipu_macc_iter")
(define_insn_reservation "ir_sr70_imul_di"
6
(define_insn_reservation "ir_sr70_imul_di" 6
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
......@@ -222,30 +209,26 @@
;; Divide algorithm is early out with best latency of 7 pcycles.
;; Use worst case for scheduling purposes.
(define_insn_reservation "ir_sr70_idiv_si"
41
(define_insn_reservation "ir_sr70_idiv_si" 41
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
"ri_alux,ipu_alux,(ipu_macc_iter*38)")
(define_insn_reservation "ir_sr70_idiv_di"
73
(define_insn_reservation "ir_sr70_idiv_di" 73
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"ri_alux,ipu_alux,(ipu_macc_iter*70)")
;; extra reservations of fpu_fpu are for repeat latency
(define_insn_reservation "ir_sr70_fadd_sf"
8
(define_insn_reservation "ir_sr70_fadd_sf" 8
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fadd")
(eq_attr "mode" "SF")))
"rf_insn,fpu_fpu")
(define_insn_reservation "ir_sr70_fadd_df"
10
(define_insn_reservation "ir_sr70_fadd_df" 10
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fadd")
(eq_attr "mode" "DF")))
......@@ -253,8 +236,7 @@
;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
;; with the sub or add.
(define_insn_reservation "ir_sr70_fmul_sf"
8
(define_insn_reservation "ir_sr70_fmul_sf" 8
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
......@@ -262,8 +244,7 @@
;; tie up the fpu unit to emulate the balance for the "repeat
;; rate" of 8 (2 are spent in the iss unit)
(define_insn_reservation "ir_sr70_fmul_df"
16
(define_insn_reservation "ir_sr70_fmul_df" 16
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
......@@ -275,28 +256,24 @@
;; 28 -- only way to fix this is to introduce new insn attrs.
;; cycles spent in iter unit are designed to satisfy balance
;; of "repeat" latency after insn uses up rf_multi1 reservation
(define_insn_reservation "ir_sr70_fdiv_sf"
60
(define_insn_reservation "ir_sr70_fdiv_sf" 60
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fdiv,frdiv")
(eq_attr "mode" "SF")))
"rf_multi1+(fpu_iter*51)")
(define_insn_reservation "ir_sr70_fdiv_df"
120
(define_insn_reservation "ir_sr70_fdiv_df" 120
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fdiv,frdiv")
(eq_attr "mode" "DF")))
"rf_multi1+(fpu_iter*109)")
(define_insn_reservation "ir_sr70_fabs"
4
(define_insn_reservation "ir_sr70_fabs" 4
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "fabs,fneg,fmove"))
"rf_insn,fpu_fpu")
(define_insn_reservation "ir_sr70_fcmp"
10
(define_insn_reservation "ir_sr70_fcmp" 10
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "fcmp"))
"rf_insn,fpu_fpu")
......@@ -304,48 +281,41 @@
;; "fcvt" type attribute covers a number of diff insns, most have the same
;; latency descriptions, a few vary. We use the
;; most common timing (which is also worst case).
(define_insn_reservation "ir_sr70_fcvt"
12
(define_insn_reservation "ir_sr70_fcvt" 12
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "fcvt"))
"rf_insn,fpu_fpu*4")
(define_insn_reservation "ir_sr70_fsqrt_sf"
62
(define_insn_reservation "ir_sr70_fsqrt_sf" 62
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fsqrt")
(eq_attr "mode" "SF")))
"rf_multi1+(fpu_iter*53)")
(define_insn_reservation "ir_sr70_fsqrt_df"
122
(define_insn_reservation "ir_sr70_fsqrt_df" 122
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "fsqrt")
(eq_attr "mode" "DF")))
"rf_multi1+(fpu_iter*111)")
(define_insn_reservation "ir_sr70_frsqrt_sf"
48
(define_insn_reservation "ir_sr70_frsqrt_sf" 48
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
"rf_multi1+(fpu_iter*39)")
(define_insn_reservation "ir_sr70_frsqrt_df"
240
(define_insn_reservation "ir_sr70_frsqrt_df" 240
(and (eq_attr "cpu" "sr71000")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"rf_multi1+(fpu_iter*229)")
(define_insn_reservation "ir_sr70_multi"
1
(define_insn_reservation "ir_sr70_multi" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "multi"))
"serial_dispatch")
(define_insn_reservation "ir_sr70_nop"
1
(define_insn_reservation "ir_sr70_nop" 1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "nop"))
"ri_insns")
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