mips-protos.h (mips_output_conditional_branch): Change interface.

	* config/mips/mips-protos.h (mips_output_conditional_branch): Change
	interface.
	(mips_output_order_conditional_branch): Declare.
	* config/mips/mips.h (MIPS_BRANCH): New macro.
	* config/mips/mips.c (gen_conditional_branch): Use VOIDmode
	for the comparison.  Use gen_condjump.
	(mips_output_conditional_branch): Rework interface to take the
	asm templates for a direct branch and the inverse of a direct branch.
	(mips_output_order_conditional_branch): New function.
	(mips_builtin_branch_and_move): New function.
	(mips_expand_builtin_compare): Use it.  Use VOIDmode for the
	branch condition.  Use gen_single_cc as the condition for
	__builtin_mips_upper_* or __builtin_mips_lower_*.
	(mips_expand_builtin_bposge): Use mips_builtin_branch_and_move.
	Use VOIDmode for the branch condition.
	* config/mips/predicates.md (order_operator): New predicate.
	* config/mips/mips.md (UNSPEC_SINGLE_CC): New constant.
	(branch_fp): Rename to...
	(*branch_fp): ...this.  Remove mode from comparison operator.
	Use new mips_output_conditional_branch interface.
	(branch_fp_inverted): Rename to...
	(*branch_fp_inverted): ...this and update as for *branch_fp.
	(*branch_zero<mode>): Rename to...
	(*branch_order<mode>): ...this.  Remove mode from comparison operator.
	Use mips_output_order_conditional_branch.  Only accept ordered
	comparisons.  
	(*branch_zero<mode>_inverted): Rename to...
	(*branch_order<mode>_inverted): ...this and update as for
	*branch_order<mode>.
	(*branch_equality<mode>): Accept zero as the second operand to
	the equality operator.  Use the new mips_output_conditional_branch
	interface.
	(*branch_equality<mode>_inverted): Likewise.
	(condjump): New expander.
	* config/mips/mips-dsp.md (mips_bposge): Remove mode from comparison
	operator.
	* config/mips/mips-ps-3d.md (bc1any4t, bc1any4f): Likewise.
	(bc1any2t, bc1any2f): Likewise.
	(single_cc): New expander.
	(*branch_upper_lower, *branch_upper_lower_inverted): New patterns.

From-SVN: r111909

gcc/ChangeLog

 2006-03-09  Richard Sandiford  <richard@codesourcery.com>
 
+	* config/mips/mips-protos.h (mips_output_conditional_branch): Change
+	interface.
+	(mips_output_order_conditional_branch): Declare.
+	* config/mips/mips.h (MIPS_BRANCH): New macro.
+	* config/mips/mips.c (gen_conditional_branch): Use VOIDmode
+	for the comparison.  Use gen_condjump.
+	(mips_output_conditional_branch): Rework interface to take the
+	asm templates for a direct branch and the inverse of a direct branch.
+	(mips_output_order_conditional_branch): New function.
+	(mips_builtin_branch_and_move): New function.
+	(mips_expand_builtin_compare): Use it.  Use VOIDmode for the
+	branch condition.  Use gen_single_cc as the condition for
+	__builtin_mips_upper_* or __builtin_mips_lower_*.
+	(mips_expand_builtin_bposge): Use mips_builtin_branch_and_move.
+	Use VOIDmode for the branch condition.
+	* config/mips/predicates.md (order_operator): New predicate.
+	* config/mips/mips.md (UNSPEC_SINGLE_CC): New constant.
+	(branch_fp): Rename to...
+	(*branch_fp): ...this.  Remove mode from comparison operator.
+	Use new mips_output_conditional_branch interface.
+	(branch_fp_inverted): Rename to...
+	(*branch_fp_inverted): ...this and update as for *branch_fp.
+	(*branch_zero<mode>): Rename to...
+	(*branch_order<mode>): ...this.  Remove mode from comparison operator.
+	Use mips_output_order_conditional_branch.  Only accept ordered
+	comparisons.  
+	(*branch_zero<mode>_inverted): Rename to...
+	(*branch_order<mode>_inverted): ...this and update as for
+	*branch_order<mode>.
+	(*branch_equality<mode>): Accept zero as the second operand to
+	the equality operator.  Use the new mips_output_conditional_branch
+	interface.
+	(*branch_equality<mode>_inverted): Likewise.
+	(condjump): New expander.
+	* config/mips/mips-dsp.md (mips_bposge): Remove mode from comparison
+	operator.
+	* config/mips/mips-ps-3d.md (bc1any4t, bc1any4f): Likewise.
+	(bc1any2t, bc1any2f): Likewise.
+	(single_cc): New expander.
+	(*branch_upper_lower, *branch_upper_lower_inverted): New patterns.
+
+2006-03-09  Richard Sandiford  <richard@codesourcery.com>
+
 	* doc/md.texi: Update documentation of MIPS constraints.
 	* config/mips/constraints.md: New file.
 	* config/mips/mips.md: Include it.

gcc/config/mips/mips-dsp.md

@@ -1046,8 +1046,7 @@
 ;; BPOSGE32
 (define_insn "mips_bposge"
   [(set (pc)
-	(if_then_else
-	   (ge:CCDSP (reg:CCDSP CCDSP_PO_REGNUM)
+	(if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
 			  (match_operand:SI 0 "immediate_operand" "I"))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]

gcc/config/mips/mips-protos.h

@@ -212,8 +212,9 @@ extern int mips_register_move_cost (enum machine_mode, enum reg_class,
 
 extern int mips_adjust_insn_length (rtx, int);
 extern const char *mips_output_load_label (void);
-extern const char *mips_output_conditional_branch (rtx, rtx *, int, int,
-						   int, int);
+extern const char *mips_output_conditional_branch (rtx, rtx *, const char *,
+						   const char *);
+extern const char *mips_output_order_conditional_branch (rtx, rtx *, bool);
 extern const char *mips_output_division (const char *, rtx *);
 extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
 extern bool mips_linked_madd_p (rtx, rtx);

gcc/config/mips/mips-ps-3d.md

@@ -389,7 +389,7 @@
 ; Branch on Any of Four Floating Point Condition Codes True
 (define_insn "bc1any4t"
   [(set (pc)
-	(if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
+	(if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
 			  (const_int 0))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
@@ -401,7 +401,7 @@
 ; Branch on Any of Four Floating Point Condition Codes False
 (define_insn "bc1any4f"
   [(set (pc)
-	(if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
+	(if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
 			  (const_int -1))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
@@ -413,7 +413,7 @@
 ; Branch on Any of Two Floating Point Condition Codes True
 (define_insn "bc1any2t"
   [(set (pc)
-	(if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
+	(if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
 			  (const_int 0))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
@@ -425,7 +425,7 @@
 ; Branch on Any of Two Floating Point Condition Codes False
 (define_insn "bc1any2f"
   [(set (pc)
-	(if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
+	(if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
 			  (const_int -1))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
@@ -434,6 +434,59 @@
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
 
+; Used to access one register in a CCV2 pair.  Operand 0 is the register
+; pair and operand 1 is the index of the register we want (a CONST_INT).
+(define_expand "single_cc"
+  [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
+       (const_int 0))])
+
+; This is a normal floating-point branch pattern, but rather than check
+; a single CCmode register, it checks one register in a CCV2 pair.
+; Operand 2 is the register pair and operand 3 is the index of the
+; register we want.
+(define_insn "*branch_upper_lower"
+  [(set (pc)
+        (if_then_else
+	 (match_operator 0 "equality_operator"
+	    [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
+			 (match_operand 3 "const_int_operand")]
+			UNSPEC_SINGLE_CC)
+	     (const_int 0)])
+	 (label_ref (match_operand 1 "" ""))
+	 (pc)))]
+  "TARGET_HARD_FLOAT"
+{
+  operands[2]
+    = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
+  return mips_output_conditional_branch (insn, operands,
+					 MIPS_BRANCH ("b%F0", "%2,%1"),
+					 MIPS_BRANCH ("b%W0", "%2,%1"));
+}
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
+; As above, but with the sense of the condition reversed.
+(define_insn "*branch_upper_lower_inverted"
+  [(set (pc)
+        (if_then_else
+	 (match_operator 0 "equality_operator"
+	    [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
+			 (match_operand 3 "const_int_operand")]
+			UNSPEC_SINGLE_CC)
+	     (const_int 0)])
+	 (pc)
+	 (label_ref (match_operand 1 "" ""))))]
+  "TARGET_HARD_FLOAT"
+{
+  operands[2]
+    = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
+  return mips_output_conditional_branch (insn, operands,
+					 MIPS_BRANCH ("b%W0", "%2,%1"),
+					 MIPS_BRANCH ("b%F0", "%2,%1"));
+}
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
 ;----------------------------------------------------------------------------
 ; Floating Point Reduced Precision Reciprocal Square Root Instructions.
 ;----------------------------------------------------------------------------

gcc/config/mips/mips.h

@@ -2273,6 +2273,12 @@ typedef struct mips_args {
 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
   ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
 
+/* Return the asm template for a non-MIPS16 conditional branch instruction.
+   OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
+   its operands.  */
+#define MIPS_BRANCH(OPCODE, OPERANDS) \
+  "%*" OPCODE "%?\t" OPERANDS "%/"
+
 /* Control the assembler format that we output.  */
 
 /* Output to assembler file text saying following lines

gcc/config/mips/mips.md

@@ -72,6 +72,7 @@
    (UNSPEC_RSQRT2		209)
    (UNSPEC_RECIP1		210)
    (UNSPEC_RECIP2		211)
+   (UNSPEC_SINGLE_CC		212)
 
    ;; MIPS DSP ASE Revision 0.98 3/24/2005
    (UNSPEC_ADDQ			300)
@@ -4272,85 +4273,65 @@
 
 ;; Conditional branches on floating-point equality tests.
 
-(define_insn "branch_fp"
+(define_insn "*branch_fp"
   [(set (pc)
         (if_then_else
-         (match_operator:CC 0 "comparison_operator"
+         (match_operator 0 "equality_operator"
                          [(match_operand:CC 2 "register_operand" "z")
 			  (const_int 0)])
          (label_ref (match_operand 1 "" ""))
          (pc)))]
   "TARGET_HARD_FLOAT"
 {
-  return mips_output_conditional_branch (insn,
-					 operands,
-					 /*two_operands_p=*/0,
-					 /*float_p=*/1,
-					 /*inverted_p=*/0,
-					 get_attr_length (insn));
+  return mips_output_conditional_branch (insn, operands,
+					 MIPS_BRANCH ("b%F0", "%2,%1"),
+					 MIPS_BRANCH ("b%W0", "%2,%1"));
 }
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
 
-(define_insn "branch_fp_inverted"
+(define_insn "*branch_fp_inverted"
   [(set (pc)
         (if_then_else
-         (match_operator:CC 0 "comparison_operator"
+         (match_operator 0 "equality_operator"
                          [(match_operand:CC 2 "register_operand" "z")
 			  (const_int 0)])
          (pc)
          (label_ref (match_operand 1 "" ""))))]
   "TARGET_HARD_FLOAT"
 {
-  return mips_output_conditional_branch (insn,
-					 operands,
-					 /*two_operands_p=*/0,
-					 /*float_p=*/1,
-					 /*inverted_p=*/1,
-					 get_attr_length (insn));
+  return mips_output_conditional_branch (insn, operands,
+					 MIPS_BRANCH ("b%W0", "%2,%1"),
+					 MIPS_BRANCH ("b%F0", "%2,%1"));
 }
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
 
-;; Conditional branches on comparisons with zero.
+;; Conditional branches on ordered comparisons with zero.
 
-(define_insn "*branch_zero<mode>"
+(define_insn "*branch_order<mode>"
   [(set (pc)
 	(if_then_else
-	 (match_operator 0 "comparison_operator"
+	 (match_operator 0 "order_operator"
 			 [(match_operand:GPR 2 "register_operand" "d")
 			  (const_int 0)])
 	 (label_ref (match_operand 1 "" ""))
 	 (pc)))]
   "!TARGET_MIPS16"
-{
-  return mips_output_conditional_branch (insn,
-					 operands,
-					 /*two_operands_p=*/0,
-					 /*float_p=*/0,
-					 /*inverted_p=*/0,
-					 get_attr_length (insn));
-}
+  { return mips_output_order_conditional_branch (insn, operands, false); }
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
 
-(define_insn "*branch_zero<mode>_inverted"
+(define_insn "*branch_order<mode>_inverted"
   [(set (pc)
 	(if_then_else
-	 (match_operator 0 "comparison_operator"
+	 (match_operator 0 "order_operator"
 			 [(match_operand:GPR 2 "register_operand" "d")
 			  (const_int 0)])
 	 (pc)
 	 (label_ref (match_operand 1 "" ""))))]
   "!TARGET_MIPS16"
-{
-  return mips_output_conditional_branch (insn,
-					 operands,
-					 /*two_operands_p=*/0,
-					 /*float_p=*/0,
-					 /*inverted_p=*/1,
-					 get_attr_length (insn));
-}
+  { return mips_output_order_conditional_branch (insn, operands, true); }
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
 
@@ -4361,17 +4342,14 @@
 	(if_then_else
 	 (match_operator 0 "equality_operator"
 			 [(match_operand:GPR 2 "register_operand" "d")
-			  (match_operand:GPR 3 "register_operand" "d")])
+			  (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
 	 (label_ref (match_operand 1 "" ""))
 	 (pc)))]
   "!TARGET_MIPS16"
 {
-  return mips_output_conditional_branch (insn,
-					 operands,
-					 /*two_operands_p=*/1,
-					 /*float_p=*/0,
-					 /*inverted_p=*/0,
-					 get_attr_length (insn));
+  return mips_output_conditional_branch (insn, operands,
+					 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
+					 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
 }
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
@@ -4381,17 +4359,14 @@
 	(if_then_else
 	 (match_operator 0 "equality_operator"
 			 [(match_operand:GPR 2 "register_operand" "d")
-			  (match_operand:GPR 3 "register_operand" "d")])
+			  (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
 	 (pc)
 	 (label_ref (match_operand 1 "" ""))))]
   "!TARGET_MIPS16"
 {
-  return mips_output_conditional_branch (insn,
-					 operands,
-					 /*two_operands_p=*/1,
-					 /*float_p=*/0,
-					 /*inverted_p=*/1,
-					 get_attr_length (insn));
+  return mips_output_conditional_branch (insn, operands,
+					 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
+					 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
 }
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
@@ -4439,6 +4414,13 @@
   DONE;
 })
 
+;; Used to implement built-in functions.
+(define_expand "condjump"
+  [(set (pc)
+	(if_then_else (match_operand 0)
+		      (label_ref (match_operand 1))
+		      (pc)))])
+
 ;;
 ;;  ....................
 ;;

gcc/config/mips/predicates.md

@@ -212,6 +212,9 @@
 (define_predicate "trap_comparison_operator"
   (match_code "eq,ne,lt,ltu,ge,geu"))
 
+(define_predicate "order_operator"
+  (match_code "lt,ltu,le,leu,ge,geu,gt,gtu"))
+
 
 (define_predicate "small_data_pattern"
   (and (match_code "set,parallel,unspec,unspec_volatile,prefetch")