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riscv-gcc-1
Commit a6ec530c by Richard Kenner
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(adddi3, subdi3, negdi2): Add constraints so output reg does not 

overlap one reg with one of the inputs.

From-SVN: r10325
parent ac1bc2ca
Showing with 26 additions and 18 deletions
gcc/config/rs6000/rs6000.md
......@@ -3510,7 +3510,11 @@
[(set_attr "type" "fp")])
;; Define the DImode operations that can be done in a small number
;; of instructions.
;; of instructions. The & constraints are to prevent the register
;; allocator from allocating registers that overlap with the inputs
;; (for example, having an input in 7,8 and an output in 6,7). We
;; also allow for the the output being the same as one of the inputs.
(define_expand "adddi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
......@@ -3524,19 +3528,21 @@
}")
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
(match_operand:DI 2 "reg_or_short_operand" "r,I")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
(match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
"TARGET_POWER && ! TARGET_POWERPC64"
"@
{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1
{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
[(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,0")
(match_operand:DI 2 "gpc_reg_operand" "r,r")))]
"! TARGET_POWER && ! TARGET_POWERPC64"
"*
{
......@@ -3547,9 +3553,9 @@
[(set_attr "length" "8")])
(define_expand "subdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
(match_operand:DI 2 "gpc_reg_operand" "r,r")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
(match_operand:DI 2 "gpc_reg_operand" "")))]
""
"
{
......@@ -3559,19 +3565,21 @@
}")
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
(match_operand:DI 2 "gpc_reg_operand" "r,r")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r,0")))]
"TARGET_POWER && ! TARGET_POWERPC64"
"@
{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2
{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
[(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r")
(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,0,r")
(match_operand:DI 2 "gpc_reg_operand" "r,r,0")))]
"! TARGET_POWER && ! TARGET_POWERPC64"
"*
{
......@@ -3588,8 +3596,8 @@
"")
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
"! TARGET_POWERPC64"
"*
{
......
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