Commit a35dd1fa by Segher Boessenkool Committed by Segher Boessenkool

rs6000: Make all rlw*nm and rld*c* type shift

They are often labeled just "integer" currently.  Fix that.

Also handle shift properly in those scheduling descriptions that
neglected it.

From-SVN: r210873
parent 73c076c8
2014-05-23 Segher Boessenkool <segher@kernel.crashing.org> 2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/440.md (ppc440-integer): Include shift without
dot.
(ppc440-compare): Include shift with dot.
* config/rs6000/e300c2c3.md (ppce300c3_iu): Include shift without
dot.
* config/rs6000/e5500.md (e5500_sfx2): Include constant shift
without dot.
* config/rs6000/e6500.md (e6500_sfx): Exclude constant shift
without dot.
(e6500_sfx2): Include it.
* config/rs6000/rs6000.md ( *zero_extend<mode>di2_internal1,
*zero_extend<mode>di2_internal2, *zero_extend<mode>di2_internal3,
*zero_extendsidi2_lfiwzx, andsi3_mc, andsi3_nomc,
andsi3_internal0_nomc, extzvsi_internal, extzvdi_internal,
*extzvdi_internal1, *extzvdi_internal2, rotlsi3, *rotlsi3_64,
*rotlsi3_internal4, *rotlsi3_internal7le, *rotlsi3_internal7be,
*rotlsi3_internal10le, *rotlsi3_internal10be, rlwinm,
*lshiftrt_internal1le, *lshiftrt_internal1be,
*lshiftrt_internal4le, *lshiftrt_internal4be, rotldi3,
*rotldi3_internal4, *rotldi3_internal7le, *rotldi3_internal7be,
*rotldi3_internal10le, *rotldi3_internal10be,
*rotldi3_internal13le, *rotldi3_internal13be, *ashldi3_internal4,
ashldi3_internal5, *ashldi3_internal6, *ashldi3_internal7,
ashldi3_internal8, *ashldi3_internal9, anddi3_mc, anddi3_nomc,
*anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous
define_insns): Use type "shift" in the appropriate alternatives.
2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (type): Add "logical". Delete * config/rs6000/rs6000.md (type): Add "logical". Delete
"fast_compare". "fast_compare".
(dot): Adjust comment. (dot): Adjust comment.
......
...@@ -53,8 +53,8 @@ ...@@ -53,8 +53,8 @@
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1 (define_insn_reservation "ppc440-integer" 1
(and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel") (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
(and (eq_attr "type" "add,logical") (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no"))) (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe") "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
...@@ -96,7 +96,7 @@ ...@@ -96,7 +96,7 @@
(define_insn_reservation "ppc440-compare" 2 (define_insn_reservation "ppc440-compare" 2
(and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr") (and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
(and (eq_attr "type" "add,logical") (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes"))) (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe") "ppc440_issue,ppc440_i_pipe")
......
...@@ -93,7 +93,7 @@ ...@@ -93,7 +93,7 @@
;; Other one cycle IU insns ;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1 (define_insn_reservation "ppce300c3_iu" 1
(and (ior (eq_attr "type" "integer,insert,isel") (and (ior (eq_attr "type" "integer,insert,isel")
(and (eq_attr "type" "add,logical") (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no"))) (eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
......
...@@ -67,7 +67,10 @@ ...@@ -67,7 +67,10 @@
(define_insn_reservation "e5500_sfx2" 2 (define_insn_reservation "e5500_sfx2" 2
(and (ior (eq_attr "type" "cmp,compare,trap") (and (ior (eq_attr "type" "cmp,compare,trap")
(and (eq_attr "type" "add,logical") (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes"))) (eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx") "e5500_decode,e5500_sfx")
......
...@@ -63,6 +63,7 @@ ...@@ -63,6 +63,7 @@
(and (eq_attr "type" "add,logical") (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no")) (eq_attr "dot" "no"))
(and (eq_attr "type" "shift") (and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no"))) (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx") "e6500_decode,e6500_sfx")
...@@ -70,7 +71,10 @@ ...@@ -70,7 +71,10 @@
(define_insn_reservation "e6500_sfx2" 2 (define_insn_reservation "e6500_sfx2" 2
(and (ior (eq_attr "type" "cmp,compare,trap") (and (ior (eq_attr "type" "cmp,compare,trap")
(and (eq_attr "type" "add,logical") (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes"))) (eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx") "e6500_decode,e6500_sfx")
......
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