rs6000: Make all rlw*nm and rld*c* type shift

They are often labeled just "integer" currently.  Fix that.

Also handle shift properly in those scheduling descriptions that
neglected it.

From-SVN: r210873

gcc/ChangeLog

 2014-05-23  Segher Boessenkool  <segher@kernel.crashing.org>
 
+	* config/rs6000/440.md (ppc440-integer): Include shift without
+	dot.
+	(ppc440-compare): Include shift with dot.
+	* config/rs6000/e300c2c3.md (ppce300c3_iu): Include shift without
+	dot.
+	* config/rs6000/e5500.md (e5500_sfx2): Include constant shift
+	without dot.
+	* config/rs6000/e6500.md (e6500_sfx): Exclude constant shift
+	without dot.
+	(e6500_sfx2): Include it.
+	* config/rs6000/rs6000.md ( *zero_extend<mode>di2_internal1,
+	*zero_extend<mode>di2_internal2, *zero_extend<mode>di2_internal3,
+	*zero_extendsidi2_lfiwzx, andsi3_mc, andsi3_nomc,
+	andsi3_internal0_nomc, extzvsi_internal, extzvdi_internal,
+	*extzvdi_internal1, *extzvdi_internal2, rotlsi3, *rotlsi3_64,
+	*rotlsi3_internal4, *rotlsi3_internal7le, *rotlsi3_internal7be,
+	*rotlsi3_internal10le, *rotlsi3_internal10be, rlwinm,
+	*lshiftrt_internal1le, *lshiftrt_internal1be,
+	*lshiftrt_internal4le, *lshiftrt_internal4be, rotldi3,
+	*rotldi3_internal4, *rotldi3_internal7le, *rotldi3_internal7be,
+	*rotldi3_internal10le, *rotldi3_internal10be,
+	*rotldi3_internal13le, *rotldi3_internal13be, *ashldi3_internal4,
+	ashldi3_internal5, *ashldi3_internal6, *ashldi3_internal7,
+	ashldi3_internal8, *ashldi3_internal9, anddi3_mc, anddi3_nomc,
+	*anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous
+	define_insns): Use type "shift" in the appropriate alternatives.
+
+2014-05-23  Segher Boessenkool  <segher@kernel.crashing.org>
+
 	* config/rs6000/rs6000.md (type): Add "logical".  Delete
 	"fast_compare".
 	(dot): Adjust comment.

gcc/config/rs6000/440.md

@@ -53,8 +53,8 @@
   "ppc440_issue,ppc440_l_pipe")
 
 (define_insn_reservation "ppc440-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+	    (and (eq_attr "type" "add,logical,shift")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc440"))
   "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -96,7 +96,7 @@
 
 (define_insn_reservation "ppc440-compare" 2
   (and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
-	    (and (eq_attr "type" "add,logical")
+	    (and (eq_attr "type" "add,logical,shift")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc440"))
   "ppc440_issue,ppc440_i_pipe")

gcc/config/rs6000/e300c2c3.md

@@ -93,7 +93,7 @@
 ;; Other one cycle IU insns
 (define_insn_reservation "ppce300c3_iu" 1
   (and (ior (eq_attr "type" "integer,insert,isel")
-	    (and (eq_attr "type" "add,logical")
+	    (and (eq_attr "type" "add,logical,shift")
 		 (eq_attr "dot" "no")))
        (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
   "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")

gcc/config/rs6000/e5500.md

@@ -67,7 +67,10 @@
 (define_insn_reservation "e5500_sfx2" 2
   (and (ior (eq_attr "type" "cmp,compare,trap")
 	    (and (eq_attr "type" "add,logical")
-		 (eq_attr "dot"  "yes")))
+		 (eq_attr "dot"  "yes"))
+	    (and (eq_attr "type" "shift")
+		 (eq_attr "dot"  "yes")
+		 (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce5500"))
   "e5500_decode,e5500_sfx")
 

gcc/config/rs6000/e6500.md

@@ -63,6 +63,7 @@
 	    (and (eq_attr "type" "add,logical")
 		 (eq_attr "dot"  "no"))
 	    (and (eq_attr "type" "shift")
+		 (eq_attr "dot"  "no")
 		 (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx")
@@ -70,7 +71,10 @@
 (define_insn_reservation "e6500_sfx2" 2
   (and (ior (eq_attr "type" "cmp,compare,trap")
 	    (and (eq_attr "type" "add,logical")
-		 (eq_attr "dot"  "yes")))
+		 (eq_attr "dot"  "yes"))
+	    (and (eq_attr "type" "shift")
+		 (eq_attr "dot"  "yes")
+		 (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx")
 

gcc/config/rs6000/rs6000.md

@@ -565,7 +565,7 @@
   "@
    l<wd>z%U1%X1 %0,%1
    rldicl %0,%1,0,<dbits>"
-  [(set_attr "type" "load,*")])
+  [(set_attr "type" "load,shift")])
 
 (define_insn "*zero_extend<mode>di2_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -576,7 +576,8 @@
   "@
    rldicl. %2,%1,0,<dbits>
    #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -602,7 +603,8 @@
   "@
    rldicl. %0,%1,0,<dbits>
    #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -629,7 +631,7 @@
    mtvsrwz %x0,%1
    lfiwzx %0,%y1
    lxsiwzx %x0,%y1"
-  [(set_attr "type" "load,*,mffgpr,fpload,fpload")])
+  [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
 
 (define_insn "extendqidi2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -866,7 +868,7 @@
   "@
    lbz%U1%X1 %0,%1
    rlwinm %0,%1,0,0xff"
-  [(set_attr "type" "load,*")])
+  [(set_attr "type" "load,shift")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -988,7 +990,7 @@
   "@
    lbz%U1%X1 %0,%1
    rlwinm %0,%1,0,0xff"
-  [(set_attr "type" "load,*")])
+  [(set_attr "type" "load,shift")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -1116,7 +1118,7 @@
   "@
    lhz%U1%X1 %0,%1
    rlwinm %0,%1,0,0xffff"
-  [(set_attr "type" "load,*")])
+  [(set_attr "type" "load,shift")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2915,7 +2917,7 @@
    rlwinm %0,%1,0,%m2,%M2
    andi. %0,%1,%b2
    andis. %0,%1,%u2"
-  [(set_attr "type" "*,*,logical,logical")
+  [(set_attr "type" "*,shift,logical,logical")
    (set_attr "dot" "no,no,yes,yes")])
 
 (define_insn "andsi3_nomc"
@@ -2926,7 +2928,8 @@
   "!rs6000_gen_cell_microcode"
   "@
    and %0,%1,%2
-   rlwinm %0,%1,0,%m2,%M2")
+   rlwinm %0,%1,0,%m2,%M2"
+  [(set_attr "type" "logical,shift")])
 
 (define_insn "andsi3_internal0_nomc"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -2935,7 +2938,8 @@
   "!rs6000_gen_cell_microcode"
   "@
    and %0,%1,%2
-   rlwinm %0,%1,0,%m2,%M2")
+   rlwinm %0,%1,0,%m2,%M2"
+  [(set_attr "type" "logical,shift")])
 
 
 ;; Note to set cr's other than cr0 we do the and immediate and then
@@ -3665,7 +3669,8 @@
   else
     operands[3] = GEN_INT (start + size);
   return \"rlwinm %0,%1,%3,%s2,31\";
-}")
+}"
+  [(set_attr "type" "shift")])
 
 (define_insn "*extzvsi_internal1"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -3795,7 +3800,8 @@
     operands[3] = GEN_INT (start + size);
   operands[2] = GEN_INT (64 - size);
   return \"rldicl %0,%1,%3,%2\";
-}")
+}"
+  [(set_attr "type" "shift")])
 
 (define_insn "*extzvdi_internal1"
   [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
@@ -3817,7 +3823,8 @@
   operands[2] = GEN_INT (64 - size);
   return \"rldicl. %4,%1,%3,%2\";
 }"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")])
 
 (define_insn "*extzvdi_internal2"
   [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
@@ -3840,7 +3847,8 @@
   operands[2] = GEN_INT (64 - size);
   return \"rldicl. %0,%1,%3,%2\";
 }"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")])
 
 (define_insn "rotlsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -3850,7 +3858,7 @@
   "@
    rlwnm %0,%1,%2,0xffffffff
    rlwinm %0,%1,%h2,0xffffffff"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_64"
@@ -3862,7 +3870,7 @@
   "@
    rlwnm %0,%1,%2,0xffffffff
    rlwinm %0,%1,%h2,0xffffffff"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal2"
@@ -3938,7 +3946,7 @@
   "@
    rlwnm %0,%1,%2,%m3,%M3
    rlwinm %0,%1,%h2,%m3,%M3"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal5"
@@ -4026,7 +4034,8 @@
   [(set (attr "cell_micro")
      (if_then_else (match_operand:SI 2 "const_int_operand" "")
 	(const_string "not")
-	(const_string "always")))])
+	(const_string "always")))
+   (set_attr "type" "shift")])
 
 (define_insn "*rotlsi3_internal7be"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4039,7 +4048,8 @@
   [(set (attr "cell_micro")
      (if_then_else (match_operand:SI 2 "const_int_operand" "")
 	(const_string "not")
-	(const_string "always")))])
+	(const_string "always")))
+   (set_attr "type" "shift")])
 
 (define_insn "*rotlsi3_internal8le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -4199,7 +4209,7 @@
   "@
    rlwnm %0,%1,%2,0xffff
    rlwinm %0,%1,%h2,0xffff"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal10be"
@@ -4212,7 +4222,7 @@
   "@
    rlwnm %0,%1,%2,0xffff
    rlwinm %0,%1,%h2,0xffff"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal11le"
@@ -4456,7 +4466,8 @@
 			   (match_operand:SI 2 "const_int_operand" "i"))
 		(match_operand:SI 3 "mask_operand" "n")))]
   "includes_lshift_p (operands[2], operands[3])"
-  "rlwinm %0,%1,%h2,%m3,%M3")
+  "rlwinm %0,%1,%h2,%m3,%M3"
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -4623,7 +4634,8 @@
 			     (match_operand:SI 2 "const_int_operand" "i"))
 		(match_operand:SI 3 "mask_operand" "n")))]
   "includes_rshift_p (operands[2], operands[3])"
-  "rlwinm %0,%1,%s2,%m3,%M3")
+  "rlwinm %0,%1,%s2,%m3,%M3"
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -4699,7 +4711,8 @@
 	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
   "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
-  "rlwinm %0,%1,%s2,0xff")
+  "rlwinm %0,%1,%s2,0xff"
+  [(set_attr "type" "shift")])
 
 (define_insn "*lshiftrt_internal1be"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4708,7 +4721,8 @@
 	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "const_int_operand" "i")) 3)))]
   "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
-  "rlwinm %0,%1,%s2,0xff")
+  "rlwinm %0,%1,%s2,0xff"
+  [(set_attr "type" "shift")])
 
 (define_insn "*lshiftrt_internal2le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -4861,7 +4875,8 @@
 	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
   "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
-  "rlwinm %0,%1,%s2,0xffff")
+  "rlwinm %0,%1,%s2,0xffff"
+  [(set_attr "type" "shift")])
 
 (define_insn "*lshiftrt_internal4be"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4870,7 +4885,8 @@
 	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "const_int_operand" "i")) 2)))]
   "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
-  "rlwinm %0,%1,%s2,0xffff")
+  "rlwinm %0,%1,%s2,0xffff"
+  [(set_attr "type" "shift")])
 
 (define_insn "*lshiftrt_internal5le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -6969,7 +6985,7 @@
   "@
    rldcl %0,%1,%2,0
    rldicl %0,%1,%H2,0"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal2"
@@ -7045,7 +7061,7 @@
   "@
    rldc%B3 %0,%1,%2,%S3
    rldic%B3 %0,%1,%H2,%S3"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal5"
@@ -7132,7 +7148,7 @@
   "@
    rldcl %0,%1,%2,56
    rldicl %0,%1,%H2,56"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal7be"
@@ -7145,7 +7161,7 @@
   "@
    rldcl %0,%1,%2,56
    rldicl %0,%1,%H2,56"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal8le"
@@ -7306,7 +7322,7 @@
   "@
    rldcl %0,%1,%2,48
    rldicl %0,%1,%H2,48"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal10be"
@@ -7319,7 +7335,7 @@
   "@
    rldcl %0,%1,%2,48
    rldicl %0,%1,%H2,48"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal11le"
@@ -7480,7 +7496,7 @@
   "@
    rldcl %0,%1,%2,32
    rldicl %0,%1,%H2,32"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal13be"
@@ -7493,7 +7509,7 @@
   "@
    rldcl %0,%1,%2,32
    rldicl %0,%1,%H2,32"
-  [(set_attr "type" "shift,integer")
+  [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal14le"
@@ -7732,7 +7748,8 @@
 			   (match_operand:SI 2 "const_int_operand" "i"))
 		(match_operand:DI 3 "const_int_operand" "n")))]
   "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
-  "rldic %0,%1,%H2,%W3")
+  "rldic %0,%1,%H2,%W3"
+  [(set_attr "type" "shift")])
 
 (define_insn "ashldi3_internal5"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -7746,7 +7763,8 @@
   "@
    rldic. %4,%1,%H2,%W3
    #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -7780,7 +7798,8 @@
   "@
    rldic. %0,%1,%H2,%W3
    #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -7808,7 +7827,8 @@
 			   (match_operand:SI 2 "const_int_operand" "i"))
 		(match_operand:DI 3 "mask64_operand" "n")))]
   "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
-  "rldicr %0,%1,%H2,%S3")
+  "rldicr %0,%1,%H2,%S3"
+  [(set_attr "type" "shift")])
 
 (define_insn "ashldi3_internal8"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -7822,7 +7842,8 @@
   "@
    rldicr. %4,%1,%H2,%S3
    #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -7856,7 +7877,8 @@
   "@
    rldicr. %0,%1,%H2,%S3
    #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -8084,7 +8106,7 @@
    andi. %0,%1,%b2
    andis. %0,%1,%u2
    #"
-  [(set_attr "type" "*,*,*,logical,logical,*")
+  [(set_attr "type" "*,shift,shift,logical,logical,*")
    (set_attr "dot" "no,no,no,yes,yes,no")
    (set_attr "length" "4,4,4,4,4,8")])
 
@@ -8099,7 +8121,8 @@
    rldic%B2 %0,%1,0,%S2
    rlwinm %0,%1,0,%m2,%M2
    #"
-  [(set_attr "length" "4,4,4,8")])
+  [(set_attr "type" "*,shift,shift,*")
+   (set_attr "length" "4,4,4,8")])
 
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -8143,7 +8166,7 @@
    #
    #
    #"
-  [(set_attr "type" "logical,compare,shift,logical,\
+  [(set_attr "type" "logical,shift,shift,logical,\
 		     logical,compare,compare,compare,compare,compare,\
 		     compare,compare")
    (set_attr "dot" "yes")
@@ -8197,7 +8220,7 @@
    #
    #
    #"
-  [(set_attr "type" "logical,compare,shift,logical,\
+  [(set_attr "type" "logical,shift,shift,logical,\
 		     logical,compare,compare,compare,compare,compare,\
 		     compare,compare")
    (set_attr "dot" "yes")