Commit a199fdd6 by James Van Artsdalen

(all patterns): Use GEN_INT instead of gen_rtx to get const_ints.

Avoid double-negative "! NON_*" constructs for clarity.
Pass NULL_PTR as null parameter instead of 0.
(sqrtM2): Patterns are only valid if IEEE FP or -ffast-math.
(sinM2,cosM2): New patterns.
(zero_extract test): New pattern.

From-SVN: r1982
parent 435defd1
...@@ -52,7 +52,10 @@ ...@@ -52,7 +52,10 @@
;; operand 1 is a register containing the value to scan for. The mode ;; operand 1 is a register containing the value to scan for. The mode
;; of the scas opcode will be the same as the mode of this operand. ;; of the scas opcode will be the same as the mode of this operand.
;; operand 2 is the known alignment of operand 0. ;; operand 2 is the known alignment of operand 0.
;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
;; operand 0 is the argument for `sin'.
;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
;; operand 0 is the argument for `cos'.
;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". ;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM".
;; But restricting MEM here would mean that gcc could not remove a redundant ;; But restricting MEM here would mean that gcc could not remove a redundant
...@@ -427,7 +430,7 @@ ...@@ -427,7 +430,7 @@
/* For small integers, we may actually use testb. */ /* For small integers, we may actually use testb. */
if (GET_CODE (operands[1]) == CONST_INT if (GET_CODE (operands[1]) == CONST_INT
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
&& ! NON_QI_REG_P (operands[0])) && (! REG_P (operands[0]) || QI_REG_P (operands[0])))
{ {
/* We may set the sign bit spuriously. */ /* We may set the sign bit spuriously. */
...@@ -440,8 +443,7 @@ ...@@ -440,8 +443,7 @@
if ((INTVAL (operands[1]) & ~0xff00) == 0) if ((INTVAL (operands[1]) & ~0xff00) == 0)
{ {
cc_status.flags |= CC_NOT_NEGATIVE; cc_status.flags |= CC_NOT_NEGATIVE;
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
INTVAL (operands[1]) >> 8);
if (QI_REG_P (operands[0])) if (QI_REG_P (operands[0]))
return AS2 (test%B0,%1,%h0); return AS2 (test%B0,%1,%h0);
...@@ -456,9 +458,7 @@ ...@@ -456,9 +458,7 @@
&& (INTVAL (operands[1]) & ~0xff0000) == 0) && (INTVAL (operands[1]) & ~0xff0000) == 0)
{ {
cc_status.flags |= CC_NOT_NEGATIVE; cc_status.flags |= CC_NOT_NEGATIVE;
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT (INTVAL (operands[1]) >> 16);
INTVAL (operands[1]) >> 16);
operands[0] = adj_offsettable_operand (operands[0], 2); operands[0] = adj_offsettable_operand (operands[0], 2);
return AS2 (test%B0,%1,%b0); return AS2 (test%B0,%1,%b0);
} }
...@@ -466,9 +466,7 @@ ...@@ -466,9 +466,7 @@
if (GET_CODE (operands[0]) == MEM if (GET_CODE (operands[0]) == MEM
&& (INTVAL (operands[1]) & ~0xff000000) == 0) && (INTVAL (operands[1]) & ~0xff000000) == 0)
{ {
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff);
(INTVAL (operands[1]) >> 24) & 0xff);
operands[0] = adj_offsettable_operand (operands[0], 3); operands[0] = adj_offsettable_operand (operands[0], 3);
return AS2 (test%B0,%1,%b0); return AS2 (test%B0,%1,%b0);
} }
...@@ -489,14 +487,13 @@ ...@@ -489,14 +487,13 @@
{ {
if (GET_CODE (operands[1]) == CONST_INT if (GET_CODE (operands[1]) == CONST_INT
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
&& ! NON_QI_REG_P (operands[0])) && (! REG_P (operands[0]) || QI_REG_P (operands[0])))
{ {
if ((INTVAL (operands[1]) & 0xff00) == 0) if ((INTVAL (operands[1]) & 0xff00) == 0)
{ {
/* ??? This might not be necessary. */ /* ??? This might not be necessary. */
if (INTVAL (operands[1]) & 0xffff0000) if (INTVAL (operands[1]) & 0xffff0000)
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
INTVAL (operands[1]) & 0xff);
/* We may set the sign bit spuriously. */ /* We may set the sign bit spuriously. */
cc_status.flags |= CC_NOT_NEGATIVE; cc_status.flags |= CC_NOT_NEGATIVE;
...@@ -505,8 +502,7 @@ ...@@ -505,8 +502,7 @@
if ((INTVAL (operands[1]) & 0xff) == 0) if ((INTVAL (operands[1]) & 0xff) == 0)
{ {
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff);
(INTVAL (operands[1]) >> 8) & 0xff);
if (QI_REG_P (operands[0])) if (QI_REG_P (operands[0]))
return AS2 (test%B0,%1,%h0); return AS2 (test%B0,%1,%h0);
...@@ -772,7 +768,7 @@ ...@@ -772,7 +768,7 @@
abort (); abort ();
xops[0] = AT_SP (SFmode); xops[0] = AT_SP (SFmode);
xops[1] = gen_rtx (CONST_INT, VOIDmode, 4); xops[1] = GEN_INT (4);
xops[2] = stack_pointer_rtx; xops[2] = stack_pointer_rtx;
output_asm_insn (AS2 (sub%L2,%1,%2), xops); output_asm_insn (AS2 (sub%L2,%1,%2), xops);
...@@ -853,7 +849,7 @@ ...@@ -853,7 +849,7 @@
rtx xops[3]; rtx xops[3];
xops[0] = AT_SP (SFmode); xops[0] = AT_SP (SFmode);
xops[1] = gen_rtx (CONST_INT, VOIDmode, 8); xops[1] = GEN_INT (8);
xops[2] = stack_pointer_rtx; xops[2] = stack_pointer_rtx;
output_asm_insn (AS2 (sub%L2,%1,%2), xops); output_asm_insn (AS2 (sub%L2,%1,%2), xops);
...@@ -974,7 +970,7 @@ ...@@ -974,7 +970,7 @@
{ {
rtx xops[2]; rtx xops[2];
xops[0] = operands[0]; xops[0] = operands[0];
xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xffff); xops[1] = GEN_INT (0xffff);
output_asm_insn (AS2 (and%L0,%1,%k0), xops); output_asm_insn (AS2 (and%L0,%1,%k0), xops);
RET; RET;
} }
...@@ -998,7 +994,7 @@ ...@@ -998,7 +994,7 @@
{ {
rtx xops[2]; rtx xops[2];
xops[0] = operands[0]; xops[0] = operands[0];
xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff); xops[1] = GEN_INT (0xff);
output_asm_insn (AS2 (and%L0,%1,%k0), xops); output_asm_insn (AS2 (and%L0,%1,%k0), xops);
RET; RET;
} }
...@@ -1022,7 +1018,7 @@ ...@@ -1022,7 +1018,7 @@
{ {
rtx xops[2]; rtx xops[2];
xops[0] = operands[0]; xops[0] = operands[0];
xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff); xops[1] = GEN_INT (0xff);
output_asm_insn (AS2 (and%L0,%1,%k0), xops); output_asm_insn (AS2 (and%L0,%1,%k0), xops);
RET; RET;
} }
...@@ -1822,8 +1818,7 @@ ...@@ -1822,8 +1818,7 @@
return AS2 (mov%B0,%2,%b0); return AS2 (mov%B0,%2,%b0);
} }
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
INTVAL (operands[2]) & 0xff);
return AS2 (and%B0,%2,%b0); return AS2 (and%B0,%2,%b0);
} }
...@@ -1837,8 +1832,7 @@ ...@@ -1837,8 +1832,7 @@
return AS2 (mov%B0,%2,%h0); return AS2 (mov%B0,%2,%h0);
} }
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
INTVAL (operands[2]) >> 8);
return AS2 (and%B0,%2,%h0); return AS2 (and%B0,%2,%h0);
} }
...@@ -1863,7 +1857,7 @@ ...@@ -1863,7 +1857,7 @@
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
{ {
/* Can we ignore the upper byte? */ /* Can we ignore the upper byte? */
if (! NON_QI_REG_P (operands[0]) if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
&& (INTVAL (operands[2]) & 0xff00) == 0xff00) && (INTVAL (operands[2]) & 0xff00) == 0xff00)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
...@@ -1874,8 +1868,7 @@ ...@@ -1874,8 +1868,7 @@
return AS2 (mov%B0,%2,%b0); return AS2 (mov%B0,%2,%b0);
} }
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
INTVAL (operands[2]) & 0xff);
return AS2 (and%B0,%2,%b0); return AS2 (and%B0,%2,%b0);
} }
...@@ -1891,8 +1884,7 @@ ...@@ -1891,8 +1884,7 @@
return AS2 (mov%B0,%2,%h0); return AS2 (mov%B0,%2,%h0);
} }
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
(INTVAL (operands[2]) >> 8) & 0xff);
return AS2 (and%B0,%2,%h0); return AS2 (and%B0,%2,%h0);
} }
} }
...@@ -1944,7 +1936,8 @@ ...@@ -1944,7 +1936,8 @@
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
{ {
if (! NON_QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff) == 0) if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
&& (INTVAL (operands[2]) & ~0xff) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
...@@ -1957,8 +1950,7 @@ ...@@ -1957,8 +1950,7 @@
if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
INTVAL (operands[2]) >> 8);
if (INTVAL (operands[2]) == 0xff) if (INTVAL (operands[2]) == 0xff)
return AS2 (mov%B0,%2,%h0); return AS2 (mov%B0,%2,%h0);
...@@ -1981,13 +1973,12 @@ ...@@ -1981,13 +1973,12 @@
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
{ {
/* Can we ignore the upper byte? */ /* Can we ignore the upper byte? */
if (! NON_QI_REG_P (operands[0]) if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
&& (INTVAL (operands[2]) & 0xff00) == 0) && (INTVAL (operands[2]) & 0xff00) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
if (INTVAL (operands[2]) & 0xffff0000) if (INTVAL (operands[2]) & 0xffff0000)
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
INTVAL (operands[2]) & 0xffff);
if (INTVAL (operands[2]) == 0xff) if (INTVAL (operands[2]) == 0xff)
return AS2 (mov%B0,%2,%b0); return AS2 (mov%B0,%2,%b0);
...@@ -2001,8 +1992,7 @@ ...@@ -2001,8 +1992,7 @@
&& (INTVAL (operands[2]) & 0xff) == 0) && (INTVAL (operands[2]) & 0xff) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
(INTVAL (operands[2]) >> 8) & 0xff);
if (INTVAL (operands[2]) == 0xff) if (INTVAL (operands[2]) == 0xff)
return AS2 (mov%B0,%2,%h0); return AS2 (mov%B0,%2,%h0);
...@@ -2034,7 +2024,8 @@ ...@@ -2034,7 +2024,8 @@
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
{ {
if (! NON_QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff) == 0) if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
&& (INTVAL (operands[2]) & ~0xff) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
...@@ -2047,8 +2038,7 @@ ...@@ -2047,8 +2038,7 @@
if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
INTVAL (operands[2]) >> 8);
if (INTVAL (operands[2]) == 0xff) if (INTVAL (operands[2]) == 0xff)
return AS1 (not%B0,%h0); return AS1 (not%B0,%h0);
...@@ -2071,13 +2061,12 @@ ...@@ -2071,13 +2061,12 @@
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
{ {
/* Can we ignore the upper byte? */ /* Can we ignore the upper byte? */
if (! NON_QI_REG_P (operands[0]) if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
&& (INTVAL (operands[2]) & 0xff00) == 0) && (INTVAL (operands[2]) & 0xff00) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
if (INTVAL (operands[2]) & 0xffff0000) if (INTVAL (operands[2]) & 0xffff0000)
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
INTVAL (operands[2]) & 0xffff);
if (INTVAL (operands[2]) == 0xff) if (INTVAL (operands[2]) == 0xff)
return AS1 (not%B0,%b0); return AS1 (not%B0,%b0);
...@@ -2091,8 +2080,7 @@ ...@@ -2091,8 +2080,7 @@
&& (INTVAL (operands[2]) & 0xff) == 0) && (INTVAL (operands[2]) & 0xff) == 0)
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
(INTVAL (operands[2]) >> 8) & 0xff);
if (INTVAL (operands[2]) == 0xff) if (INTVAL (operands[2]) == 0xff)
return AS1 (not%B0,%h0); return AS1 (not%B0,%h0);
...@@ -2192,21 +2180,59 @@ ...@@ -2192,21 +2180,59 @@
(define_insn "sqrtsf2" (define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "general_operand" "0")))] (sqrt:SF (match_operand:SF 1 "general_operand" "0")))]
"TARGET_80387" "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fsqrt") "fsqrt")
(define_insn "sqrtdf2" (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "general_operand" "0")))] (sqrt:DF (match_operand:DF 1 "general_operand" "0")))]
"TARGET_80387" "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fsqrt") "fsqrt")
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF (sqrt:DF (float_extend:DF
(match_operand:SF 1 "general_operand" "0"))))] (match_operand:SF 1 "general_operand" "0"))))]
"TARGET_80387" "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fsqrt") "fsqrt")
(define_insn "sindf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fsin")
(define_insn "sinsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fsin")
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))] 1))]
"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fsin")
(define_insn "cosdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fcos")
(define_insn "cossf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fcos")
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))] 2))]
"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
"fcos")
;;- one complement instructions ;;- one complement instructions
...@@ -2297,8 +2323,7 @@ ...@@ -2297,8 +2323,7 @@
if (INTVAL (xops[0]) > 32) if (INTVAL (xops[0]) > 32)
{ {
xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */ output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */
} }
} }
...@@ -2335,7 +2360,7 @@ ...@@ -2335,7 +2360,7 @@
output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops);
output_asm_insn (AS2 (sal%L2,%0,%2), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops);
xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ xops[1] = GEN_INT (7); /* shift count & 1 */
output_asm_insn (AS2 (shr%B0,%1,%0), xops); output_asm_insn (AS2 (shr%B0,%1,%0), xops);
...@@ -2367,8 +2392,7 @@ ...@@ -2367,8 +2392,7 @@
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
operands[1] = gen_rtx (MULT, SImode, operands[1], operands[1] = gen_rtx (MULT, SImode, operands[1],
gen_rtx (CONST_INT, VOIDmode, GEN_INT (1 << INTVAL (operands[2])));
1 << INTVAL (operands[2])));
return AS2 (lea%L0,%a1,%0); return AS2 (lea%L0,%a1,%0);
} }
} }
...@@ -2455,14 +2479,13 @@ ...@@ -2455,14 +2479,13 @@
if (INTVAL (xops[0]) > 31) if (INTVAL (xops[0]) > 31)
{ {
xops[1] = gen_rtx (CONST_INT, VOIDmode, 31); xops[1] = GEN_INT (31);
output_asm_insn (AS2 (mov%L2,%3,%2), xops); output_asm_insn (AS2 (mov%L2,%3,%2), xops);
output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */
if (INTVAL (xops[0]) > 32) if (INTVAL (xops[0]) > 32)
{ {
xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */ output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */
} }
} }
...@@ -2500,7 +2523,7 @@ ...@@ -2500,7 +2523,7 @@
output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
output_asm_insn (AS2 (sar%L3,%0,%3), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops);
xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ xops[1] = GEN_INT (7); /* shift count & 1 */
output_asm_insn (AS2 (shr%B0,%1,%0), xops); output_asm_insn (AS2 (shr%B0,%1,%0), xops);
...@@ -2597,8 +2620,7 @@ ...@@ -2597,8 +2620,7 @@
if (INTVAL (xops[0]) > 32) if (INTVAL (xops[0]) > 32)
{ {
xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */ output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */
} }
} }
...@@ -2636,7 +2658,7 @@ ...@@ -2636,7 +2658,7 @@
output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
output_asm_insn (AS2 (shr%L3,%0,%3), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops);
xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ xops[1] = GEN_INT (7); /* shift count & 1 */
output_asm_insn (AS2 (shr%B0,%1,%0), xops); output_asm_insn (AS2 (shr%B0,%1,%0), xops);
...@@ -2782,11 +2804,9 @@ ...@@ -2782,11 +2804,9 @@
if (GET_CODE (operands[3]) == CONST_INT) if (GET_CODE (operands[3]) == CONST_INT)
{ {
unsigned int mask = (1 << INTVAL (operands[1])) - 1; unsigned int mask = (1 << INTVAL (operands[1])) - 1;
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT (~(mask << INTVAL (operands[2])));
~(mask << INTVAL (operands[2])));
output_asm_insn (AS2 (and%L0,%1,%0), operands); output_asm_insn (AS2 (and%L0,%1,%0), operands);
operands[3] = gen_rtx (CONST_INT, VOIDmode, operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2]));
INTVAL (operands[3]) << INTVAL (operands[2]));
output_asm_insn (AS2 (or%L0,%3,%0), operands); output_asm_insn (AS2 (or%L0,%3,%0), operands);
} }
else else
...@@ -2795,8 +2815,7 @@ ...@@ -2795,8 +2815,7 @@
if (INTVAL (operands[2])) if (INTVAL (operands[2]))
output_asm_insn (AS2 (ror%L0,%2,%0), operands); output_asm_insn (AS2 (ror%L0,%2,%0), operands);
output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands); output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands);
operands[2] = gen_rtx (CONST_INT, VOIDmode, operands[2] = GEN_INT (BITS_PER_WORD
BITS_PER_WORD
- INTVAL (operands[1]) - INTVAL (operands[2])); - INTVAL (operands[1]) - INTVAL (operands[2]));
if (INTVAL (operands[2])) if (INTVAL (operands[2]))
output_asm_insn (AS2 (ror%L0,%2,%0), operands); output_asm_insn (AS2 (ror%L0,%2,%0), operands);
...@@ -2912,6 +2931,69 @@ ...@@ -2912,6 +2931,69 @@
;; don't allow a MEM in the operand predicate without allowing it in the ;; don't allow a MEM in the operand predicate without allowing it in the
;; constraint. ;; constraint.
;; ??? All bets are off if operand 0 is a volatile MEM reference.
(define_insn ""
[(set (cc0) (zero_extract (match_operand 0 "general_operand" "rm")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n")))]
"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 4
&& (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0]))"
"*
{
unsigned int mask;
mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
operands[1] = GEN_INT (mask);
if (! REG_P (operands[0]) || QI_REG_P (operands[0]))
{
/* We may set the sign bit spuriously. */
if ((mask & ~0xff) == 0)
{
cc_status.flags |= CC_NOT_NEGATIVE;
return AS2 (test%B0,%1,%b0);
}
if ((mask & ~0xff00) == 0)
{
cc_status.flags |= CC_NOT_NEGATIVE;
operands[1] = GEN_INT (mask >> 8);
if (QI_REG_P (operands[0]))
return AS2 (test%B0,%1,%h0);
else
{
operands[0] = adj_offsettable_operand (operands[0], 1);
return AS2 (test%B0,%1,%b0);
}
}
if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0)
{
cc_status.flags |= CC_NOT_NEGATIVE;
operands[1] = GEN_INT (mask >> 16);
operands[0] = adj_offsettable_operand (operands[0], 2);
return AS2 (test%B0,%1,%b0);
}
if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0)
{
cc_status.flags |= CC_NOT_NEGATIVE;
operands[1] = GEN_INT (mask >> 24);
operands[0] = adj_offsettable_operand (operands[0], 3);
return AS2 (test%B0,%1,%b0);
}
}
if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
return AS2 (test%L0,%1,%0);
return AS2 (test%L1,%0,%1);
}")
(define_insn "" (define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
(const_int 1) (const_int 1)
...@@ -2997,7 +3079,7 @@ ...@@ -2997,7 +3079,7 @@
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
return AS1 (sete,%0); return AS1 (sete,%0);
OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0); OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR);
}") }")
(define_expand "sgtu" (define_expand "sgtu"
...@@ -3093,7 +3175,7 @@ ...@@ -3093,7 +3175,7 @@
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
return AS1 (setb,%0); return AS1 (setb,%0);
OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0); OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR);
}") }")
(define_expand "sleu" (define_expand "sleu"
...@@ -3201,7 +3283,7 @@ ...@@ -3201,7 +3283,7 @@
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
return AS1 (je,%l0); return AS1 (je,%l0);
OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0); OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
}") }")
(define_expand "bgtu" (define_expand "bgtu"
...@@ -3333,7 +3415,7 @@ ...@@ -3333,7 +3415,7 @@
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
return AS1 (jb,%l0); return AS1 (jb,%l0);
OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0); OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
}") }")
(define_expand "bleu" (define_expand "bleu"
...@@ -3399,7 +3481,7 @@ ...@@ -3399,7 +3481,7 @@
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
return AS1 (jne,%l0); return AS1 (jne,%l0);
OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0); OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
}") }")
(define_insn "" (define_insn ""
...@@ -3471,7 +3553,7 @@ ...@@ -3471,7 +3553,7 @@
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
return AS1 (jae,%l0); return AS1 (jae,%l0);
OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0); OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
}") }")
(define_insn "" (define_insn ""
...@@ -3825,7 +3907,7 @@ ...@@ -3825,7 +3907,7 @@
{ {
if (INTVAL (operands[2]) & ~0x03) if (INTVAL (operands[2]) & ~0x03)
{ {
xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); xops[0] = GEN_INT (INTVAL (operands[2]) >> 2);
xops[1] = operands[4]; xops[1] = operands[4];
output_asm_insn (AS2 (mov%L1,%0,%1), xops); output_asm_insn (AS2 (mov%L1,%0,%1), xops);
......
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