aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>, [...]): Separate…

aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>, [...]): Separate instruction and operand with tab instead of space.

2013-01-08  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>,
	aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand
	with tab instead of space.

From-SVN: r195023

gcc/ChangeLog

+2013-01-08  Tejas Belagod  <tejas.belagod@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>,
+	aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand
+	with tab instead of space.
+
 2013-01-08  Nick Clifton  <nickc@redhat.com>
 
 	* config/rl78/rl78.c (rl78_expand_prologue): Always select

gcc/config/aarch64/aarch64-simd.md

@@ -1054,7 +1054,7 @@
                            (match_operand:VQW 2 "register_operand" "w")
                            (match_dup 3)))))]
   "TARGET_SIMD"
-  "<su>mull %0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
+  "<su>mull\\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
   [(set_attr "simd_type" "simd_mull")
    (set_attr "simd_mode" "<MODE>")]
 )
@@ -1082,7 +1082,7 @@
 			    (match_operand:VQW 2 "register_operand" "w")
 			    (match_dup 3)))))]
   "TARGET_SIMD"
-  "<su>mull2 %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+  "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
   [(set_attr "simd_type" "simd_mull")
    (set_attr "simd_mode" "<MODE>")]
 )