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riscv-gcc-1
Commit 9cb24602 by Richard Sandiford Committed by Richard Sandiford
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mips.md (*seq_[sd]i): Renamed from seq_[sd]i_zero. 

	* config/mips/mips.md (*seq_[sd]i): Renamed from seq_[sd]i_zero.
	(*sne_[sd]i): Likewise sne_[sd]i_zero.
	(*sgt_[sd]i): ...and sgt_[sd]i.
	(*slt_[sd]i): ...and slt_[sd]i.
	(*sgtu_[sd]i): ...and sgtu_[sd]i.
	(*sltu_[sd]i): ...and sltu_[sd]i.
	(*sleu_[sd]i): ...and sleu_[sd]i_const.
	Name previously unnamed mips16 patterns.  Formatting fixes.

From-SVN: r84806
parent d7ad1e57
Showing with 107 additions and 96 deletions
gcc/ChangeLog
2004-07-16 Richard Sandiford <rsandifo@redhat.com> 2004-07-16 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (*seq_[sd]i): Renamed from seq_[sd]i_zero.
(*sne_[sd]i): Likewise sne_[sd]i_zero.
(*sgt_[sd]i): ...and sgt_[sd]i.
(*slt_[sd]i): ...and slt_[sd]i.
(*sgtu_[sd]i): ...and sgtu_[sd]i.
(*sltu_[sd]i): ...and sltu_[sd]i.
(*sleu_[sd]i): ...and sleu_[sd]i_const.
Name previously unnamed mips16 patterns. Formatting fixes.
2004-07-16 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (cmp_operands): Renamed from branch_cmp. * config/mips/mips.c (cmp_operands): Renamed from branch_cmp.
(branch_type): Delete. (branch_type): Delete.
(gen_conditional_branch, gen_conditional_move) (gen_conditional_branch, gen_conditional_move)
......
gcc/config/mips/mips.md
...@@ -6021,41 +6021,41 @@ dsrl\t%3,%3,1\n\ ...@@ -6021,41 +6021,41 @@ dsrl\t%3,%3,1\n\
}) })
(define_insn "seq_si_zero" (define_insn "*seq_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(eq:SI (match_operand:SI 1 "register_operand" "d") (eq:SI (match_operand:SI 1 "register_operand" "d")
(const_int 0)))] (const_int 0)))]
"!TARGET_MIPS16" "!TARGET_MIPS16"
"sltu\t%0,%1,1" "sltu\t%0,%1,1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*seq_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t") [(set (match_operand:SI 0 "register_operand" "=t")
(eq:SI (match_operand:SI 1 "register_operand" "d") (eq:SI (match_operand:SI 1 "register_operand" "d")
(const_int 0)))] (const_int 0)))]
"TARGET_MIPS16" "TARGET_MIPS16"
"sltu\t%1,1" "sltu\t%1,1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "seq_di_zero" (define_insn "*seq_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(eq:DI (match_operand:DI 1 "register_operand" "d") (eq:DI (match_operand:DI 1 "register_operand" "d")
(const_int 0)))] (const_int 0)))]
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%1,1" "sltu\t%0,%1,1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*seq_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t") [(set (match_operand:DI 0 "register_operand" "=t")
(eq:DI (match_operand:DI 1 "register_operand" "d") (eq:DI (match_operand:DI 1 "register_operand" "d")
(const_int 0)))] (const_int 0)))]
"TARGET_64BIT && TARGET_MIPS16" "TARGET_64BIT && TARGET_MIPS16"
"sltu\t%1,1" "sltu\t%1,1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
;; On the mips16 the default code is better than using sltu. ;; On the mips16 the default code is better than using sltu.
...@@ -6072,23 +6072,23 @@ dsrl\t%3,%3,1\n\ ...@@ -6072,23 +6072,23 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "sne_si_zero" (define_insn "*sne_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ne:SI (match_operand:SI 1 "register_operand" "d") (ne:SI (match_operand:SI 1 "register_operand" "d")
(const_int 0)))] (const_int 0)))]
"!TARGET_MIPS16" "!TARGET_MIPS16"
"sltu\t%0,%.,%1" "sltu\t%0,%.,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "sne_di_zero" (define_insn "*sne_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(ne:DI (match_operand:DI 1 "register_operand" "d") (ne:DI (match_operand:DI 1 "register_operand" "d")
(const_int 0)))] (const_int 0)))]
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%.,%1" "sltu\t%0,%.,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "sgt" (define_expand "sgt"
[(set (match_operand:SI 0 "register_operand") [(set (match_operand:SI 0 "register_operand")
...@@ -6103,41 +6103,41 @@ dsrl\t%3,%3,1\n\ ...@@ -6103,41 +6103,41 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "sgt_si" (define_insn "*sgt_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(gt:SI (match_operand:SI 1 "register_operand" "d") (gt:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "reg_or_0_operand" "dJ")))] (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16" "!TARGET_MIPS16"
"slt\t%0,%z2,%1" "slt\t%0,%z2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*sgt_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t") [(set (match_operand:SI 0 "register_operand" "=t")
(gt:SI (match_operand:SI 1 "register_operand" "d") (gt:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))] (match_operand:SI 2 "register_operand" "d")))]
"TARGET_MIPS16" "TARGET_MIPS16"
"slt\t%2,%1" "slt\t%2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "sgt_di" (define_insn "*sgt_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(gt:DI (match_operand:DI 1 "register_operand" "d") (gt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "reg_or_0_operand" "dJ")))] (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"slt\t%0,%z2,%1" "slt\t%0,%z2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*sgt_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(gt:DI (match_operand:DI 1 "register_operand" "d") (gt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))] (match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_MIPS16" "TARGET_64BIT && TARGET_MIPS16"
"slt\t%2,%1" "slt\t%2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "sge" (define_expand "sge"
[(set (match_operand:SI 0 "register_operand") [(set (match_operand:SI 0 "register_operand")
...@@ -6165,46 +6165,46 @@ dsrl\t%3,%3,1\n\ ...@@ -6165,46 +6165,46 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "slt_si" (define_insn "*slt_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(lt:SI (match_operand:SI 1 "register_operand" "d") (lt:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))] (match_operand:SI 2 "arith_operand" "dI")))]
"!TARGET_MIPS16" "!TARGET_MIPS16"
"slt\t%0,%1,%2" "slt\t%0,%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*slt_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t,t") [(set (match_operand:SI 0 "register_operand" "=t,t")
(lt:SI (match_operand:SI 1 "register_operand" "d,d") (lt:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "d,I")))] (match_operand:SI 2 "arith_operand" "d,I")))]
"TARGET_MIPS16" "TARGET_MIPS16"
"slt\t%1,%2" "slt\t%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set_attr_alternative "length" (set_attr_alternative "length"
[(const_int 4) [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1") (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4) (const_int 4)
(const_int 8))])]) (const_int 8))])])
(define_insn "slt_di" (define_insn "*slt_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(lt:DI (match_operand:DI 1 "register_operand" "d") (lt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "arith_operand" "dI")))] (match_operand:DI 2 "arith_operand" "dI")))]
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"slt\t%0,%1,%2" "slt\t%0,%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*slt_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t,t") [(set (match_operand:DI 0 "register_operand" "=t,t")
(lt:DI (match_operand:DI 1 "register_operand" "d,d") (lt:DI (match_operand:DI 1 "register_operand" "d,d")
(match_operand:DI 2 "arith_operand" "d,I")))] (match_operand:DI 2 "arith_operand" "d,I")))]
"TARGET_64BIT && TARGET_MIPS16" "TARGET_64BIT && TARGET_MIPS16"
"slt\t%1,%2" "slt\t%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr_alternative "length" (set_attr_alternative "length"
[(const_int 4) [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1") (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
...@@ -6224,56 +6224,56 @@ dsrl\t%3,%3,1\n\ ...@@ -6224,56 +6224,56 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "sle_si_const" (define_insn "*sle_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(le:SI (match_operand:SI 1 "register_operand" "d") (le:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))] (match_operand:SI 2 "small_int" "I")))]
"!TARGET_MIPS16 && INTVAL (operands[2]) < 32767" "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
{ {
operands[2] = GEN_INT (INTVAL (operands[2])+1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%0,%1,%2"; return "slt\t%0,%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*sle_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t") [(set (match_operand:SI 0 "register_operand" "=t")
(le:SI (match_operand:SI 1 "register_operand" "d") (le:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))] (match_operand:SI 2 "small_int" "I")))]
"TARGET_MIPS16 && INTVAL (operands[2]) < 32767" "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
{ {
operands[2] = GEN_INT (INTVAL (operands[2])+1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%1,%2"; return "slt\t%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1") (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4) (const_int 4)
(const_int 8)))]) (const_int 8)))])
(define_insn "sle_di_const" (define_insn "*sle_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(le:DI (match_operand:DI 1 "register_operand" "d") (le:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))] (match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767" "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
{ {
operands[2] = GEN_INT (INTVAL (operands[2])+1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%0,%1,%2"; return "slt\t%0,%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*sle_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t") [(set (match_operand:DI 0 "register_operand" "=t")
(le:DI (match_operand:DI 1 "register_operand" "d") (le:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))] (match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767" "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
{ {
operands[2] = GEN_INT (INTVAL (operands[2])+1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%1,%2"; return "slt\t%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1") (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4) (const_int 4)
(const_int 8)))]) (const_int 8)))])
...@@ -6291,41 +6291,41 @@ dsrl\t%3,%3,1\n\ ...@@ -6291,41 +6291,41 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "sgtu_si" (define_insn "*sgtu_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(gtu:SI (match_operand:SI 1 "register_operand" "d") (gtu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "reg_or_0_operand" "dJ")))] (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16" "!TARGET_MIPS16"
"sltu\t%0,%z2,%1" "sltu\t%0,%z2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*sgtu_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t") [(set (match_operand:SI 0 "register_operand" "=t")
(gtu:SI (match_operand:SI 1 "register_operand" "d") (gtu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))] (match_operand:SI 2 "register_operand" "d")))]
"TARGET_MIPS16" "TARGET_MIPS16"
"sltu\t%2,%1" "sltu\t%2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "sgtu_di" (define_insn "*sgtu_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(gtu:DI (match_operand:DI 1 "register_operand" "d") (gtu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "reg_or_0_operand" "dJ")))] (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%z2,%1" "sltu\t%0,%z2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*sgtu_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t") [(set (match_operand:DI 0 "register_operand" "=t")
(gtu:DI (match_operand:DI 1 "register_operand" "d") (gtu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))] (match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_MIPS16" "TARGET_64BIT && TARGET_MIPS16"
"sltu\t%2,%1" "sltu\t%2,%1"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "sgeu" (define_expand "sgeu"
[(set (match_operand:SI 0 "register_operand") [(set (match_operand:SI 0 "register_operand")
...@@ -6353,46 +6353,46 @@ dsrl\t%3,%3,1\n\ ...@@ -6353,46 +6353,46 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "sltu_si" (define_insn "*sltu_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ltu:SI (match_operand:SI 1 "register_operand" "d") (ltu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))] (match_operand:SI 2 "arith_operand" "dI")))]
"!TARGET_MIPS16" "!TARGET_MIPS16"
"sltu\t%0,%1,%2" "sltu\t%0,%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*sltu_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t,t") [(set (match_operand:SI 0 "register_operand" "=t,t")
(ltu:SI (match_operand:SI 1 "register_operand" "d,d") (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "d,I")))] (match_operand:SI 2 "arith_operand" "d,I")))]
"TARGET_MIPS16" "TARGET_MIPS16"
"sltu\t%1,%2" "sltu\t%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set_attr_alternative "length" (set_attr_alternative "length"
[(const_int 4) [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1") (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4) (const_int 4)
(const_int 8))])]) (const_int 8))])])
(define_insn "sltu_di" (define_insn "*sltu_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(ltu:DI (match_operand:DI 1 "register_operand" "d") (ltu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "arith_operand" "dI")))] (match_operand:DI 2 "arith_operand" "dI")))]
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%1,%2" "sltu\t%0,%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*sltu_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t,t") [(set (match_operand:DI 0 "register_operand" "=t,t")
(ltu:DI (match_operand:DI 1 "register_operand" "d,d") (ltu:DI (match_operand:DI 1 "register_operand" "d,d")
(match_operand:DI 2 "arith_operand" "d,I")))] (match_operand:DI 2 "arith_operand" "d,I")))]
"TARGET_64BIT && TARGET_MIPS16" "TARGET_64BIT && TARGET_MIPS16"
"sltu\t%1,%2" "sltu\t%1,%2"
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr_alternative "length" (set_attr_alternative "length"
[(const_int 4) [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1") (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
...@@ -6412,7 +6412,7 @@ dsrl\t%3,%3,1\n\ ...@@ -6412,7 +6412,7 @@ dsrl\t%3,%3,1\n\
DONE; DONE;
}) })
(define_insn "sleu_si_const" (define_insn "*sleu_si"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(leu:SI (match_operand:SI 1 "register_operand" "d") (leu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))] (match_operand:SI 2 "small_int" "I")))]
...@@ -6421,25 +6421,25 @@ dsrl\t%3,%3,1\n\ ...@@ -6421,25 +6421,25 @@ dsrl\t%3,%3,1\n\
operands[2] = GEN_INT (INTVAL (operands[2]) + 1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%0,%1,%2"; return "sltu\t%0,%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "" (define_insn "*sleu_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t") [(set (match_operand:SI 0 "register_operand" "=t")
(leu:SI (match_operand:SI 1 "register_operand" "d") (leu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))] (match_operand:SI 2 "small_int" "I")))]
"TARGET_MIPS16 && INTVAL (operands[2]) < 32767" "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
{ {
operands[2] = GEN_INT (INTVAL (operands[2])+1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%1,%2"; return "sltu\t%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1") (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4) (const_int 4)
(const_int 8)))]) (const_int 8)))])
(define_insn "sleu_di_const" (define_insn "*sleu_di"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(leu:DI (match_operand:DI 1 "register_operand" "d") (leu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))] (match_operand:DI 2 "small_int" "I")))]
...@@ -6448,20 +6448,20 @@ dsrl\t%3,%3,1\n\ ...@@ -6448,20 +6448,20 @@ dsrl\t%3,%3,1\n\
operands[2] = GEN_INT (INTVAL (operands[2]) + 1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%0,%1,%2"; return "sltu\t%0,%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "" (define_insn "*sleu_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t") [(set (match_operand:DI 0 "register_operand" "=t")
(leu:DI (match_operand:DI 1 "register_operand" "d") (leu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))] (match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767" "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
{ {
operands[2] = GEN_INT (INTVAL (operands[2])+1); operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%1,%2"; return "sltu\t%1,%2";
} }
[(set_attr "type" "slt") [(set_attr "type" "slt")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1") (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4) (const_int 4)
(const_int 8)))]) (const_int 8)))])
......
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