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riscv-gcc-1
Commit 9c6fdb46 by David Edelsohn Committed by David Edelsohn
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rs6000.md (neg-minus-mult): Set type to dmul. 

2005-09-23  David Edelsohn  <edelsohn@gnu.org>
	    Pete Steinmetz <steinmtz@us.ibm.com>

	* config/rs6000/rs6000.md (neg-minus-mult): Set type to dmul.
	(rldic.): Set type to "compare".
	(rldicr.): Same.
	(movsf_hardfloat): Set type to mtjmpr for MTCTR/MTLR.  Set type to
	mfjmpr for MFCTR/MFLR.
	(movdf_hardfloat64): Same.
	(movdf_softfloat64): Same.  Correct order of store and move types.
	(movti_string): Set type to store_ux/load_ux.
	(load_multiple): Set type to load_ux.
	(store_multiple): Set type to store_ux.
	(movmemsi): Set type to store_ux.
	(output_cbranch direct_return): Set type to jmpreg.
	(stmw): Set type to store_ux.
	(lmw): Set type to load_ux.
	* config/rs6000/40x.md (ppc403-store): Increase latency to 2.
	* config/rs6000/440.md (ppc440-store): Increase latency to 6.
	* config/rs6000/603.md (ppc603-store): Occupy LSU for 2 cycles.
	* config/rs6000/6xx.md (ppc604-store): Increase latency to 3.
	* config/rs6000/mpc.md (mpccore-store): Increase latency to 2.
	* config/rs6000/rios1.md (rios1-store): Increase latency to 2.
	(rios1-fpstore): Increase latency to 3.
	* config/rs6000/rios2.md (rios2-store): Increase latency to 2.
	* config/rs6000/rs64.md (rs64a-store): Increase latency to 2.

Co-Authored-By: Pete Steinmetz <steinmtz@us.ibm.com>

From-SVN: r104568
parent 66684b7e
Showing with 77 additions and 48 deletions
gcc/ChangeLog
2005-09-23 David Edelsohn <edelsohn@gnu.org> 2005-09-23 David Edelsohn <edelsohn@gnu.org>
Pete Steinmetz <steinmtz@us.ibm.com>
* config/rs6000/rs6000.md (neg-minus-mult): Set type to dmul.
(rldic.): Set type to "compare".
(rldicr.): Same.
(movsf_hardfloat): Set type to mtjmpr for MTCTR/MTLR. Set type to
mfjmpr for MFCTR/MFLR.
(movdf_hardfloat64): Same.
(movdf_softfloat64): Same. Correct order of store and move types.
(movti_string): Set type to store_ux/load_ux.
(load_multiple): Set type to load_ux.
(store_multiple): Set type to store_ux.
(movmemsi): Set type to store_ux.
(output_cbranch direct_return): Set type to jmpreg.
(stmw): Set type to store_ux.
(lmw): Set type to load_ux.
* config/rs6000/40x.md (ppc403-store): Increase latency to 2.
* config/rs6000/440.md (ppc440-store): Increase latency to 6.
* config/rs6000/603.md (ppc603-store): Occupy LSU for 2 cycles.
* config/rs6000/6xx.md (ppc604-store): Increase latency to 3.
* config/rs6000/mpc.md (mpccore-store): Increase latency to 2.
* config/rs6000/rios1.md (rios1-store): Increase latency to 2.
(rios1-fpstore): Increase latency to 3.
* config/rs6000/rios2.md (rios2-store): Increase latency to 2.
* config/rs6000/rs64.md (rs64a-store): Increase latency to 2.
2005-09-23 David Edelsohn <edelsohn@gnu.org>
Andrew Pinski <pinskia@physics.uc.edu> Andrew Pinski <pinskia@physics.uc.edu>
* config/rs6000/sync.md (sync_<fetchop_name>si_internal): Change * config/rs6000/sync.md (sync_<fetchop_name>si_internal): Change
......
gcc/config/rs6000/40x.md
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
(eq_attr "cpu" "ppc403,ppc405")) (eq_attr "cpu" "ppc403,ppc405"))
"iu_40x") "iu_40x")
(define_insn_reservation "ppc403-store" 1 (define_insn_reservation "ppc403-store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc403,ppc405")) (eq_attr "cpu" "ppc403,ppc405"))
"iu_40x") "iu_40x")
......
gcc/config/rs6000/440.md
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 1 (define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
......
gcc/config/rs6000/603.md
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
(define_insn_reservation "ppc603-store" 2 (define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603") "lsu_603*2")
(define_insn_reservation "ppc603-fpload" 2 (define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
......
gcc/config/rs6000/6xx.md
...@@ -58,7 +58,7 @@ ...@@ -58,7 +58,7 @@
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
(define_insn_reservation "ppc604-store" 1 (define_insn_reservation "ppc604-store" 3
(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
......
gcc/config/rs6000/mpc.md
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
(define_insn_reservation "mpccore-store" 1 (define_insn_reservation "mpccore-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
......
gcc/config/rs6000/rios1.md
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
(eq_attr "cpu" "rios1,ppc601")) (eq_attr "cpu" "rios1,ppc601"))
"iu_rios1") "iu_rios1")
(define_insn_reservation "rios1-store" 1 (define_insn_reservation "rios1-store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "rios1,ppc601")) (eq_attr "cpu" "rios1,ppc601"))
"iu_rios1") "iu_rios1")
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_rios1") "iu_rios1")
(define_insn_reservation "rios1-fpstore" 1 (define_insn_reservation "rios1-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rios1,ppc601")) (eq_attr "cpu" "rios1,ppc601"))
"iu_rios1+fpu_rios1") "iu_rios1+fpu_rios1")
......
gcc/config/rs6000/rios2.md
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2") "iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-store" 1 (define_insn_reservation "rios2-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2") "iu1_rios2|iu2_rios2")
......
gcc/config/rs6000/rs6000.md
...@@ -4669,7 +4669,7 @@ ...@@ -4669,7 +4669,7 @@
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& ! HONOR_SIGNED_ZEROS (SFmode)" && ! HONOR_SIGNED_ZEROS (SFmode)"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "dmul")])
(define_expand "sqrtsf2" (define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
...@@ -6382,7 +6382,7 @@ ...@@ -6382,7 +6382,7 @@
"@ "@
rldic. %4,%1,%H2,%W3 rldic. %4,%1,%H2,%W3
#" #"
[(set_attr "type" "delayed_compare") [(set_attr "type" "compare")
(set_attr "length" "4,8")]) (set_attr "length" "4,8")])
(define_split (define_split
...@@ -6416,7 +6416,7 @@ ...@@ -6416,7 +6416,7 @@
"@ "@
rldic. %0,%1,%H2,%W3 rldic. %0,%1,%H2,%W3
#" #"
[(set_attr "type" "delayed_compare") [(set_attr "type" "compare")
(set_attr "length" "4,8")]) (set_attr "length" "4,8")])
(define_split (define_split
...@@ -6458,7 +6458,7 @@ ...@@ -6458,7 +6458,7 @@
"@ "@
rldicr. %4,%1,%H2,%S3 rldicr. %4,%1,%H2,%S3
#" #"
[(set_attr "type" "delayed_compare") [(set_attr "type" "compare")
(set_attr "length" "4,8")]) (set_attr "length" "4,8")])
(define_split (define_split
...@@ -6492,7 +6492,7 @@ ...@@ -6492,7 +6492,7 @@
"@ "@
rldicr. %0,%1,%H2,%S3 rldicr. %0,%1,%H2,%S3
#" #"
[(set_attr "type" "delayed_compare") [(set_attr "type" "compare")
(set_attr "length" "4,8")]) (set_attr "length" "4,8")])
(define_split (define_split
...@@ -6740,7 +6740,7 @@ ...@@ -6740,7 +6740,7 @@
# #
# #
#" #"
[(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare") [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split (define_split
...@@ -6791,7 +6791,7 @@ ...@@ -6791,7 +6791,7 @@
# #
# #
#" #"
[(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare") [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split (define_split
...@@ -7418,7 +7418,7 @@ ...@@ -7418,7 +7418,7 @@
{cror 0,0,0|nop} {cror 0,0,0|nop}
# #
#" #"
[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
(define_insn "*movsf_softfloat" (define_insn "*movsf_softfloat"
...@@ -7440,7 +7440,7 @@ ...@@ -7440,7 +7440,7 @@
# #
# #
{cror 0,0,0|nop}" {cror 0,0,0|nop}"
[(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
...@@ -7700,7 +7700,7 @@ ...@@ -7700,7 +7700,7 @@
# #
# #
#" #"
[(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat64" (define_insn "*movdf_softfloat64"
...@@ -7719,7 +7719,7 @@ ...@@ -7719,7 +7719,7 @@
# #
# #
{cror 0,0,0|nop}" {cror 0,0,0|nop}"
[(set_attr "type" "load,store,*,*,*,*,*,*,*") [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")]) (set_attr "length" "4,4,4,4,4,8,12,16,4")])
(define_expand "movtf" (define_expand "movtf"
...@@ -8153,7 +8153,7 @@ ...@@ -8153,7 +8153,7 @@
return \"#\"; return \"#\";
} }
}" }"
[(set_attr "type" "store,store,*,load,load,*")]) [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
(define_insn "*movti_ppc64" (define_insn "*movti_ppc64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
...@@ -8254,7 +8254,7 @@ ...@@ -8254,7 +8254,7 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 8" "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load") [(set_attr "type" "load_ux")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi7" (define_insn "*ldmsi7"
...@@ -8276,7 +8276,7 @@ ...@@ -8276,7 +8276,7 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 7" "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load") [(set_attr "type" "load_ux")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi6" (define_insn "*ldmsi6"
...@@ -8296,7 +8296,7 @@ ...@@ -8296,7 +8296,7 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 6" "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load") [(set_attr "type" "load_ux")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi5" (define_insn "*ldmsi5"
...@@ -8314,7 +8314,7 @@ ...@@ -8314,7 +8314,7 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 5" "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load") [(set_attr "type" "load_ux")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi4" (define_insn "*ldmsi4"
...@@ -8330,7 +8330,7 @@ ...@@ -8330,7 +8330,7 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 4" "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load") [(set_attr "type" "load_ux")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi3" (define_insn "*ldmsi3"
...@@ -8344,7 +8344,7 @@ ...@@ -8344,7 +8344,7 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 3" "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load") [(set_attr "type" "load_ux")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_expand "store_multiple" (define_expand "store_multiple"
...@@ -8421,7 +8421,7 @@ ...@@ -8421,7 +8421,7 @@
(match_operand:SI 10 "gpc_reg_operand" "r"))])] (match_operand:SI 10 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
"{stsi|stswi} %2,%1,%O0" "{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")]) [(set_attr "type" "store_ux")])
(define_insn "*stmsi7" (define_insn "*stmsi7"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -8442,7 +8442,7 @@ ...@@ -8442,7 +8442,7 @@
(match_operand:SI 9 "gpc_reg_operand" "r"))])] (match_operand:SI 9 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
"{stsi|stswi} %2,%1,%O0" "{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")]) [(set_attr "type" "store_ux")])
(define_insn "*stmsi6" (define_insn "*stmsi6"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -8461,7 +8461,7 @@ ...@@ -8461,7 +8461,7 @@
(match_operand:SI 8 "gpc_reg_operand" "r"))])] (match_operand:SI 8 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
"{stsi|stswi} %2,%1,%O0" "{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")]) [(set_attr "type" "store_ux")])
(define_insn "*stmsi5" (define_insn "*stmsi5"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -8478,7 +8478,7 @@ ...@@ -8478,7 +8478,7 @@
(match_operand:SI 7 "gpc_reg_operand" "r"))])] (match_operand:SI 7 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
"{stsi|stswi} %2,%1,%O0" "{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")]) [(set_attr "type" "store_ux")])
(define_insn "*stmsi4" (define_insn "*stmsi4"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -8493,7 +8493,7 @@ ...@@ -8493,7 +8493,7 @@
(match_operand:SI 6 "gpc_reg_operand" "r"))])] (match_operand:SI 6 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
"{stsi|stswi} %2,%1,%O0" "{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")]) [(set_attr "type" "store_ux")])
(define_insn "*stmsi3" (define_insn "*stmsi3"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -8506,7 +8506,7 @@ ...@@ -8506,7 +8506,7 @@
(match_operand:SI 5 "gpc_reg_operand" "r"))])] (match_operand:SI 5 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
"{stsi|stswi} %2,%1,%O0" "{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")]) [(set_attr "type" "store_ux")])
(define_expand "setmemsi" (define_expand "setmemsi"
[(parallel [(set (match_operand:BLK 0 "" "") [(parallel [(set (match_operand:BLK 0 "" "")
...@@ -8587,7 +8587,7 @@ ...@@ -8587,7 +8587,7 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -8611,7 +8611,7 @@ ...@@ -8611,7 +8611,7 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
;; Move up to 24 bytes at a time. The fixed registers are needed because the ;; Move up to 24 bytes at a time. The fixed registers are needed because the
...@@ -8650,7 +8650,7 @@ ...@@ -8650,7 +8650,7 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -8671,7 +8671,7 @@ ...@@ -8671,7 +8671,7 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
...@@ -8706,7 +8706,7 @@ ...@@ -8706,7 +8706,7 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -8725,7 +8725,7 @@ ...@@ -8725,7 +8725,7 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
;; Move up to 8 bytes at a time. ;; Move up to 8 bytes at a time.
...@@ -8749,7 +8749,7 @@ ...@@ -8749,7 +8749,7 @@
"TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -8762,7 +8762,7 @@ ...@@ -8762,7 +8762,7 @@
"TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
;; Move up to 4 bytes at a time. ;; Move up to 4 bytes at a time.
...@@ -8786,7 +8786,7 @@ ...@@ -8786,7 +8786,7 @@
"TARGET_STRING && TARGET_POWER "TARGET_STRING && TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -8799,7 +8799,7 @@ ...@@ -8799,7 +8799,7 @@
"TARGET_STRING && ! TARGET_POWER "TARGET_STRING && ! TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load") [(set_attr "type" "store_ux")
(set_attr "length" "8")]) (set_attr "length" "8")])
;; Define insns that do load or store with update. Some of these we can ;; Define insns that do load or store with update. Some of these we can
...@@ -12825,7 +12825,7 @@ ...@@ -12825,7 +12825,7 @@
{ {
return output_cbranch (operands[0], NULL, 0, insn); return output_cbranch (operands[0], NULL, 0, insn);
}" }"
[(set_attr "type" "branch") [(set_attr "type" "jmpreg")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "" (define_insn ""
...@@ -12856,7 +12856,7 @@ ...@@ -12856,7 +12856,7 @@
{ {
return output_cbranch (operands[0], NULL, 1, insn); return output_cbranch (operands[0], NULL, 1, insn);
}" }"
[(set_attr "type" "branch") [(set_attr "type" "jmpreg")
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Logic on condition register values. ;; Logic on condition register values.
...@@ -13327,7 +13327,8 @@ ...@@ -13327,7 +13327,8 @@
[(set (match_operand:SI 1 "memory_operand" "=m") [(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r"))])] (match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE" "TARGET_MULTIPLE"
"{stm|stmw} %2,%1") "{stm|stmw} %2,%1"
[(set_attr "type" "store_ux")])
(define_insn "*save_fpregs_<mode>" (define_insn "*save_fpregs_<mode>"
[(match_parallel 0 "any_parallel_operand" [(match_parallel 0 "any_parallel_operand"
...@@ -13402,14 +13403,15 @@ ...@@ -13402,14 +13403,15 @@
; The load-multiple instructions have similar properties. ; The load-multiple instructions have similar properties.
; Note that "load_multiple" is a name known to the machine-independent ; Note that "load_multiple" is a name known to the machine-independent
; code that actually corresponds to the powerpc load-string. ; code that actually corresponds to the PowerPC load-string.
(define_insn "*lmw" (define_insn "*lmw"
[(match_parallel 0 "lmw_operation" [(match_parallel 0 "lmw_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r") [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "memory_operand" "m"))])] (match_operand:SI 2 "memory_operand" "m"))])]
"TARGET_MULTIPLE" "TARGET_MULTIPLE"
"{lm|lmw} %1,%2") "{lm|lmw} %1,%2"
[(set_attr "type" "load_ux")])
(define_insn "*return_internal_<mode>" (define_insn "*return_internal_<mode>"
[(return) [(return)
......
gcc/config/rs6000/rs64.md
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
(define_insn_reservation "rs64a-store" 1 (define_insn_reservation "rs64a-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
......
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