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riscv-gcc-1
Commit 9bddde52 by Aldy Hernandez Committed by Aldy Hernandez
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rs6000.md: Use spaces instead of tabs in output templates. 

      * config/rs6000/rs6000.md: Use spaces instead of tabs in output
        templates.

From-SVN: r47059
parent fea54805
Showing with 125 additions and 120 deletions
gcc/ChangeLog
2001-11-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md: Use spaces instead of tabs in output
templates.
Thu Nov 15 08:36:39 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu> Thu Nov 15 08:36:39 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
* final.c (alter_subreg): If simplify_subreg can't do anything, * final.c (alter_subreg): If simplify_subreg can't do anything,
......
gcc/config/rs6000/rs6000.md
...@@ -13369,7 +13369,7 @@ ...@@ -13369,7 +13369,7 @@
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))] (match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvx\t%0,%y1" "lvx %0,%y1"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
;; Generic STVX store instruction. ;; Generic STVX store instruction.
...@@ -13377,7 +13377,7 @@ ...@@ -13377,7 +13377,7 @@
[(set (match_operand:V4SI 0 "memory_operand" "=m") [(set (match_operand:V4SI 0 "memory_operand" "=m")
(match_operand:V4SI 1 "register_operand" "v"))] (match_operand:V4SI 1 "register_operand" "v"))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"stvx\t%1,%y0" "stvx %1,%y0"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
;; Vector move instructions. ;; Vector move instructions.
...@@ -13392,9 +13392,9 @@ ...@@ -13392,9 +13392,9 @@
(match_operand:V4SI 1 "input_operand" "v,m,v"))] (match_operand:V4SI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"@ "@
stvx\t%1,%y0 stvx %1,%y0
ldvx\t%0,%y1 ldvx %0,%y1
vor\t%0,%1,%1" vor %0,%1,%1"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_expand "movv8hi" (define_expand "movv8hi"
...@@ -13408,9 +13408,9 @@ ...@@ -13408,9 +13408,9 @@
(match_operand:V8HI 1 "input_operand" "v,m,v"))] (match_operand:V8HI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"@ "@
stvx\t%1,%y0 stvx %1,%y0
ldvx\t%0,%y1 ldvx %0,%y1
vor\t%0,%1,%1" vor %0,%1,%1"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_expand "movv16qi" (define_expand "movv16qi"
...@@ -13424,9 +13424,9 @@ ...@@ -13424,9 +13424,9 @@
(match_operand:V16QI 1 "input_operand" "v,m,v"))] (match_operand:V16QI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"@ "@
stvx\t%1,%y0 stvx %1,%y0
ldvx\t%0,%y1 ldvx %0,%y1
vor\t%0,%1,%1" vor %0,%1,%1"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_expand "movv4sf" (define_expand "movv4sf"
...@@ -13440,9 +13440,9 @@ ...@@ -13440,9 +13440,9 @@
(match_operand:V4SF 1 "input_operand" "v,m,v"))] (match_operand:V4SF 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"@ "@
stvx\t%1,%y0 stvx %1,%y0
ldvx\t%0,%y1 ldvx %0,%y1
vor\t%0,%1,%1" vor %0,%1,%1"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
;; Simple binary operations. ;; Simple binary operations.
...@@ -13452,7 +13452,7 @@ ...@@ -13452,7 +13452,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 31))] (match_operand:V16QI 2 "register_operand" "v")] 31))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddubm\t%0,%1,%2" "vaddubm %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vadduhm" (define_insn "altivec_vadduhm"
...@@ -13460,7 +13460,7 @@ ...@@ -13460,7 +13460,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 32))] (match_operand:V8HI 2 "register_operand" "v")] 32))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vadduhm\t%0,%1,%2" "vadduhm %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vadduwm" (define_insn "altivec_vadduwm"
...@@ -13468,7 +13468,7 @@ ...@@ -13468,7 +13468,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 33))] (match_operand:V4SI 2 "register_operand" "v")] 33))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vadduwm\t%0,%1,%2" "vadduwm %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vaddfp" (define_insn "altivec_vaddfp"
...@@ -13476,7 +13476,7 @@ ...@@ -13476,7 +13476,7 @@
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 34))] (match_operand:V4SF 2 "register_operand" "v")] 34))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddfp\t%0,%1,%2" "vaddfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vaddcuw" (define_insn "altivec_vaddcuw"
...@@ -13484,7 +13484,7 @@ ...@@ -13484,7 +13484,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 35))] (match_operand:V4SI 2 "register_operand" "v")] 35))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddcuw\t%0,%1,%2" "vaddcuw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vaddubs" (define_insn "altivec_vaddubs"
...@@ -13492,7 +13492,7 @@ ...@@ -13492,7 +13492,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 36))] (match_operand:V16QI 2 "register_operand" "v")] 36))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddubs\t%0,%1,%2" "vaddubs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vaddsbs" (define_insn "altivec_vaddsbs"
...@@ -13500,7 +13500,7 @@ ...@@ -13500,7 +13500,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 37))] (match_operand:V16QI 2 "register_operand" "v")] 37))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddsbs\t%0,%1,%2" "vaddsbs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vadduhs" (define_insn "altivec_vadduhs"
...@@ -13508,7 +13508,7 @@ ...@@ -13508,7 +13508,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 38))] (match_operand:V8HI 2 "register_operand" "v")] 38))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vadduhs\t%0,%1,%2" "vadduhs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vaddshs" (define_insn "altivec_vaddshs"
...@@ -13516,7 +13516,7 @@ ...@@ -13516,7 +13516,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 39))] (match_operand:V8HI 2 "register_operand" "v")] 39))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddshs\t%0,%1,%2" "vaddshs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vadduws" (define_insn "altivec_vadduws"
...@@ -13524,7 +13524,7 @@ ...@@ -13524,7 +13524,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 40))] (match_operand:V4SI 2 "register_operand" "v")] 40))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vadduws\t%0,%1,%2" "vadduws %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vaddsws" (define_insn "altivec_vaddsws"
...@@ -13532,7 +13532,7 @@ ...@@ -13532,7 +13532,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 41))] (match_operand:V4SI 2 "register_operand" "v")] 41))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vaddsws\t%0,%1,%2" "vaddsws %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vand" (define_insn "altivec_vand"
...@@ -13540,7 +13540,7 @@ ...@@ -13540,7 +13540,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 42))] (match_operand:V4SI 2 "register_operand" "v")] 42))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vand\t%0,%1,%2" "vand %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vandc" (define_insn "altivec_vandc"
...@@ -13548,7 +13548,7 @@ ...@@ -13548,7 +13548,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 43))] (match_operand:V4SI 2 "register_operand" "v")] 43))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vandc\t%0,%1,%2" "vandc %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vavgub" (define_insn "altivec_vavgub"
...@@ -13556,7 +13556,7 @@ ...@@ -13556,7 +13556,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 44))] (match_operand:V16QI 2 "register_operand" "v")] 44))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vavgub\t%0,%1,%2" "vavgub %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vavgsb" (define_insn "altivec_vavgsb"
...@@ -13564,7 +13564,7 @@ ...@@ -13564,7 +13564,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 45))] (match_operand:V16QI 2 "register_operand" "v")] 45))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vavgsb\t%0,%1,%2" "vavgsb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vavguh" (define_insn "altivec_vavguh"
...@@ -13572,7 +13572,7 @@ ...@@ -13572,7 +13572,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 46))] (match_operand:V8HI 2 "register_operand" "v")] 46))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vavguh\t%0,%1,%2" "vavguh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vavgsh" (define_insn "altivec_vavgsh"
...@@ -13580,7 +13580,7 @@ ...@@ -13580,7 +13580,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 47))] (match_operand:V8HI 2 "register_operand" "v")] 47))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vavgsh\t%0,%1,%2" "vavgsh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vavguw" (define_insn "altivec_vavguw"
...@@ -13588,7 +13588,7 @@ ...@@ -13588,7 +13588,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 48))] (match_operand:V4SI 2 "register_operand" "v")] 48))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vavguw\t%0,%1,%2" "vavguw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vavgsw" (define_insn "altivec_vavgsw"
...@@ -13596,7 +13596,7 @@ ...@@ -13596,7 +13596,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 49))] (match_operand:V4SI 2 "register_operand" "v")] 49))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vavgsw\t%0,%1,%2" "vavgsw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpbfp" (define_insn "altivec_vcmpbfp"
...@@ -13604,7 +13604,7 @@ ...@@ -13604,7 +13604,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 50))] (match_operand:V4SF 2 "register_operand" "v")] 50))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpbfp\t%0,%1,%2" "vcmpbfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequb" (define_insn "altivec_vcmpequb"
...@@ -13612,7 +13612,7 @@ ...@@ -13612,7 +13612,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 51))] (match_operand:V16QI 2 "register_operand" "v")] 51))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpequb\t%0,%1,%2" "vcmpequb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequh" (define_insn "altivec_vcmpequh"
...@@ -13620,7 +13620,7 @@ ...@@ -13620,7 +13620,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 52))] (match_operand:V8HI 2 "register_operand" "v")] 52))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpequh\t%0,%1,%2" "vcmpequh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequw" (define_insn "altivec_vcmpequw"
...@@ -13628,7 +13628,7 @@ ...@@ -13628,7 +13628,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 53))] (match_operand:V4SI 2 "register_operand" "v")] 53))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpequw\t%0,%1,%2" "vcmpequw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpeqfp" (define_insn "altivec_vcmpeqfp"
...@@ -13636,7 +13636,7 @@ ...@@ -13636,7 +13636,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 54))] (match_operand:V4SF 2 "register_operand" "v")] 54))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpeqfp\t%0,%1,%2" "vcmpeqfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgefp" (define_insn "altivec_vcmpgefp"
...@@ -13644,7 +13644,7 @@ ...@@ -13644,7 +13644,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 55))] (match_operand:V4SF 2 "register_operand" "v")] 55))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgefp\t%0,%1,%2" "vcmpgefp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtub" (define_insn "altivec_vcmpgtub"
...@@ -13652,7 +13652,7 @@ ...@@ -13652,7 +13652,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 56))] (match_operand:V16QI 2 "register_operand" "v")] 56))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtub\t%0,%1,%2" "vcmpgtub %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsb" (define_insn "altivec_vcmpgtsb"
...@@ -13660,7 +13660,7 @@ ...@@ -13660,7 +13660,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 57))] (match_operand:V16QI 2 "register_operand" "v")] 57))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtsb\t%0,%1,%2" "vcmpgtsb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuh" (define_insn "altivec_vcmpgtuh"
...@@ -13668,7 +13668,7 @@ ...@@ -13668,7 +13668,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 58))] (match_operand:V8HI 2 "register_operand" "v")] 58))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtuh\t%0,%1,%2" "vcmpgtuh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsh" (define_insn "altivec_vcmpgtsh"
...@@ -13676,7 +13676,7 @@ ...@@ -13676,7 +13676,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 59))] (match_operand:V8HI 2 "register_operand" "v")] 59))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtsh\t%0,%1,%2" "vcmpgtsh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuw" (define_insn "altivec_vcmpgtuw"
...@@ -13684,7 +13684,7 @@ ...@@ -13684,7 +13684,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 60))] (match_operand:V4SI 2 "register_operand" "v")] 60))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtuw\t%0,%1,%2" "vcmpgtuw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsw" (define_insn "altivec_vcmpgtsw"
...@@ -13692,7 +13692,7 @@ ...@@ -13692,7 +13692,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 61))] (match_operand:V4SI 2 "register_operand" "v")] 61))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtsw\t%0,%1,%2" "vcmpgtsw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtfp" (define_insn "altivec_vcmpgtfp"
...@@ -13700,7 +13700,7 @@ ...@@ -13700,7 +13700,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 62))] (match_operand:V4SF 2 "register_operand" "v")] 62))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vcmpgtfp\t%0,%1,%2" "vcmpgtfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxub" (define_insn "altivec_vmaxub"
...@@ -13708,7 +13708,7 @@ ...@@ -13708,7 +13708,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 63))] (match_operand:V16QI 2 "register_operand" "v")] 63))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxub\t%0,%1,%2" "vmaxub %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsb" (define_insn "altivec_vmaxsb"
...@@ -13716,7 +13716,7 @@ ...@@ -13716,7 +13716,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 64))] (match_operand:V16QI 2 "register_operand" "v")] 64))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxsb\t%0,%1,%2" "vmaxsb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxuh" (define_insn "altivec_vmaxuh"
...@@ -13724,7 +13724,7 @@ ...@@ -13724,7 +13724,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 65))] (match_operand:V8HI 2 "register_operand" "v")] 65))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxuh\t%0,%1,%2" "vmaxuh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsh" (define_insn "altivec_vmaxsh"
...@@ -13732,7 +13732,7 @@ ...@@ -13732,7 +13732,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 66))] (match_operand:V8HI 2 "register_operand" "v")] 66))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxsh\t%0,%1,%2" "vmaxsh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxuw" (define_insn "altivec_vmaxuw"
...@@ -13740,7 +13740,7 @@ ...@@ -13740,7 +13740,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 67))] (match_operand:V4SI 2 "register_operand" "v")] 67))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxuw\t%0,%1,%2" "vmaxuw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsw" (define_insn "altivec_vmaxsw"
...@@ -13748,7 +13748,7 @@ ...@@ -13748,7 +13748,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 68))] (match_operand:V4SI 2 "register_operand" "v")] 68))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxsw\t%0,%1,%2" "vmaxsw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmaxfp" (define_insn "altivec_vmaxfp"
...@@ -13756,7 +13756,7 @@ ...@@ -13756,7 +13756,7 @@
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 69))] (match_operand:V4SF 2 "register_operand" "v")] 69))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmaxfp\t%0,%1,%2" "vmaxfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmrghb" (define_insn "altivec_vmrghb"
...@@ -13764,7 +13764,7 @@ ...@@ -13764,7 +13764,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 70))] (match_operand:V16QI 2 "register_operand" "v")] 70))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmrghb\t%0,%1,%2" "vmrghb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmrghh" (define_insn "altivec_vmrghh"
...@@ -13772,7 +13772,7 @@ ...@@ -13772,7 +13772,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 71))] (match_operand:V8HI 2 "register_operand" "v")] 71))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmrghh\t%0,%1,%2" "vmrghh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmrghw" (define_insn "altivec_vmrghw"
...@@ -13780,7 +13780,7 @@ ...@@ -13780,7 +13780,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 72))] (match_operand:V4SI 2 "register_operand" "v")] 72))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmrghw\t%0,%1,%2" "vmrghw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmrglb" (define_insn "altivec_vmrglb"
...@@ -13788,7 +13788,7 @@ ...@@ -13788,7 +13788,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 73))] (match_operand:V16QI 2 "register_operand" "v")] 73))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmrglb\t%0,%1,%2" "vmrglb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmrglh" (define_insn "altivec_vmrglh"
...@@ -13796,7 +13796,7 @@ ...@@ -13796,7 +13796,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 74))] (match_operand:V8HI 2 "register_operand" "v")] 74))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmrglh\t%0,%1,%2" "vmrglh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmrglw" (define_insn "altivec_vmrglw"
...@@ -13804,7 +13804,7 @@ ...@@ -13804,7 +13804,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 75))] (match_operand:V4SI 2 "register_operand" "v")] 75))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmrglw\t%0,%1,%2" "vmrglw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminub" (define_insn "altivec_vminub"
...@@ -13812,7 +13812,7 @@ ...@@ -13812,7 +13812,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 76))] (match_operand:V16QI 2 "register_operand" "v")] 76))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminub\t%0,%1,%2" "vminub %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminsb" (define_insn "altivec_vminsb"
...@@ -13820,7 +13820,7 @@ ...@@ -13820,7 +13820,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 77))] (match_operand:V16QI 2 "register_operand" "v")] 77))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminsb\t%0,%1,%2" "vminsb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminuh" (define_insn "altivec_vminuh"
...@@ -13828,7 +13828,7 @@ ...@@ -13828,7 +13828,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 78))] (match_operand:V8HI 2 "register_operand" "v")] 78))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminuh\t%0,%1,%2" "vminuh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminsh" (define_insn "altivec_vminsh"
...@@ -13836,7 +13836,7 @@ ...@@ -13836,7 +13836,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 79))] (match_operand:V8HI 2 "register_operand" "v")] 79))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminsh\t%0,%1,%2" "vminsh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminuw" (define_insn "altivec_vminuw"
...@@ -13844,7 +13844,7 @@ ...@@ -13844,7 +13844,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 80))] (match_operand:V4SI 2 "register_operand" "v")] 80))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminuw\t%0,%1,%2" "vminuw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminsw" (define_insn "altivec_vminsw"
...@@ -13852,7 +13852,7 @@ ...@@ -13852,7 +13852,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 81))] (match_operand:V4SI 2 "register_operand" "v")] 81))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminsw\t%0,%1,%2" "vminsw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vminfp" (define_insn "altivec_vminfp"
...@@ -13860,7 +13860,7 @@ ...@@ -13860,7 +13860,7 @@
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 82))] (match_operand:V4SF 2 "register_operand" "v")] 82))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vminfp\t%0,%1,%2" "vminfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmuleub" (define_insn "altivec_vmuleub"
...@@ -13868,7 +13868,7 @@ ...@@ -13868,7 +13868,7 @@
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 83))] (match_operand:V16QI 2 "register_operand" "v")] 83))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmuleub\t%0,%1,%2" "vmuleub %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmulesb" (define_insn "altivec_vmulesb"
...@@ -13876,7 +13876,7 @@ ...@@ -13876,7 +13876,7 @@
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 84))] (match_operand:V16QI 2 "register_operand" "v")] 84))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmulesb\t%0,%1,%2" "vmulesb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmuleuh" (define_insn "altivec_vmuleuh"
...@@ -13884,7 +13884,7 @@ ...@@ -13884,7 +13884,7 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 85))] (match_operand:V8HI 2 "register_operand" "v")] 85))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmuleuh\t%0,%1,%2" "vmuleuh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmulesh" (define_insn "altivec_vmulesh"
...@@ -13892,7 +13892,7 @@ ...@@ -13892,7 +13892,7 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 86))] (match_operand:V8HI 2 "register_operand" "v")] 86))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmulesh\t%0,%1,%2" "vmulesh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmuloub" (define_insn "altivec_vmuloub"
...@@ -13900,7 +13900,7 @@ ...@@ -13900,7 +13900,7 @@
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 87))] (match_operand:V16QI 2 "register_operand" "v")] 87))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmuloub\t%0,%1,%2" "vmuloub %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmulosb" (define_insn "altivec_vmulosb"
...@@ -13908,7 +13908,7 @@ ...@@ -13908,7 +13908,7 @@
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 88))] (match_operand:V16QI 2 "register_operand" "v")] 88))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmulosb\t%0,%1,%2" "vmulosb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmulouh" (define_insn "altivec_vmulouh"
...@@ -13916,7 +13916,7 @@ ...@@ -13916,7 +13916,7 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 89))] (match_operand:V8HI 2 "register_operand" "v")] 89))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmulouh\t%0,%1,%2" "vmulouh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vmulosh" (define_insn "altivec_vmulosh"
...@@ -13924,7 +13924,7 @@ ...@@ -13924,7 +13924,7 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 90))] (match_operand:V8HI 2 "register_operand" "v")] 90))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vmulosh\t%0,%1,%2" "vmulosh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vnor" (define_insn "altivec_vnor"
...@@ -13932,7 +13932,7 @@ ...@@ -13932,7 +13932,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 91))] (match_operand:V4SI 2 "register_operand" "v")] 91))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vnor\t%0,%1,%2" "vnor %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vor" (define_insn "altivec_vor"
...@@ -13940,7 +13940,7 @@ ...@@ -13940,7 +13940,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 92))] (match_operand:V4SI 2 "register_operand" "v")] 92))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vor\t%0,%1,%2" "vor %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhum" (define_insn "altivec_vpkuhum"
...@@ -13948,7 +13948,7 @@ ...@@ -13948,7 +13948,7 @@
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 93))] (match_operand:V8HI 2 "register_operand" "v")] 93))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkuhum\t%0,%1,%2" "vpkuhum %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwum" (define_insn "altivec_vpkuwum"
...@@ -13956,7 +13956,7 @@ ...@@ -13956,7 +13956,7 @@
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 94))] (match_operand:V4SI 2 "register_operand" "v")] 94))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkuwum\t%0,%1,%2" "vpkuwum %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkpx" (define_insn "altivec_vpkpx"
...@@ -13964,7 +13964,7 @@ ...@@ -13964,7 +13964,7 @@
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 95))] (match_operand:V4SI 2 "register_operand" "v")] 95))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkpx\t%0,%1,%2" "vpkpx %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhss" (define_insn "altivec_vpkuhss"
...@@ -13972,7 +13972,7 @@ ...@@ -13972,7 +13972,7 @@
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 96))] (match_operand:V8HI 2 "register_operand" "v")] 96))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkuhss\t%0,%1,%2" "vpkuhss %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkshss" (define_insn "altivec_vpkshss"
...@@ -13980,7 +13980,7 @@ ...@@ -13980,7 +13980,7 @@
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 97))] (match_operand:V8HI 2 "register_operand" "v")] 97))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkshss\t%0,%1,%2" "vpkshss %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwss" (define_insn "altivec_vpkuwss"
...@@ -13988,7 +13988,7 @@ ...@@ -13988,7 +13988,7 @@
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 98))] (match_operand:V4SI 2 "register_operand" "v")] 98))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkuwss\t%0,%1,%2" "vpkuwss %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkswss" (define_insn "altivec_vpkswss"
...@@ -13996,7 +13996,7 @@ ...@@ -13996,7 +13996,7 @@
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 99))] (match_operand:V4SI 2 "register_operand" "v")] 99))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkswss\t%0,%1,%2" "vpkswss %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhus" (define_insn "altivec_vpkuhus"
...@@ -14004,7 +14004,7 @@ ...@@ -14004,7 +14004,7 @@
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 100))] (match_operand:V8HI 2 "register_operand" "v")] 100))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkuhus\t%0,%1,%2" "vpkuhus %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkshus" (define_insn "altivec_vpkshus"
...@@ -14012,7 +14012,7 @@ ...@@ -14012,7 +14012,7 @@
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 101))] (match_operand:V8HI 2 "register_operand" "v")] 101))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkshus\t%0,%1,%2" "vpkshus %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwus" (define_insn "altivec_vpkuwus"
...@@ -14020,7 +14020,7 @@ ...@@ -14020,7 +14020,7 @@
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 102))] (match_operand:V4SI 2 "register_operand" "v")] 102))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkuwus\t%0,%1,%2" "vpkuwus %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vpkswus" (define_insn "altivec_vpkswus"
...@@ -14028,7 +14028,7 @@ ...@@ -14028,7 +14028,7 @@
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 103))] (match_operand:V4SI 2 "register_operand" "v")] 103))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vpkswus\t%0,%1,%2" "vpkswus %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vrlb" (define_insn "altivec_vrlb"
...@@ -14036,7 +14036,7 @@ ...@@ -14036,7 +14036,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 104))] (match_operand:V16QI 2 "register_operand" "v")] 104))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vrlb\t%0,%1,%2" "vrlb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vrlh" (define_insn "altivec_vrlh"
...@@ -14044,7 +14044,7 @@ ...@@ -14044,7 +14044,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 105))] (match_operand:V8HI 2 "register_operand" "v")] 105))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vrlh\t%0,%1,%2" "vrlh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vrlw" (define_insn "altivec_vrlw"
...@@ -14052,7 +14052,7 @@ ...@@ -14052,7 +14052,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 106))] (match_operand:V4SI 2 "register_operand" "v")] 106))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vrlw\t%0,%1,%2" "vrlw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vslb" (define_insn "altivec_vslb"
...@@ -14060,7 +14060,7 @@ ...@@ -14060,7 +14060,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 107))] (match_operand:V16QI 2 "register_operand" "v")] 107))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vslb\t%0,%1,%2" "vslb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vslh" (define_insn "altivec_vslh"
...@@ -14068,7 +14068,7 @@ ...@@ -14068,7 +14068,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 108))] (match_operand:V8HI 2 "register_operand" "v")] 108))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vslh\t%0,%1,%2" "vslh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vslw" (define_insn "altivec_vslw"
...@@ -14076,7 +14076,7 @@ ...@@ -14076,7 +14076,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 109))] (match_operand:V4SI 2 "register_operand" "v")] 109))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vslw\t%0,%1,%2" "vslw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsl" (define_insn "altivec_vsl"
...@@ -14084,7 +14084,7 @@ ...@@ -14084,7 +14084,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 110))] (match_operand:V4SI 2 "register_operand" "v")] 110))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsl\t%0,%1,%2" "vsl %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vslo" (define_insn "altivec_vslo"
...@@ -14092,7 +14092,7 @@ ...@@ -14092,7 +14092,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 111))] (match_operand:V4SI 2 "register_operand" "v")] 111))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vslo\t%0,%1,%2" "vslo %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsrb" (define_insn "altivec_vsrb"
...@@ -14100,7 +14100,7 @@ ...@@ -14100,7 +14100,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 112))] (match_operand:V16QI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsrb\t%0,%1,%2" "vsrb %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vrsh" (define_insn "altivec_vrsh"
...@@ -14108,7 +14108,7 @@ ...@@ -14108,7 +14108,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 113))] (match_operand:V8HI 2 "register_operand" "v")] 113))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vrsh\t%0,%1,%2" "vrsh %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vrsw" (define_insn "altivec_vrsw"
...@@ -14116,7 +14116,7 @@ ...@@ -14116,7 +14116,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 114))] (match_operand:V4SI 2 "register_operand" "v")] 114))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vrsw\t%0,%1,%2" "vrsw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsrab" (define_insn "altivec_vsrab"
...@@ -14124,7 +14124,7 @@ ...@@ -14124,7 +14124,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 115))] (match_operand:V16QI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsrab\t%0,%1,%2" "vsrab %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsrah" (define_insn "altivec_vsrah"
...@@ -14132,7 +14132,7 @@ ...@@ -14132,7 +14132,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 116))] (match_operand:V8HI 2 "register_operand" "v")] 116))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsrah\t%0,%1,%2" "vsrah %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsraw" (define_insn "altivec_vsraw"
...@@ -14140,7 +14140,7 @@ ...@@ -14140,7 +14140,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 117))] (match_operand:V4SI 2 "register_operand" "v")] 117))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsraw\t%0,%1,%2" "vsraw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsr" (define_insn "altivec_vsr"
...@@ -14148,7 +14148,7 @@ ...@@ -14148,7 +14148,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 118))] (match_operand:V4SI 2 "register_operand" "v")] 118))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsr\t%0,%1,%2" "vsr %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsro" (define_insn "altivec_vsro"
...@@ -14156,7 +14156,7 @@ ...@@ -14156,7 +14156,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 119))] (match_operand:V4SI 2 "register_operand" "v")] 119))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsro\t%0,%1,%2" "vsro %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsububm" (define_insn "altivec_vsububm"
...@@ -14164,7 +14164,7 @@ ...@@ -14164,7 +14164,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 120))] (match_operand:V16QI 2 "register_operand" "v")] 120))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsububm\t%0,%1,%2" "vsububm %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhm" (define_insn "altivec_vsubuhm"
...@@ -14172,7 +14172,7 @@ ...@@ -14172,7 +14172,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 121))] (match_operand:V8HI 2 "register_operand" "v")] 121))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubuhm\t%0,%1,%2" "vsubuhm %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubuwm" (define_insn "altivec_vsubuwm"
...@@ -14180,7 +14180,7 @@ ...@@ -14180,7 +14180,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 122))] (match_operand:V4SI 2 "register_operand" "v")] 122))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubuwm\t%0,%1,%2" "vsubuwm %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubfp" (define_insn "altivec_vsubfp"
...@@ -14188,7 +14188,7 @@ ...@@ -14188,7 +14188,7 @@
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 123))] (match_operand:V4SF 2 "register_operand" "v")] 123))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubfp\t%0,%1,%2" "vsubfp %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubcuw" (define_insn "altivec_vsubcuw"
...@@ -14196,7 +14196,7 @@ ...@@ -14196,7 +14196,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 124))] (match_operand:V4SI 2 "register_operand" "v")] 124))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubcuw\t%0,%1,%2" "vsubcuw %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsububs" (define_insn "altivec_vsububs"
...@@ -14204,7 +14204,7 @@ ...@@ -14204,7 +14204,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 125))] (match_operand:V16QI 2 "register_operand" "v")] 125))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsububs\t%0,%1,%2" "vsububs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubsbs" (define_insn "altivec_vsubsbs"
...@@ -14212,7 +14212,7 @@ ...@@ -14212,7 +14212,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 126))] (match_operand:V16QI 2 "register_operand" "v")] 126))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubsbs\t%0,%1,%2" "vsubsbs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhs" (define_insn "altivec_vsubuhs"
...@@ -14220,7 +14220,7 @@ ...@@ -14220,7 +14220,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 127))] (match_operand:V8HI 2 "register_operand" "v")] 127))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubuhs\t%0,%1,%2" "vsubuhs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubshs" (define_insn "altivec_vsubshs"
...@@ -14228,7 +14228,7 @@ ...@@ -14228,7 +14228,7 @@
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 128))] (match_operand:V8HI 2 "register_operand" "v")] 128))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubshs\t%0,%1,%2" "vsubshs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubuws" (define_insn "altivec_vsubuws"
...@@ -14236,7 +14236,7 @@ ...@@ -14236,7 +14236,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 129))] (match_operand:V4SI 2 "register_operand" "v")] 129))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubuws\t%0,%1,%2" "vsubuws %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsubsws" (define_insn "altivec_vsubsws"
...@@ -14244,7 +14244,7 @@ ...@@ -14244,7 +14244,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 130))] (match_operand:V4SI 2 "register_operand" "v")] 130))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsubsws\t%0,%1,%2" "vsubsws %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsum4ubs" (define_insn "altivec_vsum4ubs"
...@@ -14252,7 +14252,7 @@ ...@@ -14252,7 +14252,7 @@
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 131))] (match_operand:V4SI 2 "register_operand" "v")] 131))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsum4ubs\t%0,%1,%2" "vsum4ubs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsum4sbs" (define_insn "altivec_vsum4sbs"
...@@ -14260,7 +14260,7 @@ ...@@ -14260,7 +14260,7 @@
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 132))] (match_operand:V4SI 2 "register_operand" "v")] 132))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsum4sbs\t%0,%1,%2" "vsum4sbs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsum4shs" (define_insn "altivec_vsum4shs"
...@@ -14268,7 +14268,7 @@ ...@@ -14268,7 +14268,7 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 133))] (match_operand:V4SI 2 "register_operand" "v")] 133))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsum4shs\t%0,%1,%2" "vsum4shs %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsum2sws" (define_insn "altivec_vsum2sws"
...@@ -14276,7 +14276,7 @@ ...@@ -14276,7 +14276,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 134))] (match_operand:V4SI 2 "register_operand" "v")] 134))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsum2sws\t%0,%1,%2" "vsum2sws %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vsumsws" (define_insn "altivec_vsumsws"
...@@ -14284,7 +14284,7 @@ ...@@ -14284,7 +14284,7 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 135))] (match_operand:V4SI 2 "register_operand" "v")] 135))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vsumsws\t%0,%1,%2" "vsumsws %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
(define_insn "altivec_vxor" (define_insn "altivec_vxor"
...@@ -14292,5 +14292,5 @@ ...@@ -14292,5 +14292,5 @@
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 136))] (match_operand:V4SI 2 "register_operand" "v")] 136))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"vxor\t%0,%1,%2" "vxor %0,%1,%2"
[(set_attr "type" "altivec")]) [(set_attr "type" "altivec")])
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