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Commit 99d85f91 by James Greenhalgh Committed by James Greenhalgh
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[AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2" tuning options. 

gcc/
	* config/aarch64/aarch64-cores.def (example-1): Remove.
	(example-2): Likewise.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* config/aarch64/aarch64.md: Do not include "large.md" or "small.md".
	(generic_sched): Remove "large", "small".
	* config/aarch64/large.md: Delete.
	* config/aarch64/small.md: Delete.

gcc/testsuite/
	* gcc.target/aarch64/cpu-diagnostics-2.c: Change "-mcpu="
	to "cortex-a53".
	* gcc.target/aarch64/cpu-diagnostics-3.c: Change "-mcpu="
	to "cortex-a53".

From-SVN: r204784
parent 1763249f
Showing with 21 additions and 607 deletions
gcc/ChangeLog
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com> 2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-cores.def (example-1): Remove.
(example-2): Likewise.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.md: Do not include "large.md" or "small.md".
(generic_sched): Remove "large", "small".
* config/aarch64/large.md: Delete.
* config/aarch64/small.md: Delete.
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-cores.def (cortex-a57): Tune for cortexa15. * config/aarch64/aarch64-cores.def (cortex-a57): Tune for cortexa15.
* config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.md: Include cortex-a15 pipeline model. * config/aarch64/aarch64.md: Include cortex-a15 pipeline model.
gcc/config/aarch64/aarch64-cores.def
...@@ -36,5 +36,3 @@ ...@@ -36,5 +36,3 @@
AARCH64_CORE("cortex-a53", cortexa53, 8, AARCH64_FL_FPSIMD, generic) AARCH64_CORE("cortex-a53", cortexa53, 8, AARCH64_FL_FPSIMD, generic)
AARCH64_CORE("cortex-a57", cortexa15, 8, AARCH64_FL_FPSIMD, generic) AARCH64_CORE("cortex-a57", cortexa15, 8, AARCH64_FL_FPSIMD, generic)
AARCH64_CORE("example-1", large, 8, AARCH64_FL_FPSIMD, generic)
AARCH64_CORE("example-2", small, 8, AARCH64_FL_FPSIMD, generic)
gcc/config/aarch64/aarch64-tune.md
;; -*- buffer-read-only: t -*- ;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def ;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune" (define_attr "tune"
"cortexa53,cortexa15,large,small" "cortexa53,cortexa15"
(const (symbol_ref "((enum attr_tune) aarch64_tune)"))) (const (symbol_ref "((enum attr_tune) aarch64_tune)")))
gcc/config/aarch64/aarch64.md
...@@ -312,13 +312,11 @@ ...@@ -312,13 +312,11 @@
(define_attr "generic_sched" "yes,no" (define_attr "generic_sched" "yes,no"
(const (if_then_else (const (if_then_else
(eq_attr "tune" "large,small,cortexa53,cortexa15") (eq_attr "tune" "cortexa53,cortexa15")
(const_string "no") (const_string "no")
(const_string "yes")))) (const_string "yes"))))
;; Scheduling ;; Scheduling
(include "large.md")
(include "small.md")
(include "../arm/cortex-a53.md") (include "../arm/cortex-a53.md")
(include "../arm/cortex-a15.md") (include "../arm/cortex-a15.md")
......
gcc/config/aarch64/large.md deleted 100644 → 0
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;;
;; Contributed by ARM Ltd.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; In the absence of any ARMv8-A implementations, two examples derived
;; from ARM's most recent ARMv7-A cores (Cortex-A7 and Cortex-A15) are
;; included by way of example. This is a temporary measure.
;; Example pipeline description for an example 'large' core
;; implementing AArch64
;;-------------------------------------------------------
;; General Description
;;-------------------------------------------------------
(define_automaton "large_cpu")
;; The core is modelled as a triple issue pipeline that has
;; the following dispatch units.
;; 1. Two pipelines for simple integer operations: int1, int2
;; 2. Two pipelines for SIMD and FP data-processing operations: fpsimd1, fpsimd2
;; 3. One pipeline for branch operations: br
;; 4. One pipeline for integer multiply and divide operations: multdiv
;; 5. Two pipelines for load and store operations: ls1, ls2
;;
;; We can issue into three pipelines per-cycle.
;;
;; We assume that where we have unit pairs xxx1 is always filled before xxx2.
;;-------------------------------------------------------
;; CPU Units and Reservations
;;-------------------------------------------------------
;; The three issue units
(define_cpu_unit "large_cpu_unit_i1, large_cpu_unit_i2, large_cpu_unit_i3" "large_cpu")
(define_reservation "large_cpu_resv_i1"
"(large_cpu_unit_i1 | large_cpu_unit_i2 | large_cpu_unit_i3)")
(define_reservation "large_cpu_resv_i2"
"((large_cpu_unit_i1 + large_cpu_unit_i2) | (large_cpu_unit_i2 + large_cpu_unit_i3))")
(define_reservation "large_cpu_resv_i3"
"(large_cpu_unit_i1 + large_cpu_unit_i2 + large_cpu_unit_i3)")
(final_presence_set "large_cpu_unit_i2" "large_cpu_unit_i1")
(final_presence_set "large_cpu_unit_i3" "large_cpu_unit_i2")
;; The main dispatch units
(define_cpu_unit "large_cpu_unit_int1, large_cpu_unit_int2" "large_cpu")
(define_cpu_unit "large_cpu_unit_fpsimd1, large_cpu_unit_fpsimd2" "large_cpu")
(define_cpu_unit "large_cpu_unit_ls1, large_cpu_unit_ls2" "large_cpu")
(define_cpu_unit "large_cpu_unit_br" "large_cpu")
(define_cpu_unit "large_cpu_unit_multdiv" "large_cpu")
(define_reservation "large_cpu_resv_ls" "(large_cpu_unit_ls1 | large_cpu_unit_ls2)")
;; The extended load-store pipeline
(define_cpu_unit "large_cpu_unit_load, large_cpu_unit_store" "large_cpu")
;; The extended ALU pipeline
(define_cpu_unit "large_cpu_unit_int1_alu, large_cpu_unit_int2_alu" "large_cpu")
(define_cpu_unit "large_cpu_unit_int1_shf, large_cpu_unit_int2_shf" "large_cpu")
(define_cpu_unit "large_cpu_unit_int1_sat, large_cpu_unit_int2_sat" "large_cpu")
;;-------------------------------------------------------
;; Simple ALU Instructions
;;-------------------------------------------------------
;; Simple ALU operations without shift
(define_insn_reservation "large_cpu_alu" 2
(and (eq_attr "tune" "large") (eq_attr "v8type" "adc,alu,alu_ext"))
"large_cpu_resv_i1, \
(large_cpu_unit_int1, large_cpu_unit_int1_alu) |\
(large_cpu_unit_int2, large_cpu_unit_int2_alu)")
(define_insn_reservation "large_cpu_logic" 2
(and (eq_attr "tune" "large") (eq_attr "v8type" "logic,logic_imm"))
"large_cpu_resv_i1, \
(large_cpu_unit_int1, large_cpu_unit_int1_alu) |\
(large_cpu_unit_int2, large_cpu_unit_int2_alu)")
(define_insn_reservation "large_cpu_shift" 2
(and (eq_attr "tune" "large") (eq_attr "v8type" "shift,shift_imm"))
"large_cpu_resv_i1, \
(large_cpu_unit_int1, large_cpu_unit_int1_shf) |\
(large_cpu_unit_int2, large_cpu_unit_int2_shf)")
;; Simple ALU operations with immediate shift
(define_insn_reservation "large_cpu_alu_shift" 3
(and (eq_attr "tune" "large") (eq_attr "v8type" "alu_shift"))
"large_cpu_resv_i1, \
(large_cpu_unit_int1,
large_cpu_unit_int1 + large_cpu_unit_int1_shf, large_cpu_unit_int1_alu) | \
(large_cpu_unit_int2,
large_cpu_unit_int2 + large_cpu_unit_int2_shf, large_cpu_unit_int2_alu)")
(define_insn_reservation "large_cpu_logic_shift" 3
(and (eq_attr "tune" "large") (eq_attr "v8type" "logic_shift"))
"large_cpu_resv_i1, \
(large_cpu_unit_int1, large_cpu_unit_int1_alu) |\
(large_cpu_unit_int2, large_cpu_unit_int2_alu)")
;;-------------------------------------------------------
;; Multiplication/Division
;;-------------------------------------------------------
;; Simple multiplication
(define_insn_reservation "large_cpu_mult_single" 3
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "SI")))
"large_cpu_resv_i1, large_cpu_unit_multdiv")
(define_insn_reservation "large_cpu_mult_double" 4
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "DI")))
"large_cpu_resv_i1, large_cpu_unit_multdiv")
;; 64-bit multiplication
(define_insn_reservation "large_cpu_mull" 4
(and (eq_attr "tune" "large") (eq_attr "v8type" "mull,mulh,maddl"))
"large_cpu_resv_i1, large_cpu_unit_multdiv * 2")
;; Division
(define_insn_reservation "large_cpu_udiv_single" 9
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "udiv") (eq_attr "mode" "SI")))
"large_cpu_resv_i1, large_cpu_unit_multdiv")
(define_insn_reservation "large_cpu_udiv_double" 18
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "udiv") (eq_attr "mode" "DI")))
"large_cpu_resv_i1, large_cpu_unit_multdiv")
(define_insn_reservation "large_cpu_sdiv_single" 10
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "sdiv") (eq_attr "mode" "SI")))
"large_cpu_resv_i1, large_cpu_unit_multdiv")
(define_insn_reservation "large_cpu_sdiv_double" 20
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "sdiv") (eq_attr "mode" "DI")))
"large_cpu_resv_i1, large_cpu_unit_multdiv")
;;-------------------------------------------------------
;; Branches
;;-------------------------------------------------------
;; Branches take one issue slot.
;; No latency as there is no result
(define_insn_reservation "large_cpu_branch" 0
(and (eq_attr "tune" "large") (eq_attr "v8type" "branch"))
"large_cpu_resv_i1, large_cpu_unit_br")
;; Calls take up all issue slots, and form a block in the
;; pipeline. The result however is available the next cycle.
;; Addition of new units requires this to be updated.
(define_insn_reservation "large_cpu_call" 1
(and (eq_attr "tune" "large") (eq_attr "v8type" "call"))
"large_cpu_resv_i3 | large_cpu_resv_i2, \
large_cpu_unit_int1 + large_cpu_unit_int2 + large_cpu_unit_br + \
large_cpu_unit_multdiv + large_cpu_unit_fpsimd1 + large_cpu_unit_fpsimd2 + \
large_cpu_unit_ls1 + large_cpu_unit_ls2,\
large_cpu_unit_int1_alu + large_cpu_unit_int1_shf + large_cpu_unit_int1_sat + \
large_cpu_unit_int2_alu + large_cpu_unit_int2_shf + \
large_cpu_unit_int2_sat + large_cpu_unit_load + large_cpu_unit_store")
;;-------------------------------------------------------
;; Load/Store Instructions
;;-------------------------------------------------------
;; Loads of up to two words.
(define_insn_reservation "large_cpu_load1" 4
(and (eq_attr "tune" "large") (eq_attr "v8type" "load_acq,load1,load2"))
"large_cpu_resv_i1, large_cpu_resv_ls, large_cpu_unit_load, nothing")
;; Stores of up to two words.
(define_insn_reservation "large_cpu_store1" 0
(and (eq_attr "tune" "large") (eq_attr "v8type" "store_rel,store1,store2"))
"large_cpu_resv_i1, large_cpu_resv_ls, large_cpu_unit_store")
;;-------------------------------------------------------
;; Floating-point arithmetic.
;;-------------------------------------------------------
(define_insn_reservation "large_cpu_fpalu" 4
(and (eq_attr "tune" "large")
(eq_attr "v8type" "ffarith,fadd,fccmp,fcvt,fcmp"))
"large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
(define_insn_reservation "large_cpu_fconst" 3
(and (eq_attr "tune" "large")
(eq_attr "v8type" "fconst"))
"large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
(define_insn_reservation "large_cpu_fpmuls" 4
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fmul,fmadd") (eq_attr "mode" "SF")))
"large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
(define_insn_reservation "large_cpu_fpmuld" 7
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fmul,fmadd") (eq_attr "mode" "DF")))
"large_cpu_resv_i1 + large_cpu_unit_fpsimd1, large_cpu_unit_fpsimd1 * 2,\
large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
;;-------------------------------------------------------
;; Floating-point Division
;;-------------------------------------------------------
;; Single-precision divide takes 14 cycles to complete, and this
;; includes the time taken for the special instruction used to collect the
;; result to travel down the multiply pipeline.
(define_insn_reservation "large_cpu_fdivs" 14
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF")))
"large_cpu_resv_i1, large_cpu_unit_fpsimd1 * 13")
(define_insn_reservation "large_cpu_fdivd" 29
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF")))
"large_cpu_resv_i1, large_cpu_unit_fpsimd1 * 28")
;;-------------------------------------------------------
;; Floating-point Transfers
;;-------------------------------------------------------
(define_insn_reservation "large_cpu_i2f" 4
(and (eq_attr "tune" "large")
(eq_attr "v8type" "fmovi2f"))
"large_cpu_resv_i1")
(define_insn_reservation "large_cpu_f2i" 2
(and (eq_attr "tune" "large")
(eq_attr "v8type" "fmovf2i"))
"large_cpu_resv_i1")
;;-------------------------------------------------------
;; Floating-point Load/Store
;;-------------------------------------------------------
(define_insn_reservation "large_cpu_floads" 4
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fpsimd_load,fpsimd_load2") (eq_attr "mode" "SF")))
"large_cpu_resv_i1")
(define_insn_reservation "large_cpu_floadd" 5
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fpsimd_load,fpsimd_load2") (eq_attr "mode" "DF")))
"large_cpu_resv_i1 + large_cpu_unit_br, large_cpu_resv_i1")
(define_insn_reservation "large_cpu_fstores" 0
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fpsimd_store,fpsimd_store2") (eq_attr "mode" "SF")))
"large_cpu_resv_i1")
(define_insn_reservation "large_cpu_fstored" 0
(and (eq_attr "tune" "large")
(and (eq_attr "v8type" "fpsimd_store,fpsimd_store2") (eq_attr "mode" "DF")))
"large_cpu_resv_i1 + large_cpu_unit_br, large_cpu_resv_i1")
;;-------------------------------------------------------
;; Bypasses
;;-------------------------------------------------------
(define_bypass 1 "large_cpu_alu, large_cpu_logic, large_cpu_shift"
"large_cpu_alu, large_cpu_alu_shift, large_cpu_logic, large_cpu_logic_shift, large_cpu_shift")
(define_bypass 2 "large_cpu_alu_shift, large_cpu_logic_shift"
"large_cpu_alu, large_cpu_alu_shift, large_cpu_logic, large_cpu_logic_shift, large_cpu_shift")
(define_bypass 1 "large_cpu_alu, large_cpu_logic, large_cpu_shift" "large_cpu_load1")
(define_bypass 2 "large_cpu_alu_shift, large_cpu_logic_shift" "large_cpu_load1")
(define_bypass 2 "large_cpu_floads"
"large_cpu_fpalu, large_cpu_fpmuld,\
large_cpu_fdivs, large_cpu_fdivd,\
large_cpu_f2i")
(define_bypass 3 "large_cpu_floadd"
"large_cpu_fpalu, large_cpu_fpmuld,\
large_cpu_fdivs, large_cpu_fdivd,\
large_cpu_f2i")
gcc/config/aarch64/small.md deleted 100644 → 0
;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
;;
;; Contributed by ARM Ltd.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; In the absence of any ARMv8-A implementations, two examples derived
;; from ARM's most recent ARMv7-A cores (Cortex-A7 and Cortex-A15) are
;; included by way of example. This is a temporary measure.
;; Example pipeline description for an example 'small' core
;; implementing AArch64
;;-------------------------------------------------------
;; General Description
;;-------------------------------------------------------
(define_automaton "small_cpu")
;; The core is modelled as a single issue pipeline with the following
;; dispatch units.
;; 1. One pipeline for simple intructions.
;; 2. One pipeline for branch intructions.
;;
;; There are five pipeline stages.
;; The decode/issue stages operate the same for all instructions.
;; Instructions always advance one stage per cycle in order.
;; Only branch instructions may dual-issue with other instructions, except
;; when those instructions take multiple cycles to issue.
;;-------------------------------------------------------
;; CPU Units and Reservations
;;-------------------------------------------------------
(define_cpu_unit "small_cpu_unit_i" "small_cpu")
(define_cpu_unit "small_cpu_unit_br" "small_cpu")
;; Pseudo-unit for blocking the multiply pipeline when a double-precision
;; multiply is in progress.
(define_cpu_unit "small_cpu_unit_fpmul_pipe" "small_cpu")
;; The floating-point add pipeline, used to model the usage
;; of the add pipeline by fp alu instructions.
(define_cpu_unit "small_cpu_unit_fpadd_pipe" "small_cpu")
;; Floating-point division pipeline (long latency, out-of-order completion).
(define_cpu_unit "small_cpu_unit_fpdiv" "small_cpu")
;;-------------------------------------------------------
;; Simple ALU Instructions
;;-------------------------------------------------------
;; Simple ALU operations without shift
(define_insn_reservation "small_cpu_alu" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "adc,alu,alu_ext"))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_logic" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "logic,logic_imm"))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_shift" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "shift,shift_imm"))
"small_cpu_unit_i")
;; Simple ALU operations with immediate shift
(define_insn_reservation "small_cpu_alu_shift" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "alu_shift"))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_logic_shift" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "logic_shift"))
"small_cpu_unit_i")
;;-------------------------------------------------------
;; Multiplication/Division
;;-------------------------------------------------------
;; Simple multiplication
(define_insn_reservation "small_cpu_mult_single" 2
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "SI")))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_mult_double" 3
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "DI")))
"small_cpu_unit_i")
;; 64-bit multiplication
(define_insn_reservation "small_cpu_mull" 3
(and (eq_attr "tune" "small") (eq_attr "v8type" "mull,mulh,maddl"))
"small_cpu_unit_i * 2")
;; Division
(define_insn_reservation "small_cpu_udiv_single" 5
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "udiv") (eq_attr "mode" "SI")))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_udiv_double" 10
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "udiv") (eq_attr "mode" "DI")))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_sdiv_single" 6
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "sdiv") (eq_attr "mode" "SI")))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_sdiv_double" 12
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "sdiv") (eq_attr "mode" "DI")))
"small_cpu_unit_i")
;;-------------------------------------------------------
;; Load/Store Instructions
;;-------------------------------------------------------
(define_insn_reservation "small_cpu_load1" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "load_acq,load1"))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_store1" 0
(and (eq_attr "tune" "small")
(eq_attr "v8type" "store_rel,store1"))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_load2" 3
(and (eq_attr "tune" "small")
(eq_attr "v8type" "load2"))
"small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i")
(define_insn_reservation "small_cpu_store2" 0
(and (eq_attr "tune" "small")
(eq_attr "v8type" "store2"))
"small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i")
;;-------------------------------------------------------
;; Branches
;;-------------------------------------------------------
;; Direct branches are the only instructions that can dual-issue.
;; The latency here represents when the branch actually takes place.
(define_insn_reservation "small_cpu_unit_br" 3
(and (eq_attr "tune" "small")
(eq_attr "v8type" "branch,call"))
"small_cpu_unit_br")
;;-------------------------------------------------------
;; Floating-point arithmetic.
;;-------------------------------------------------------
(define_insn_reservation "small_cpu_fpalu" 4
(and (eq_attr "tune" "small")
(eq_attr "v8type" "ffarith,fadd,fccmp,fcvt,fcmp"))
"small_cpu_unit_i + small_cpu_unit_fpadd_pipe")
(define_insn_reservation "small_cpu_fconst" 3
(and (eq_attr "tune" "small")
(eq_attr "v8type" "fconst"))
"small_cpu_unit_i + small_cpu_unit_fpadd_pipe")
(define_insn_reservation "small_cpu_fpmuls" 4
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fmul") (eq_attr "mode" "SF")))
"small_cpu_unit_i + small_cpu_unit_fpmul_pipe")
(define_insn_reservation "small_cpu_fpmuld" 7
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fmul") (eq_attr "mode" "DF")))
"small_cpu_unit_i + small_cpu_unit_fpmul_pipe, small_cpu_unit_fpmul_pipe * 2,\
small_cpu_unit_i + small_cpu_unit_fpmul_pipe")
;;-------------------------------------------------------
;; Floating-point Division
;;-------------------------------------------------------
;; Single-precision divide takes 14 cycles to complete, and this
;; includes the time taken for the special instruction used to collect the
;; result to travel down the multiply pipeline.
(define_insn_reservation "small_cpu_fdivs" 14
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF")))
"small_cpu_unit_i, small_cpu_unit_fpdiv * 13")
(define_insn_reservation "small_cpu_fdivd" 29
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF")))
"small_cpu_unit_i, small_cpu_unit_fpdiv * 28")
;;-------------------------------------------------------
;; Floating-point Transfers
;;-------------------------------------------------------
(define_insn_reservation "small_cpu_i2f" 4
(and (eq_attr "tune" "small")
(eq_attr "v8type" "fmovi2f"))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_f2i" 2
(and (eq_attr "tune" "small")
(eq_attr "v8type" "fmovf2i"))
"small_cpu_unit_i")
;;-------------------------------------------------------
;; Floating-point Load/Store
;;-------------------------------------------------------
(define_insn_reservation "small_cpu_floads" 4
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "SF")))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_floadd" 5
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fpsimd_load") (eq_attr "mode" "DF")))
"small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i")
(define_insn_reservation "small_cpu_fstores" 0
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "SF")))
"small_cpu_unit_i")
(define_insn_reservation "small_cpu_fstored" 0
(and (eq_attr "tune" "small")
(and (eq_attr "v8type" "fpsimd_store") (eq_attr "mode" "DF")))
"small_cpu_unit_i + small_cpu_unit_br, small_cpu_unit_i")
;;-------------------------------------------------------
;; Bypasses
;;-------------------------------------------------------
;; Forwarding path for unshifted operands.
(define_bypass 1 "small_cpu_alu, small_cpu_alu_shift"
"small_cpu_alu, small_cpu_alu_shift, small_cpu_logic, small_cpu_logic_shift, small_cpu_shift")
(define_bypass 1 "small_cpu_logic, small_cpu_logic_shift"
"small_cpu_alu, small_cpu_alu_shift, small_cpu_logic, small_cpu_logic_shift, small_cpu_shift")
(define_bypass 1 "small_cpu_shift"
"small_cpu_alu, small_cpu_alu_shift, small_cpu_logic, small_cpu_logic_shift, small_cpu_shift")
;; Load-to-use for floating-point values has a penalty of one cycle.
(define_bypass 2 "small_cpu_floads"
"small_cpu_fpalu, small_cpu_fpmuld,\
small_cpu_fdivs, small_cpu_fdivd,\
small_cpu_f2i")
(define_bypass 3 "small_cpu_floadd"
"small_cpu_fpalu, small_cpu_fpmuld,\
small_cpu_fdivs, small_cpu_fdivd,\
small_cpu_f2i")
gcc/testsuite/ChangeLog
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.target/aarch64/cpu-diagnostics-2.c: Change "-mcpu="
to "cortex-a53".
* gcc.target/aarch64/cpu-diagnostics-3.c: Change "-mcpu="
to "cortex-a53".
2013-11-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 2013-11-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* gcc.dg/atomic/c11-atomic-exec-4.c: Define _XOPEN_SOURCE=600 on * gcc.dg/atomic/c11-atomic-exec-4.c: Define _XOPEN_SOURCE=600 on
......
gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
/* { dg-error "missing" "" {target "aarch64*-*-*" } } */ /* { dg-error "missing" "" {target "aarch64*-*-*" } } */
/* { dg-options "-O2 -mcpu=example-1+no" } */ /* { dg-options "-O2 -mcpu=cortex-a53+no" } */
void f () void f ()
{ {
......
gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */ /* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
/* { dg-options "-O2 -mcpu=example-1+dummy" } */ /* { dg-options "-O2 -mcpu=cortex-a53+dummy" } */
void f () void f ()
{ {
......
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