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riscv-gcc-1
Commit 98b2d887 by Jeff Law
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pa.md (dbra pattern): Use output_dbra. 

        * pa.md (dbra pattern): Use output_dbra.
        (dbra pattern #2): New pattern.  Also use output_dbra.
        (movb, inverted movb): New patterns.

From-SVN: r4887
parent 6bd5174e
Showing with 147 additions and 66 deletions
gcc/config/pa/pa.md
...@@ -2898,7 +2898,6 @@ ...@@ -2898,7 +2898,6 @@
return \"depi %3,%2+%1-1,%1,%0\"; return \"depi %3,%2+%1-1,%1,%0\";
}") }")
;; The dbra pattern from hell.
;; This insn is used for some loop tests, typically loops reversed when ;; This insn is used for some loop tests, typically loops reversed when
;; strength reduction is used. It is actually created when the instruction ;; strength reduction is used. It is actually created when the instruction
;; combination phase combines the special loop test. Since this insn ;; combination phase combines the special loop test. Since this insn
...@@ -2918,72 +2917,63 @@ ...@@ -2918,72 +2917,63 @@
(plus:SI (match_dup 0) (match_dup 1))) (plus:SI (match_dup 0) (match_dup 1)))
(clobber (match_scratch:SI 4 "=X,r,r"))] (clobber (match_scratch:SI 4 "=X,r,r"))]
"" ""
"* "* output_dbra (operands, insn, which_alternative); "
{ ;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi")
(set (attr "length")
(if_then_else (eq_attr "alternative" "0")
;; Loop counter in register case
;; Short branch has length of 1
;; Long branch has length of 2
(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 1)
(const_int 2))
if (which_alternative == 0) ;; Loop counter in FP reg case.
{ ;; Extra goo to deal with additional reload insns.
int nullify = INSN_ANNULLED_BRANCH_P (insn); (if_then_else (eq_attr "alternative" "1")
int length = get_attr_length (insn); (if_then_else (lt (match_dup 3) (pc))
(if_then_else
/* If this is a long branch with its delay slot unfilled, set `nullify' (lt (abs (minus (match_dup 3) (plus (pc) (const_int 6))))
as it can nullify the delay slot and save a nop. */ (const_int 2047))
if (length == 2 && dbr_sequence_length () == 0) (const_int 6)
nullify = 1; (const_int 7))
(if_then_else
/* If this is a short forward conditional branch which did not get (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
its delay slot filled, the delay slot can still be nullified. */ (const_int 2047))
if (! nullify && length == 1 && dbr_sequence_length () == 0) (const_int 6)
nullify = forward_branch_p (insn); (const_int 7)))
;; Loop counter in memory case.
/* Handle short versions first. */ ;; Extra goo to deal with additional reload insns.
if (length == 1 && nullify) (if_then_else (lt (match_dup 3) (pc))
return \"addib,%C2,n %1,%0,%3\"; (if_then_else
else if (length == 1 && ! nullify) (lt (abs (minus (match_dup 3) (plus (pc) (const_int 3))))
return \"addib,%C2 %1,%0,%3\"; (const_int 2047))
else if (length == 2) (const_int 3)
{ (const_int 4))
/* Handle weird backwards branch with a fulled delay slot (if_then_else
which is nullified. */ (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
if (dbr_sequence_length () != 0 (const_int 2047))
&& ! forward_branch_p (insn) (const_int 3)
&& nullify) (const_int 4))))))])
return \"addib,%N2,n %1,%0,.+12\;bl %3,0\";
;; Simply another variant of the dbra pattern. More restrictive
/* Handle normal cases. */ ;; in testing the comparison operator as it must worry about overflow
if (nullify) ;; problems.
return \"addi,%N2 %1,%0,%0\;bl,n %3,0\"; (define_insn ""
else [(set (pc)
return \"addi,%N2 %1,%0,%0\;bl %3,0\"; (if_then_else
} (match_operator 2 "eq_neq_comparison_operator"
else [(match_operand:SI 0 "register_operand" "+!r,!*fx,!*m")
abort(); (match_operand:SI 5 "const_int_operand" "")])
} (label_ref (match_operand 3 "" ""))
/* Deal with gross reload from FP register case. */ (pc)))
else if (which_alternative == 1) (set (match_dup 0)
{ (plus:SI (match_dup 0) (match_operand:SI 1 "int5_operand" "L,L,L")))
/* Move loop counter from FP register to MEM then into a GR, (clobber (match_scratch:SI 4 "=X,r,r"))]
increment the GR, store the GR into MEM, and finally reload "INTVAL (operands[5]) == - INTVAL (operands[1])"
the FP register from MEM from within the branch's delay slot. */ "* return output_dbra (operands, insn, which_alternative);"
output_asm_insn (\"fstws %0,-16(0,%%r30)\;ldw -16(0,%%r30),%4\",operands);
output_asm_insn (\"ldo %1(%4),%4\;stw %4,-16(0,%%r30)\", operands);
if (get_attr_length (insn) == 6)
return \"comb,%S2 0,%4,%3\;fldws -16(0,%%r30),%0\";
else
return \"comclr,%B2 0,%4,0\;bl %3,0\;fldws -16(0,%%r30),%0\";
}
/* Deal with gross reload from memory case. */
else
{
/* Reload loop counter from memory, the store back to memory
happens in the branch's delay slot. */
output_asm_insn (\"ldw %0,%4\", operands);
if (get_attr_length (insn) == 3)
return \"addib,%C2 %1,%4,%3;stw %4,%0\";
else
return \"addi,%N2 %1,%4,%0\;bl %3,0\;stw %4,%0\";
}
}"
;; Do not expect to understand this the first time through. ;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi") [(set_attr "type" "cbranch,multi,multi")
(set (attr "length") (set (attr "length")
...@@ -3024,6 +3014,97 @@ ...@@ -3024,6 +3014,97 @@
(const_int 3) (const_int 3)
(const_int 4))))))]) (const_int 4))))))])
(define_insn ""
[(set (pc)
(if_then_else
(match_operator 2 "movb_comparison_operator"
[(match_operand:SI 1 "register_operand" "r,r,r") (const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))
(set (match_operand:SI 0 "register_operand" "=!r,!*fx,!*m")
(match_dup 1))]
""
"* return output_movb (operands, insn, which_alternative, 0); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi")
(set (attr "length")
(if_then_else (eq_attr "alternative" "0")
;; Loop counter in register case
;; Short branch has length of 1
;; Long branch has length of 2
(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 1)
(const_int 2))
;; Loop counter in FP reg case.
;; Extra goo to deal with additional reload insns.
(if_then_else (eq_attr "alternative" "1")
(if_then_else (lt (match_dup 3) (pc))
(if_then_else
(lt (abs (minus (match_dup 3) (plus (pc) (const_int 3))))
(const_int 2047))
(const_int 3)
(const_int 4))
(if_then_else
(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 3)
(const_int 4)))
;; Loop counter in memory case.
;; Extra goo to deal with additional reload insns.
(if_then_else
(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 2)
(const_int 3)))))])
;; Handle negated branch.
(define_insn ""
[(set (pc)
(if_then_else
(match_operator 2 "movb_comparison_operator"
[(match_operand:SI 1 "register_operand" "r,r,r") (const_int 0)])
(pc)
(label_ref (match_operand 3 "" ""))))
(set (match_operand:SI 0 "register_operand" "=!r,!*fx,!*m")
(match_dup 1))]
""
"* return output_movb (operands, insn, which_alternative, 1); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi")
(set (attr "length")
(if_then_else (eq_attr "alternative" "0")
;; Loop counter in register case
;; Short branch has length of 1
;; Long branch has length of 2
(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 1)
(const_int 2))
;; Loop counter in FP reg case.
;; Extra goo to deal with additional reload insns.
(if_then_else (eq_attr "alternative" "1")
(if_then_else (lt (match_dup 3) (pc))
(if_then_else
(lt (abs (minus (match_dup 3) (plus (pc) (const_int 3))))
(const_int 2047))
(const_int 3)
(const_int 4))
(if_then_else
(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 3)
(const_int 4)))
;; Loop counter in memory case.
;; Extra goo to deal with additional reload insns.
(if_then_else
(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
(const_int 2047))
(const_int 2)
(const_int 3)))))])
;; The next four peepholes take advantage of the new 5 operand ;; The next four peepholes take advantage of the new 5 operand
;; fmpy{add,sub} instructions available on 1.1 CPUS. Basically ;; fmpy{add,sub} instructions available on 1.1 CPUS. Basically
;; fmpyadd performs a multiply and add/sub of independent operands ;; fmpyadd performs a multiply and add/sub of independent operands
......
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