Skip to content

R
riscv-gcc-1
Commit 9602b6a1 by Andreas Krebbel Committed by Andreas Krebbel
Options

s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 

2010-04-13  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
            Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
	
	* gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH.
	* gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with
	UNITS_PER_LONG where it is ABI relevant.	
	(s390_return_addr_rtx): Likewise.
	(s390_back_chain_rtx): Likewise.
	(s390_frame_area): Likewise.
	(s390_frame_info): Likewise.
	(s390_initial_elimination_offset): Likewise.
	(save_gprs): Likewise.
	(s390_emit_prologue): Likewise.
	(s390_emit_epilogue): Likewise.
	(s390_function_arg_advance): Likewise.
	(s390_function_arg): Likewise.
	(s390_va_start): Likewise.
	(s390_gimplify_va_arg): Likewise.
	(s390_function_profiler): Likewise.
	(s390_optimize_prologue): Likewise.
	(s390_rtx_costs): Likewise.
	(s390_secondary_reload): Likewise.
	(s390_promote_function_mode): Likewise.
	(s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH.
	(s390_scalar_mode_supported_p): Disallow TImode if no 64 bit
	registers available.
	(s390_unwind_word_mode): New function.
	(s390_function_value): Split 64 bit values into register pair if
	used as return value.
	(s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for
	function call parameters.  Handle parallels.
	(TARGET_SCALAR_MODE_SUPPORTED_P): New macro.
	(HARD_REGNO_CALL_PART_CLOBBERED): New macro.
	(DWARF_CIE_DATA_ALIGNMENT): New macro.
	(s390_expand_setmem): Remove unused variable src_addr.
	* gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to
	deal with 64 bit registers.	
	* gcc/config/s390/s390.h: Define __zarch__ predefined macro.
	Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant.
	(UNITS_PER_LONG): New macro.
	* libjava/include/s390-signal.h: Define extended ucontext
	structure containing the upper halfs of the 64 bit registers.


Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com>

From-SVN: r158257
parent 3b123595
Showing with 531 additions and 242 deletions
gcc/ChangeLog
2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH.
* gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with
UNITS_PER_LONG where it is ABI relevant.
(s390_return_addr_rtx): Likewise.
(s390_back_chain_rtx): Likewise.
(s390_frame_area): Likewise.
(s390_frame_info): Likewise.
(s390_initial_elimination_offset): Likewise.
(save_gprs): Likewise.
(s390_emit_prologue): Likewise.
(s390_emit_epilogue): Likewise.
(s390_function_arg_advance): Likewise.
(s390_function_arg): Likewise.
(s390_va_start): Likewise.
(s390_gimplify_va_arg): Likewise.
(s390_function_profiler): Likewise.
(s390_optimize_prologue): Likewise.
(s390_rtx_costs): Likewise.
(s390_secondary_reload): Likewise.
(s390_promote_function_mode): Likewise.
(s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH.
(s390_scalar_mode_supported_p): Disallow TImode if no 64 bit
registers available.
(s390_unwind_word_mode): New function.
(s390_function_value): Split 64 bit values into register pair if
used as return value.
(s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for
function call parameters. Handle parallels.
(TARGET_SCALAR_MODE_SUPPORTED_P): New macro.
(HARD_REGNO_CALL_PART_CLOBBERED): New macro.
(DWARF_CIE_DATA_ALIGNMENT): New macro.
(s390_expand_setmem): Remove unused variable src_addr.
* gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to
deal with 64 bit registers.
* gcc/config/s390/s390.h: Define __zarch__ predefined macro.
Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant.
(UNITS_PER_LONG): New macro.
* libjava/include/s390-signal.h: Define extended ucontext
structure containing the upper halfs of the 64 bit registers.
2010-04-13 Simon Baldwin <simonb@google.com> 2010-04-13 Simon Baldwin <simonb@google.com>
* cfgexpand.c (gimple_expand_cfg): Clarify warning message text. * cfgexpand.c (gimple_expand_cfg): Clarify warning message text.
......
gcc/config/s390/s390.c
...@@ -324,7 +324,7 @@ struct GTY(()) machine_function ...@@ -324,7 +324,7 @@ struct GTY(()) machine_function
#define cfun_frame_layout (cfun->machine->frame_layout) #define cfun_frame_layout (cfun->machine->frame_layout)
#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs) #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \ #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD) cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \ #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
(1 << (BITNUM))) (1 << (BITNUM)))
#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \ #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
...@@ -365,14 +365,25 @@ s390_libgcc_shift_count_mode (void) ...@@ -365,14 +365,25 @@ s390_libgcc_shift_count_mode (void)
return TARGET_64BIT ? DImode : SImode; return TARGET_64BIT ? DImode : SImode;
} }
static enum machine_mode
s390_unwind_word_mode (void)
{
return TARGET_64BIT ? DImode : SImode;
}
/* Return true if the back end supports mode MODE. */ /* Return true if the back end supports mode MODE. */
static bool static bool
s390_scalar_mode_supported_p (enum machine_mode mode) s390_scalar_mode_supported_p (enum machine_mode mode)
{ {
/* In contrast to the default implementation reject TImode constants on 31bit
TARGET_ZARCH for ABI compliance. */
if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
return false;
if (DECIMAL_FLOAT_MODE_P (mode)) if (DECIMAL_FLOAT_MODE_P (mode))
return default_decimal_float_supported_p (); return default_decimal_float_supported_p ();
else
return default_scalar_mode_supported_p (mode); return default_scalar_mode_supported_p (mode);
} }
/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */ /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
...@@ -2407,7 +2418,7 @@ s390_rtx_costs (rtx x, int code, int outer_code, int *total, ...@@ -2407,7 +2418,7 @@ s390_rtx_costs (rtx x, int code, int outer_code, int *total,
{ {
rtx left = XEXP (x, 0); rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1); rtx right = XEXP (x, 1);
if (TARGET_64BIT) if (TARGET_ZARCH)
{ {
if (GET_CODE (right) == CONST_INT if (GET_CODE (right) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (right))) && CONST_OK_FOR_K (INTVAL (right)))
...@@ -2468,7 +2479,7 @@ s390_rtx_costs (rtx x, int code, int outer_code, int *total, ...@@ -2468,7 +2479,7 @@ s390_rtx_costs (rtx x, int code, int outer_code, int *total,
{ {
rtx right = XEXP (x, 1); rtx right = XEXP (x, 1);
if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
if (TARGET_64BIT) if (TARGET_ZARCH)
*total = s390_cost->dsgfr; *total = s390_cost->dsgfr;
else else
*total = s390_cost->dr; *total = s390_cost->dr;
...@@ -2960,7 +2971,7 @@ s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass, ...@@ -2960,7 +2971,7 @@ s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
if (MEM_P (x) if (MEM_P (x)
&& s390_symref_operand_p (XEXP (x, 0), NULL, NULL) && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
&& (mode == QImode || mode == TImode || FLOAT_MODE_P (mode) && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
|| (!TARGET_64BIT && mode == DImode) || (!TARGET_ZARCH && mode == DImode)
|| ((mode == HImode || mode == SImode || mode == DImode) || ((mode == HImode || mode == SImode || mode == DImode)
&& (!s390_check_symref_alignment (XEXP (x, 0), && (!s390_check_symref_alignment (XEXP (x, 0),
GET_MODE_SIZE (mode)))))) GET_MODE_SIZE (mode))))))
...@@ -4033,7 +4044,7 @@ s390_expand_setmem (rtx dst, rtx len, rtx val) ...@@ -4033,7 +4044,7 @@ s390_expand_setmem (rtx dst, rtx len, rtx val)
else else
{ {
rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX; rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
rtx loop_start_label = gen_label_rtx (); rtx loop_start_label = gen_label_rtx ();
rtx loop_end_label = gen_label_rtx (); rtx loop_end_label = gen_label_rtx ();
rtx end_label = gen_label_rtx (); rtx end_label = gen_label_rtx ();
...@@ -4044,7 +4055,6 @@ s390_expand_setmem (rtx dst, rtx len, rtx val) ...@@ -4044,7 +4055,6 @@ s390_expand_setmem (rtx dst, rtx len, rtx val)
mode = Pmode; mode = Pmode;
dst_addr = gen_reg_rtx (Pmode); dst_addr = gen_reg_rtx (Pmode);
src_addr = gen_reg_rtx (Pmode);
count = gen_reg_rtx (mode); count = gen_reg_rtx (mode);
blocks = gen_reg_rtx (mode); blocks = gen_reg_rtx (mode);
...@@ -5412,7 +5422,6 @@ s390_first_cycle_multipass_dfa_lookahead (void) ...@@ -5412,7 +5422,6 @@ s390_first_cycle_multipass_dfa_lookahead (void)
return 4; return 4;
} }
/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression. /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
Fix up MEMs as required. */ Fix up MEMs as required. */
...@@ -6810,9 +6819,9 @@ s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) ...@@ -6810,9 +6819,9 @@ s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
} }
if (TARGET_PACKED_STACK) if (TARGET_PACKED_STACK)
offset = -2 * UNITS_PER_WORD; offset = -2 * UNITS_PER_LONG;
else else
offset = RETURN_REGNUM * UNITS_PER_WORD; offset = RETURN_REGNUM * UNITS_PER_LONG;
addr = plus_constant (frame, offset); addr = plus_constant (frame, offset);
addr = memory_address (Pmode, addr); addr = memory_address (Pmode, addr);
...@@ -6831,7 +6840,7 @@ s390_back_chain_rtx (void) ...@@ -6831,7 +6840,7 @@ s390_back_chain_rtx (void)
if (TARGET_PACKED_STACK) if (TARGET_PACKED_STACK)
chain = plus_constant (stack_pointer_rtx, chain = plus_constant (stack_pointer_rtx,
STACK_POINTER_OFFSET - UNITS_PER_WORD); STACK_POINTER_OFFSET - UNITS_PER_LONG);
else else
chain = stack_pointer_rtx; chain = stack_pointer_rtx;
...@@ -6956,9 +6965,9 @@ s390_frame_area (int *area_bottom, int *area_top) ...@@ -6956,9 +6965,9 @@ s390_frame_area (int *area_bottom, int *area_top)
if (cfun_frame_layout.first_restore_gpr != -1) if (cfun_frame_layout.first_restore_gpr != -1)
{ {
b = (cfun_frame_layout.gprs_offset b = (cfun_frame_layout.gprs_offset
+ cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD); + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
t = b + (cfun_frame_layout.last_restore_gpr t = b + (cfun_frame_layout.last_restore_gpr
- cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD; - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
} }
if (TARGET_64BIT && cfun_save_high_fprs_p) if (TARGET_64BIT && cfun_save_high_fprs_p)
...@@ -7153,20 +7162,20 @@ s390_frame_info (void) ...@@ -7153,20 +7162,20 @@ s390_frame_info (void)
if (!TARGET_PACKED_STACK) if (!TARGET_PACKED_STACK)
{ {
cfun_frame_layout.backchain_offset = 0; cfun_frame_layout.backchain_offset = 0;
cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD; cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8; cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8; cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
* UNITS_PER_WORD); * UNITS_PER_LONG);
} }
else if (TARGET_BACKCHAIN) /* kernel stack layout */ else if (TARGET_BACKCHAIN) /* kernel stack layout */
{ {
cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
- UNITS_PER_WORD); - UNITS_PER_LONG);
cfun_frame_layout.gprs_offset cfun_frame_layout.gprs_offset
= (cfun_frame_layout.backchain_offset = (cfun_frame_layout.backchain_offset
- (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1) - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
* UNITS_PER_WORD); * UNITS_PER_LONG);
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
...@@ -7221,7 +7230,7 @@ s390_frame_info (void) ...@@ -7221,7 +7230,7 @@ s390_frame_info (void)
else else
{ {
if (TARGET_BACKCHAIN) if (TARGET_BACKCHAIN)
cfun_frame_layout.frame_size += UNITS_PER_WORD; cfun_frame_layout.frame_size += UNITS_PER_LONG;
/* No alignment trouble here because f8-f15 are only saved under /* No alignment trouble here because f8-f15 are only saved under
64 bit. */ 64 bit. */
...@@ -7340,7 +7349,7 @@ s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) ...@@ -7340,7 +7349,7 @@ s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
case GENERAL_REGS: case GENERAL_REGS:
if (REGNO_PAIR_OK (regno, mode)) if (REGNO_PAIR_OK (regno, mode))
{ {
if (TARGET_64BIT if (TARGET_ZARCH
|| (mode != TFmode && mode != TCmode && mode != TDmode)) || (mode != TFmode && mode != TCmode && mode != TDmode))
return true; return true;
} }
...@@ -7471,7 +7480,7 @@ s390_initial_elimination_offset (int from, int to) ...@@ -7471,7 +7480,7 @@ s390_initial_elimination_offset (int from, int to)
index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot; index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
gcc_assert (index >= 0); gcc_assert (index >= 0);
offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset; offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
offset += index * UNITS_PER_WORD; offset += index * UNITS_PER_LONG;
break; break;
case BASE_REGNUM: case BASE_REGNUM:
...@@ -7607,7 +7616,7 @@ save_gprs (rtx base, int offset, int first, int last) ...@@ -7607,7 +7616,7 @@ save_gprs (rtx base, int offset, int first, int last)
if (start > last) if (start > last)
return insn; return insn;
addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD); addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
gen_rtx_REG (Pmode, start), gen_rtx_REG (Pmode, start),
GEN_INT (last - start + 1)); GEN_INT (last - start + 1));
...@@ -7756,7 +7765,7 @@ s390_emit_prologue (void) ...@@ -7756,7 +7765,7 @@ s390_emit_prologue (void)
{ {
insn = save_gprs (stack_pointer_rtx, insn = save_gprs (stack_pointer_rtx,
cfun_frame_layout.gprs_offset + cfun_frame_layout.gprs_offset +
UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
- cfun_frame_layout.first_save_gpr_slot), - cfun_frame_layout.first_save_gpr_slot),
cfun_frame_layout.first_save_gpr, cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr); cfun_frame_layout.last_save_gpr);
...@@ -8153,7 +8162,7 @@ s390_emit_epilogue (bool sibcall) ...@@ -8153,7 +8162,7 @@ s390_emit_epilogue (bool sibcall)
addr = plus_constant (frame_pointer, addr = plus_constant (frame_pointer,
offset + cfun_frame_layout.gprs_offset offset + cfun_frame_layout.gprs_offset
+ (i - cfun_frame_layout.first_save_gpr_slot) + (i - cfun_frame_layout.first_save_gpr_slot)
* UNITS_PER_WORD); * UNITS_PER_LONG);
addr = gen_rtx_MEM (Pmode, addr); addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ()); set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (addr, gen_rtx_REG (Pmode, i)); emit_move_insn (addr, gen_rtx_REG (Pmode, i));
...@@ -8182,7 +8191,7 @@ s390_emit_epilogue (bool sibcall) ...@@ -8182,7 +8191,7 @@ s390_emit_epilogue (bool sibcall)
offset + cfun_frame_layout.gprs_offset offset + cfun_frame_layout.gprs_offset
+ (RETURN_REGNUM + (RETURN_REGNUM
- cfun_frame_layout.first_save_gpr_slot) - cfun_frame_layout.first_save_gpr_slot)
* UNITS_PER_WORD); * UNITS_PER_LONG);
addr = gen_rtx_MEM (Pmode, addr); addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ()); set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (return_reg, addr); emit_move_insn (return_reg, addr);
...@@ -8193,7 +8202,7 @@ s390_emit_epilogue (bool sibcall) ...@@ -8193,7 +8202,7 @@ s390_emit_epilogue (bool sibcall)
offset + cfun_frame_layout.gprs_offset offset + cfun_frame_layout.gprs_offset
+ (cfun_frame_layout.first_restore_gpr + (cfun_frame_layout.first_restore_gpr
- cfun_frame_layout.first_save_gpr_slot) - cfun_frame_layout.first_save_gpr_slot)
* UNITS_PER_WORD, * UNITS_PER_LONG,
cfun_frame_layout.first_restore_gpr, cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr); cfun_frame_layout.last_restore_gpr);
insn = emit_insn (insn); insn = emit_insn (insn);
...@@ -8357,7 +8366,7 @@ s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, ...@@ -8357,7 +8366,7 @@ s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
else if (s390_function_arg_integer (mode, type)) else if (s390_function_arg_integer (mode, type))
{ {
int size = s390_function_arg_size (mode, type); int size = s390_function_arg_size (mode, type);
cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD); cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
} }
else else
gcc_unreachable (); gcc_unreachable ();
...@@ -8396,12 +8405,25 @@ s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, ...@@ -8396,12 +8405,25 @@ s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
else if (s390_function_arg_integer (mode, type)) else if (s390_function_arg_integer (mode, type))
{ {
int size = s390_function_arg_size (mode, type); int size = s390_function_arg_size (mode, type);
int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD; int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
if (cum->gprs + n_gprs > GP_ARG_NUM_REG) if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
return 0; return 0;
else else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
return gen_rtx_REG (mode, cum->gprs + 2); return gen_rtx_REG (mode, cum->gprs + 2);
else if (n_gprs == 2)
{
rtvec p = rtvec_alloc (2);
RTVEC_ELT (p, 0)
= gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
const0_rtx);
RTVEC_ELT (p, 1)
= gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
GEN_INT (4));
return gen_rtx_PARALLEL (mode, p);
}
} }
/* After the real arguments, expand_call calls us once again /* After the real arguments, expand_call calls us once again
...@@ -8451,7 +8473,7 @@ s390_promote_function_mode (const_tree type, enum machine_mode mode, ...@@ -8451,7 +8473,7 @@ s390_promote_function_mode (const_tree type, enum machine_mode mode,
int for_return ATTRIBUTE_UNUSED) int for_return ATTRIBUTE_UNUSED)
{ {
if (INTEGRAL_MODE_P (mode) if (INTEGRAL_MODE_P (mode)
&& GET_MODE_SIZE (mode) < UNITS_PER_WORD) && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
{ {
if (POINTER_TYPE_P (type)) if (POINTER_TYPE_P (type))
*punsignedp = POINTERS_EXTEND_UNSIGNED; *punsignedp = POINTERS_EXTEND_UNSIGNED;
...@@ -8479,8 +8501,22 @@ s390_function_value (const_tree type, const_tree fn, enum machine_mode mode) ...@@ -8479,8 +8501,22 @@ s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode)) if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
return gen_rtx_REG (mode, 16); return gen_rtx_REG (mode, 16);
else else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
|| UNITS_PER_LONG == UNITS_PER_WORD)
return gen_rtx_REG (mode, 2); return gen_rtx_REG (mode, 2);
else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
{
rtvec p = rtvec_alloc (2);
RTVEC_ELT (p, 0)
= gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
RTVEC_ELT (p, 1)
= gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
return gen_rtx_PARALLEL (mode, p);
}
gcc_unreachable ();
} }
...@@ -8628,7 +8664,7 @@ s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) ...@@ -8628,7 +8664,7 @@ s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
{ {
t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx); t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t, t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
size_int (-RETURN_REGNUM * UNITS_PER_WORD)); size_int (-RETURN_REGNUM * UNITS_PER_LONG));
t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
TREE_SIDE_EFFECTS (t) = 1; TREE_SIDE_EFFECTS (t) = 1;
...@@ -8702,9 +8738,9 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, ...@@ -8702,9 +8738,9 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
/* kernel stack layout on 31 bit: It is assumed here that no padding /* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */ number of gprs has to be saved r15-r2 = 14 regs. */
sav_ofs = 2 * UNITS_PER_WORD; sav_ofs = 2 * UNITS_PER_LONG;
sav_scale = UNITS_PER_WORD; sav_scale = UNITS_PER_LONG;
size = UNITS_PER_WORD; size = UNITS_PER_LONG;
max_reg = GP_ARG_NUM_REG - n_reg; max_reg = GP_ARG_NUM_REG - n_reg;
} }
else if (s390_function_arg_float (TYPE_MODE (type), type)) else if (s390_function_arg_float (TYPE_MODE (type), type))
...@@ -8719,7 +8755,7 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, ...@@ -8719,7 +8755,7 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
indirect_p = 0; indirect_p = 0;
reg = fpr; reg = fpr;
n_reg = 1; n_reg = 1;
sav_ofs = 16 * UNITS_PER_WORD; sav_ofs = 16 * UNITS_PER_LONG;
sav_scale = 8; sav_scale = 8;
max_reg = FP_ARG_NUM_REG - n_reg; max_reg = FP_ARG_NUM_REG - n_reg;
} }
...@@ -8734,17 +8770,17 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, ...@@ -8734,17 +8770,17 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
/* Otherwise into GP registers. */ /* Otherwise into GP registers. */
indirect_p = 0; indirect_p = 0;
reg = gpr; reg = gpr;
n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
/* kernel stack layout on 31 bit: It is assumed here that no padding /* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */ number of gprs has to be saved r15-r2 = 14 regs. */
sav_ofs = 2 * UNITS_PER_WORD; sav_ofs = 2 * UNITS_PER_LONG;
if (size < UNITS_PER_WORD) if (size < UNITS_PER_LONG)
sav_ofs += UNITS_PER_WORD - size; sav_ofs += UNITS_PER_LONG - size;
sav_scale = UNITS_PER_WORD; sav_scale = UNITS_PER_LONG;
max_reg = GP_ARG_NUM_REG - n_reg; max_reg = GP_ARG_NUM_REG - n_reg;
} }
...@@ -8776,9 +8812,9 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, ...@@ -8776,9 +8812,9 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
/* ... Otherwise out of the overflow area. */ /* ... Otherwise out of the overflow area. */
t = ovf; t = ovf;
if (size < UNITS_PER_WORD) if (size < UNITS_PER_LONG)
t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
size_int (UNITS_PER_WORD - size)); size_int (UNITS_PER_LONG - size));
gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
...@@ -9002,7 +9038,7 @@ s390_function_profiler (FILE *file, int labelno) ...@@ -9002,7 +9038,7 @@ s390_function_profiler (FILE *file, int labelno)
op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM); op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD)); op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
op[2] = gen_rtx_REG (Pmode, 1); op[2] = gen_rtx_REG (Pmode, 1);
op[3] = gen_rtx_SYMBOL_REF (Pmode, label); op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
...@@ -9408,14 +9444,50 @@ s390_call_saved_register_used (tree call_expr) ...@@ -9408,14 +9444,50 @@ s390_call_saved_register_used (tree call_expr)
s390_function_arg_advance (&cum, mode, type, 0); s390_function_arg_advance (&cum, mode, type, 0);
if (parm_rtx && REG_P (parm_rtx)) if (!parm_rtx)
continue;
if (REG_P (parm_rtx))
{
int n_regs;
/* Only integer registers (r6) are call saved and used for
parameter passing. */
if (REGNO_REG_CLASS (REGNO (parm_rtx)) == FP_REGS)
continue;
n_regs = ((GET_MODE_SIZE (GET_MODE (parm_rtx)) + UNITS_PER_LONG - 1)
/ UNITS_PER_LONG);
for (reg = 0; reg < n_regs; reg++)
if (!call_used_regs[reg + REGNO (parm_rtx)])
return true;
}
if (GET_CODE (parm_rtx) == PARALLEL)
{ {
for (reg = 0; int i;
reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx)); for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
reg++) {
if (! call_used_regs[reg + REGNO (parm_rtx)]) rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
return true; int n_regs;
gcc_assert (REG_P (r));
/* Only integer registers (r6) are call saved and used
for parameter passing. */
if (REGNO_REG_CLASS (REGNO (r)) == FP_REGS)
continue;
n_regs = ((GET_MODE_SIZE (GET_MODE (r)) + UNITS_PER_LONG - 1)
/ UNITS_PER_LONG);
for (reg = 0; reg < n_regs; reg++)
if (!call_used_regs[reg + REGNO (r)])
return true;
}
} }
} }
return false; return false;
} }
...@@ -9661,7 +9733,7 @@ s390_optimize_prologue (void) ...@@ -9661,7 +9733,7 @@ s390_optimize_prologue (void)
{ {
new_insn = save_gprs (base, new_insn = save_gprs (base,
off + (cfun_frame_layout.first_save_gpr off + (cfun_frame_layout.first_save_gpr
- first) * UNITS_PER_WORD, - first) * UNITS_PER_LONG,
cfun_frame_layout.first_save_gpr, cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr); cfun_frame_layout.last_save_gpr);
new_insn = emit_insn_before (new_insn, insn); new_insn = emit_insn_before (new_insn, insn);
...@@ -9722,7 +9794,7 @@ s390_optimize_prologue (void) ...@@ -9722,7 +9794,7 @@ s390_optimize_prologue (void)
{ {
new_insn = restore_gprs (base, new_insn = restore_gprs (base,
off + (cfun_frame_layout.first_restore_gpr off + (cfun_frame_layout.first_restore_gpr
- first) * UNITS_PER_WORD, - first) * UNITS_PER_LONG,
cfun_frame_layout.first_restore_gpr, cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr); cfun_frame_layout.last_restore_gpr);
new_insn = emit_insn_before (new_insn, insn); new_insn = emit_insn_before (new_insn, insn);
...@@ -10319,12 +10391,16 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) ...@@ -10319,12 +10391,16 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
#undef TARGET_DEFAULT_TARGET_FLAGS #undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD) #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
#undef TARGET_HANDLE_OPTION #undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION s390_handle_option #define TARGET_HANDLE_OPTION s390_handle_option
#undef TARGET_ENCODE_SECTION_INFO #undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
#ifdef HAVE_AS_TLS #ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS #undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true #define TARGET_HAVE_TLS true
...@@ -10438,6 +10514,9 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) ...@@ -10438,6 +10514,9 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
#undef TARGET_TRAMPOLINE_INIT #undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT s390_trampoline_init #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
#undef TARGET_UNWIND_WORD_MODE
#define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
struct gcc_target targetm = TARGET_INITIALIZER; struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-s390.h" #include "gt-s390.h"
gcc/config/s390/s390.h
...@@ -108,6 +108,8 @@ extern int s390_arch_flags; ...@@ -108,6 +108,8 @@ extern int s390_arch_flags;
builtin_assert ("cpu=s390"); \ builtin_assert ("cpu=s390"); \
builtin_assert ("machine=s390"); \ builtin_assert ("machine=s390"); \
builtin_define ("__s390__"); \ builtin_define ("__s390__"); \
if (TARGET_ZARCH) \
builtin_define ("__zarch__"); \
if (TARGET_64BIT) \ if (TARGET_64BIT) \
builtin_define ("__s390x__"); \ builtin_define ("__s390x__"); \
if (TARGET_LONG_DOUBLE_128) \ if (TARGET_LONG_DOUBLE_128) \
...@@ -185,17 +187,6 @@ extern int s390_arch_flags; ...@@ -185,17 +187,6 @@ extern int s390_arch_flags;
#define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
| S390_TDC_NEGATIVE_INFINITY ) | S390_TDC_NEGATIVE_INFINITY )
/* In libgcc2, determine target settings as compile-time constants. */
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __s390x__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
/* Target machine storage layout. */ /* Target machine storage layout. */
/* Everything is big-endian. */ /* Everything is big-endian. */
...@@ -203,12 +194,33 @@ extern int s390_arch_flags; ...@@ -203,12 +194,33 @@ extern int s390_arch_flags;
#define BYTES_BIG_ENDIAN 1 #define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1 #define WORDS_BIG_ENDIAN 1
/* Width of a word, in units (bytes). */ #define STACK_SIZE_MODE (Pmode)
#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#ifndef IN_LIBGCC2 #ifndef IN_LIBGCC2
#define MIN_UNITS_PER_WORD 4
/* Width of a word, in units (bytes). */
#define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
/* Width of a pointer. To be used instead of UNITS_PER_WORD in
ABI-relevant contexts. This always matches
GET_MODE_SIZE (Pmode). */
#define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
#define MIN_UNITS_PER_WORD 4
#define MAX_BITS_PER_WORD 64
#else
/* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
the library should export TImode functions or not. Thus, we have
to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */
#ifdef __s390x__
#define UNITS_PER_WORD 8
#else
#define UNITS_PER_WORD 4
#endif
#endif #endif
#define MAX_BITS_PER_WORD 64
/* Width of a pointer, in bits. */
#define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
/* Allocation boundary (in *bits*) for storing arguments in argument list. */ /* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
...@@ -402,6 +414,15 @@ extern int s390_arch_flags; ...@@ -402,6 +414,15 @@ extern int s390_arch_flags;
(((MODE1) == SFmode || (MODE1) == DFmode) \ (((MODE1) == SFmode || (MODE1) == DFmode) \
== ((MODE2) == SFmode || (MODE2) == DFmode)) == ((MODE2) == SFmode || (MODE2) == DFmode))
/* When generating code that runs in z/Architecture mode,
but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
the ABI guarantees only that the lower 4 bytes are
saved across calls, however. */
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
(!TARGET_64BIT && TARGET_ZARCH \
&& GET_MODE_SIZE (MODE) > 4 \
&& (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
/* Maximum number of registers to represent a value of mode MODE /* Maximum number of registers to represent a value of mode MODE
in a register of class CLASS. */ in a register of class CLASS. */
#define CLASS_MAX_NREGS(CLASS, MODE) \ #define CLASS_MAX_NREGS(CLASS, MODE) \
...@@ -573,7 +594,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; ...@@ -573,7 +594,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
the corresponding RETURN_REGNUM register was saved. */ the corresponding RETURN_REGNUM register was saved. */
#define DYNAMIC_CHAIN_ADDRESS(FRAME) \ #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
(TARGET_PACKED_STACK ? \ (TARGET_PACKED_STACK ? \
plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME)) plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
/* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
builtin_frame_address. Otherwise arg pointer - builtin_frame_address. Otherwise arg pointer -
...@@ -609,6 +630,9 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; ...@@ -609,6 +630,9 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
: DW_EH_PE_absptr) : DW_EH_PE_absptr)
/* Register save slot alignment. */
#define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
/* Frame registers. */ /* Frame registers. */
...@@ -790,19 +814,19 @@ do { \ ...@@ -790,19 +814,19 @@ do { \
/* The maximum number of bytes that a single instruction can move quickly /* The maximum number of bytes that a single instruction can move quickly
between memory and registers or between two memory locations. */ between memory and registers or between two memory locations. */
#define MOVE_MAX (TARGET_64BIT ? 16 : 8) #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
#define MAX_MOVE_MAX 16 #define MAX_MOVE_MAX 16
/* Determine whether to use move_by_pieces or block move insn. */ /* Determine whether to use move_by_pieces or block move insn. */
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \ #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
|| (TARGET_64BIT && (SIZE) == 8) ) || (TARGET_ZARCH && (SIZE) == 8) )
/* Determine whether to use clear_by_pieces or block clear insn. */ /* Determine whether to use clear_by_pieces or block clear insn. */
#define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
|| (TARGET_64BIT && (SIZE) == 8) ) || (TARGET_ZARCH && (SIZE) == 8) )
/* This macro is used to determine whether store_by_pieces should be /* This macro is used to determine whether store_by_pieces should be
called to "memcpy" storage when the source is a constant string. */ called to "memcpy" storage when the source is a constant string. */
...@@ -907,7 +931,7 @@ do { \ ...@@ -907,7 +931,7 @@ do { \
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
do { \ do { \
char buf[32]; \ char buf[32]; \
fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
assemble_name ((FILE), buf); \ assemble_name ((FILE), buf); \
fputc ('\n', (FILE)); \ fputc ('\n', (FILE)); \
...@@ -917,7 +941,7 @@ do { \ ...@@ -917,7 +941,7 @@ do { \
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
do { \ do { \
char buf[32]; \ char buf[32]; \
fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
assemble_name ((FILE), buf); \ assemble_name ((FILE), buf); \
fputc ('-', (FILE)); \ fputc ('-', (FILE)); \
......
gcc/config/s390/s390.md
...@@ -337,21 +337,25 @@ ...@@ -337,21 +337,25 @@
;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template. ;; from the same template.
(define_mode_iterator GPR [(DI "TARGET_64BIT") SI]) (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
(define_mode_iterator DSI [DI SI]) (define_mode_iterator DSI [DI SI])
;; These mode iterators allow :P to be used for patterns that operate on ;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match. ;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
;; These macros refer to the actual word_mode of the configuration. This is equal
;; to Pmode except on 31-bit machines in zarch mode.
(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
;; This mode iterator allows the QI and HI patterns to be defined from ;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template. ;; the same template.
(define_mode_iterator HQI [HI QI]) (define_mode_iterator HQI [HI QI])
;; This mode iterator allows the integer patterns to be defined from the ;; This mode iterator allows the integer patterns to be defined from the
;; same template. ;; same template.
(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
(define_mode_iterator INTALL [TI DI SI HI QI]) (define_mode_iterator INTALL [TI DI SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
...@@ -455,7 +459,7 @@ ...@@ -455,7 +459,7 @@
;; variant for long displacements. ;; variant for long displacements.
(define_mode_attr y [(DI "g") (SI "y")]) (define_mode_attr y [(DI "g") (SI "y")])
;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode. ;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")]) (define_mode_attr tg [(TI "g") (DI "")])
...@@ -506,7 +510,7 @@ ...@@ -506,7 +510,7 @@
(match_operand:DI 1 "immediate_operand" (match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0")) "N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))] (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
"TARGET_64BIT "TARGET_ZARCH
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0" && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@ "@
...@@ -556,7 +560,7 @@ ...@@ -556,7 +560,7 @@
(match_operand:DI 1 "const0_operand" ""))) (match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d") (set (match_operand:DI 2 "register_operand" "=d,d")
(sign_extend:DI (match_dup 0)))] (sign_extend:DI (match_dup 0)))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
"ltgfr\t%2,%0 "ltgfr\t%2,%0
ltgf\t%2,%0" ltgf\t%2,%0"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RXY")
...@@ -596,7 +600,7 @@ ...@@ -596,7 +600,7 @@
(match_operand:DI 1 "const0_operand" ""))) (match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d") (set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))] (match_dup 0))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
"ltgr\t%2,%0" "ltgr\t%2,%0"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_fr_E1")]) (set_attr "z10prop" "z10_fr_E1")])
...@@ -632,7 +636,7 @@ ...@@ -632,7 +636,7 @@
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d") (compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))] (match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
"srda\t%0,0" "srda\t%0,0"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -720,7 +724,7 @@ ...@@ -720,7 +724,7 @@
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@ "@
cgr\t%0,%1 cgr\t%0,%1
cghi\t%0,%h1 cghi\t%0,%h1
...@@ -752,7 +756,7 @@ ...@@ -752,7 +756,7 @@
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b")) "d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))] (match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@ "@
cgfr\t%0,%1 cgfr\t%0,%1
cgf\t%0,%1 cgf\t%0,%1
...@@ -847,7 +851,7 @@ ...@@ -847,7 +851,7 @@
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b")) "d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))] (match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@ "@
clgfr\t%0,%1 clgfr\t%0,%1
clgf\t%0,%1 clgf\t%0,%1
...@@ -863,7 +867,7 @@ ...@@ -863,7 +867,7 @@
"d, d,d,Q, d, Q,BQ") "d, d,d,Q, d, Q,BQ")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
"d,Op,b,D,RT,BQ,Q")))] "d,Op,b,D,RT,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@ "@
clgr\t%0,%1 clgr\t%0,%1
clgfi\t%0,%1 clgfi\t%0,%1
...@@ -1115,7 +1119,7 @@ ...@@ -1115,7 +1119,7 @@
(define_insn "movti" (define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
(match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
lmg\t%0,%N0,%S1 lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0 stmg\t%1,%N1,%S0
...@@ -1127,7 +1131,7 @@ ...@@ -1127,7 +1131,7 @@
(define_split (define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "") [(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))] (match_operand:TI 1 "general_operand" ""))]
"TARGET_64BIT && reload_completed "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)" && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -1141,7 +1145,7 @@ ...@@ -1141,7 +1145,7 @@
(define_split (define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "") [(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))] (match_operand:TI 1 "general_operand" ""))]
"TARGET_64BIT && reload_completed "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)" && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -1155,11 +1159,12 @@ ...@@ -1155,11 +1159,12 @@
(define_split (define_split
[(set (match_operand:TI 0 "register_operand" "") [(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))] (match_operand:TI 1 "memory_operand" ""))]
"TARGET_64BIT && reload_completed "TARGET_ZARCH && reload_completed
&& !s_operand (operands[1], VOIDmode)" && !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))] [(set (match_dup 0) (match_dup 1))]
{ {
rtx addr = operand_subword (operands[0], 1, 0, TImode); rtx addr = operand_subword (operands[0], 1, 0, TImode);
addr = gen_lowpart (Pmode, addr);
s390_load_address (addr, XEXP (operands[1], 0)); s390_load_address (addr, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr); operands[1] = replace_equiv_address (operands[1], addr);
}) })
...@@ -1308,7 +1313,7 @@ ...@@ -1308,7 +1313,7 @@
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
lghi\t%0,%h1 lghi\t%0,%h1
llihh\t%0,%i1 llihh\t%0,%i1
...@@ -1375,7 +1380,7 @@ ...@@ -1375,7 +1380,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))] (match_operand:DI 1 "register_operand" ""))]
"TARGET_64BIT && ACCESS_REG_P (operands[1])" "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
[(set (match_dup 2) (match_dup 3)) [(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
(set (strict_low_part (match_dup 2)) (match_dup 4))] (set (strict_low_part (match_dup 2)) (match_dup 4))]
...@@ -1385,7 +1390,7 @@ ...@@ -1385,7 +1390,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))] (match_operand:DI 1 "register_operand" ""))]
"TARGET_64BIT && ACCESS_REG_P (operands[0]) "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& dead_or_set_p (insn, operands[1])" && dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2)) [(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
...@@ -1396,7 +1401,7 @@ ...@@ -1396,7 +1401,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))] (match_operand:DI 1 "register_operand" ""))]
"TARGET_64BIT && ACCESS_REG_P (operands[0]) "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& !dead_or_set_p (insn, operands[1])" && !dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2)) [(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
...@@ -1410,7 +1415,7 @@ ...@@ -1410,7 +1415,7 @@
"=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
" Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"@ "@
lm\t%0,%N0,%S1 lm\t%0,%N0,%S1
lmy\t%0,%N0,%S1 lmy\t%0,%N0,%S1
...@@ -1433,7 +1438,7 @@ ...@@ -1433,7 +1438,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))] (match_operand:DI 1 "memory_operand" ""))]
"!TARGET_64BIT && reload_completed && TARGET_Z10 "!TARGET_ZARCH && reload_completed && TARGET_Z10
&& larl_operand (XEXP (operands[1], 0), SImode)" && larl_operand (XEXP (operands[1], 0), SImode)"
[(set (match_dup 2) (match_dup 3)) [(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (match_dup 1))] (set (match_dup 0) (match_dup 1))]
...@@ -1446,7 +1451,7 @@ ...@@ -1446,7 +1451,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))] (match_operand:DI 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)" && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -1460,7 +1465,7 @@ ...@@ -1460,7 +1465,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))] (match_operand:DI 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)" && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -1474,7 +1479,7 @@ ...@@ -1474,7 +1479,7 @@
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))] (match_operand:DI 1 "memory_operand" ""))]
"!TARGET_64BIT && reload_completed "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0]) && !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)" && !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))] [(set (match_dup 0) (match_dup 1))]
...@@ -1487,7 +1492,7 @@ ...@@ -1487,7 +1492,7 @@
(define_peephole2 (define_peephole2
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(mem:DI (match_operand 1 "address_operand" "")))] (mem:DI (match_operand 1 "address_operand" "")))]
"TARGET_64BIT "TARGET_ZARCH
&& !FP_REG_P (operands[0]) && !FP_REG_P (operands[0])
&& GET_CODE (operands[1]) == SYMBOL_REF && GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1]) && CONSTANT_POOL_ADDRESS_P (operands[1])
...@@ -1826,8 +1831,8 @@ ...@@ -1826,8 +1831,8 @@
&& register_operand (operands[0], VOIDmode) && register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM) && GET_CODE (operands[1]) == MEM)
{ {
rtx tmp = gen_reg_rtx (word_mode); rtx tmp = gen_reg_rtx (DImode);
rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
operands[1] = gen_lowpart (QImode, tmp); operands[1] = gen_lowpart (QImode, tmp);
} }
...@@ -1905,7 +1910,7 @@ ...@@ -1905,7 +1910,7 @@
(define_insn "movstrictsi" (define_insn "movstrictsi"
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
(match_operand:SI 1 "general_operand" "d,R,T,t"))] (match_operand:SI 1 "general_operand" "d,R,T,t"))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
lr\t%0,%1 lr\t%0,%1
l\t%0,%1 l\t%0,%1
...@@ -1928,7 +1933,7 @@ ...@@ -1928,7 +1933,7 @@
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
lzxr\t%0 lzxr\t%0
lxr\t%0,%1 lxr\t%0,%1
...@@ -1944,7 +1949,7 @@ ...@@ -1944,7 +1949,7 @@
(define_insn "*mov<mode>_31" (define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"@ "@
lzxr\t%0 lzxr\t%0
lxr\t%0,%1 lxr\t%0,%1
...@@ -1958,7 +1963,7 @@ ...@@ -1958,7 +1963,7 @@
(define_split (define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))] (match_operand:TD_TF 1 "general_operand" ""))]
"TARGET_64BIT && reload_completed "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -1972,7 +1977,7 @@ ...@@ -1972,7 +1977,7 @@
(define_split (define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))] (match_operand:TD_TF 1 "general_operand" ""))]
"TARGET_64BIT && reload_completed "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -1986,7 +1991,7 @@ ...@@ -1986,7 +1991,7 @@
(define_split (define_split
[(set (match_operand:TD_TF 0 "register_operand" "") [(set (match_operand:TD_TF 0 "register_operand" "")
(match_operand:TD_TF 1 "memory_operand" ""))] (match_operand:TD_TF 1 "memory_operand" ""))]
"TARGET_64BIT && reload_completed "TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0]) && !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)" && !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))] [(set (match_dup 0) (match_dup 1))]
...@@ -2045,7 +2050,7 @@ ...@@ -2045,7 +2050,7 @@
"=f,f,f,d,f,f,R,T,d, d,RT") "=f,f,f,d,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" G,f,d,f,R,T,f,f,d,RT, d"))] " G,f,d,f,R,T,f,f,d,RT, d"))]
"TARGET_64BIT && TARGET_DFP" "TARGET_DFP"
"@ "@
lzdr\t%0 lzdr\t%0
ldr\t%0,%1 ldr\t%0,%1
...@@ -2077,7 +2082,7 @@ ...@@ -2077,7 +2082,7 @@
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))] (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
lzdr\t%0 lzdr\t%0
ldr\t%0,%1 ldr\t%0,%1
...@@ -2106,7 +2111,7 @@ ...@@ -2106,7 +2111,7 @@
"=f,f,f,f,R,T,d,d,Q,S, d,o") "=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"@ "@
lzdr\t%0 lzdr\t%0
ldr\t%0,%1 ldr\t%0,%1
...@@ -2127,7 +2132,7 @@ ...@@ -2127,7 +2132,7 @@
(define_split (define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))] (match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -2141,7 +2146,7 @@ ...@@ -2141,7 +2146,7 @@
(define_split (define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))] (match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))] (set (match_dup 3) (match_dup 5))]
...@@ -2155,7 +2160,7 @@ ...@@ -2155,7 +2160,7 @@
(define_split (define_split
[(set (match_operand:DD_DF 0 "register_operand" "") [(set (match_operand:DD_DF 0 "register_operand" "")
(match_operand:DD_DF 1 "memory_operand" ""))] (match_operand:DD_DF 1 "memory_operand" ""))]
"!TARGET_64BIT && reload_completed "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0]) && !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)" && !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))] [(set (match_dup 0) (match_dup 1))]
...@@ -2304,7 +2309,7 @@ ...@@ -2304,7 +2309,7 @@
count = INTVAL (operands[2]); count = INTVAL (operands[2]);
regno = REGNO (operands[0]); regno = REGNO (operands[0]);
mode = GET_MODE (operands[0]); mode = GET_MODE (operands[0]);
if (mode != SImode && mode != word_mode) if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL; FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
...@@ -2342,7 +2347,7 @@ ...@@ -2342,7 +2347,7 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r") [(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])] (match_operand:DI 2 "s_operand" "QS"))])]
"reload_completed && word_mode == DImode" "reload_completed && TARGET_ZARCH"
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
...@@ -2393,7 +2398,7 @@ ...@@ -2393,7 +2398,7 @@
count = INTVAL (operands[2]); count = INTVAL (operands[2]);
regno = REGNO (operands[1]); regno = REGNO (operands[1]);
mode = GET_MODE (operands[1]); mode = GET_MODE (operands[1]);
if (mode != SImode && mode != word_mode) if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL; FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
...@@ -2433,7 +2438,7 @@ ...@@ -2433,7 +2438,7 @@
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS") [(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])] (match_operand:DI 2 "register_operand" "r"))])]
"reload_completed && word_mode == DImode" "reload_completed && TARGET_ZARCH"
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
...@@ -2715,11 +2720,12 @@ ...@@ -2715,11 +2720,12 @@
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
"" ""
{ {
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
rtx reg0 = gen_reg_rtx (dword_mode); enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
rtx reg1 = gen_reg_rtx (dword_mode); rtx reg0 = gen_reg_rtx (dreg_mode);
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); rtx reg1 = gen_reg_rtx (dreg_mode);
rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0); rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1); rtx len1 = gen_lowpart (Pmode, reg1);
...@@ -2745,7 +2751,20 @@ ...@@ -2745,7 +2751,20 @@
(use (match_dup 2)) (use (match_dup 2))
(use (match_dup 3)) (use (match_dup 3))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" "TARGET_64BIT || !TARGET_ZARCH"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
(define_insn "*movmem_long_31z"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(clobber (match_operand:TI 1 "register_operand" "=d"))
(set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
(mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
(use (match_dup 2))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,0\;jo\t.-4" "mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8") [(set_attr "length" "8")
(set_attr "type" "vs")]) (set_attr "type" "vs")])
...@@ -2917,10 +2936,11 @@ ...@@ -2917,10 +2936,11 @@
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
"" ""
{ {
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
rtx reg0 = gen_reg_rtx (dword_mode); enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
rtx reg1 = gen_reg_rtx (dword_mode); rtx reg0 = gen_reg_rtx (dreg_mode);
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); rtx reg1 = gen_reg_rtx (dreg_mode);
rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
rtx len0 = gen_lowpart (Pmode, reg0); rtx len0 = gen_lowpart (Pmode, reg0);
emit_clobber (reg0); emit_clobber (reg0);
...@@ -2941,7 +2961,7 @@ ...@@ -2941,7 +2961,7 @@
(use (match_dup 3)) (use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d")) (use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" "TARGET_64BIT || !TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4" "mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8") [(set_attr "length" "8")
(set_attr "type" "vs")]) (set_attr "type" "vs")])
...@@ -2954,10 +2974,24 @@ ...@@ -2954,10 +2974,24 @@
(use (match_dup 3)) (use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d")) (use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"(INTVAL (operands[4]) & 255) == 255" "(TARGET_64BIT || !TARGET_ZARCH) &&
(INTVAL (operands[4]) & 255) == 255"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
(define_insn "*setmem_long_31z"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
(match_operand 2 "shift_count_or_setmem_operand" "Y"))
(use (match_dup 3))
(use (match_operand:TI 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4" "mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8") [(set_attr "length" "8")
(set_attr "type" "vs")]) (set_attr "type" "vs")])
; ;
; cmpmemM instruction pattern(s). ; cmpmemM instruction pattern(s).
; ;
...@@ -3071,11 +3105,12 @@ ...@@ -3071,11 +3105,12 @@
(use (match_dup 3))])] (use (match_dup 3))])]
"" ""
{ {
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
rtx reg0 = gen_reg_rtx (dword_mode); enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
rtx reg1 = gen_reg_rtx (dword_mode); rtx reg0 = gen_reg_rtx (dreg_mode);
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); rtx reg1 = gen_reg_rtx (dreg_mode);
rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0); rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1); rtx len1 = gen_lowpart (Pmode, reg1);
...@@ -3101,11 +3136,25 @@ ...@@ -3101,11 +3136,25 @@
(mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
(use (match_dup 2)) (use (match_dup 2))
(use (match_dup 3))] (use (match_dup 3))]
"" "TARGET_64BIT || !TARGET_ZARCH"
"clcle\t%0,%1,0\;jo\t.-4" "clcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8") [(set_attr "length" "8")
(set_attr "type" "vs")]) (set_attr "type" "vs")])
(define_insn "*cmpmem_long_31z"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(clobber (match_operand:TI 1 "register_operand" "=d"))
(set (reg:CCU CC_REGNUM)
(compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
(mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
(use (match_dup 2))
(use (match_dup 3))]
"!TARGET_64BIT && TARGET_ZARCH"
"clcle\t%0,%1,0\;jo\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
(set_attr "length" "8")])
; Convert CCUmode condition code to integer. ; Convert CCUmode condition code to integer.
; Result is zero if EQ, positive if LTU, negative if GTU. ; Result is zero if EQ, positive if LTU, negative if GTU.
...@@ -3147,7 +3196,7 @@ ...@@ -3147,7 +3196,7 @@
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CCU_TO_INT))) UNSPEC_CCU_TO_INT)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
...@@ -3164,7 +3213,7 @@ ...@@ -3164,7 +3213,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
...@@ -3199,7 +3248,7 @@ ...@@ -3199,7 +3248,7 @@
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS") (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"icmh\t%0,%2,%S1" "icmh\t%0,%2,%S1"
[(set_attr "op_type" "RSY") [(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")]) (set_attr "z10prop" "z10_super")])
...@@ -3209,7 +3258,7 @@ ...@@ -3209,7 +3258,7 @@
(unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"@ "@
icm\t%0,%2,%S1 icm\t%0,%2,%S1
icmy\t%0,%2,%S1" icmy\t%0,%2,%S1"
...@@ -3365,10 +3414,10 @@ ...@@ -3365,10 +3414,10 @@
[(set_attr "op_type" "RIE")]) [(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg" (define_insn "*insv<mode>_mem_reg"
[(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n") (match_operand 1 "const_int_operand" "n,n")
(const_int 0)) (const_int 0))
(match_operand:P 2 "register_operand" "d,d"))] (match_operand:W 2 "register_operand" "d,d"))]
"INTVAL (operands[1]) > 0 "INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0" && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
...@@ -3388,7 +3437,7 @@ ...@@ -3388,7 +3437,7 @@
(const_int 0)) (const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d") (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))] (const_int 32)))]
"TARGET_64BIT "TARGET_ZARCH
&& INTVAL (operands[1]) > 0 && INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0" && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
...@@ -3401,11 +3450,11 @@ ...@@ -3401,11 +3450,11 @@
[(set_attr "op_type" "RSY") [(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")]) (set_attr "z10prop" "z10_super")])
(define_insn "*insv<mode>_reg_imm" (define_insn "*insvdi_reg_imm"
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
(const_int 16) (const_int 16)
(match_operand 1 "const_int_operand" "n")) (match_operand 1 "const_int_operand" "n"))
(match_operand:P 2 "const_int_operand" "n"))] (match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH "TARGET_ZARCH
&& INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD && INTVAL (operands[1]) < BITS_PER_WORD
...@@ -3455,7 +3504,7 @@ ...@@ -3455,7 +3504,7 @@
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
"" ""
{ {
if (!TARGET_64BIT) if (!TARGET_ZARCH)
{ {
emit_clobber (operands[0]); emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
...@@ -3468,7 +3517,7 @@ ...@@ -3468,7 +3517,7 @@
(define_insn "*extendsidi2" (define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
lgfr\t%0,%1 lgfr\t%0,%1
lgf\t%0,%1 lgf\t%0,%1
...@@ -3487,7 +3536,7 @@ ...@@ -3487,7 +3536,7 @@
(sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
"" ""
{ {
if (<DSI:MODE>mode == DImode && !TARGET_64BIT) if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
...@@ -3513,7 +3562,7 @@ ...@@ -3513,7 +3562,7 @@
(define_insn "*extendhidi2_extimm" (define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
"TARGET_64BIT && TARGET_EXTIMM" "TARGET_ZARCH && TARGET_EXTIMM"
"@ "@
lghr\t%0,%1 lghr\t%0,%1
lgh\t%0,%1 lgh\t%0,%1
...@@ -3526,7 +3575,7 @@ ...@@ -3526,7 +3575,7 @@
(define_insn "*extendhidi2" (define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
"TARGET_64BIT" "TARGET_ZARCH"
"lgh\t%0,%1" "lgh\t%0,%1"
[(set_attr "op_type" "RXY") [(set_attr "op_type" "RXY")
(set_attr "z10prop" "z10_super_E1")]) (set_attr "z10prop" "z10_super_E1")])
...@@ -3612,7 +3661,7 @@ ...@@ -3612,7 +3661,7 @@
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
"" ""
{ {
if (!TARGET_64BIT) if (!TARGET_ZARCH)
{ {
emit_clobber (operands[0]); emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
...@@ -3624,7 +3673,7 @@ ...@@ -3624,7 +3673,7 @@
(define_insn "*zero_extendsidi2" (define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
llgfr\t%0,%1 llgfr\t%0,%1
llgf\t%0,%1 llgf\t%0,%1
...@@ -3642,7 +3691,7 @@ ...@@ -3642,7 +3691,7 @@
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))] (const_int 2147483647)))]
"TARGET_64BIT" "TARGET_ZARCH"
"llgt\t%0,%1" "llgt\t%0,%1"
[(set_attr "op_type" "RXE") [(set_attr "op_type" "RXE")
(set_attr "z10prop" "z10_super_E1")]) (set_attr "z10prop" "z10_super_E1")])
...@@ -3652,7 +3701,7 @@ ...@@ -3652,7 +3701,7 @@
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647))) (const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
...@@ -3675,7 +3724,7 @@ ...@@ -3675,7 +3724,7 @@
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
(const_int 2147483647)))] (const_int 2147483647)))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
llgtr\t%0,%1 llgtr\t%0,%1
llgt\t%0,%N1" llgt\t%0,%N1"
...@@ -3683,13 +3732,13 @@ ...@@ -3683,13 +3732,13 @@
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_split (define_split
[(set (match_operand:GPR 0 "register_operand" "") [(set (match_operand:DSI 0 "register_operand" "")
(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
(const_int 2147483647))) (const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && reload_completed" "TARGET_ZARCH && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(and:GPR (match_dup 1) (and:DSI (match_dup 1)
(const_int 2147483647)))] (const_int 2147483647)))]
"") "")
...@@ -3702,7 +3751,7 @@ ...@@ -3702,7 +3751,7 @@
(zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
"" ""
{ {
if (!TARGET_64BIT) if (!TARGET_ZARCH)
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
...@@ -3954,7 +4003,7 @@ ...@@ -3954,7 +4003,7 @@
(define_expand "fix_trunc<mode>di2" (define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
"TARGET_64BIT && TARGET_HARD_DFP" "TARGET_ZARCH && TARGET_HARD_DFP"
{ {
operands[1] = force_reg (<MODE>mode, operands[1]); operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
...@@ -3968,7 +4017,7 @@ ...@@ -3968,7 +4017,7 @@
(fix:DI (match_operand:DFP 1 "register_operand" "f"))) (fix:DI (match_operand:DFP 1 "register_operand" "f")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && TARGET_HARD_DFP" "TARGET_ZARCH && TARGET_HARD_DFP"
"cg<DFP:xde>tr\t%0,%h2,%1" "cg<DFP:xde>tr\t%0,%h2,%1"
[(set_attr "op_type" "RRF") [(set_attr "op_type" "RRF")
(set_attr "type" "ftoidfp")]) (set_attr "type" "ftoidfp")])
...@@ -3995,7 +4044,7 @@ ...@@ -3995,7 +4044,7 @@
(define_insn "floatdi<mode>2" (define_insn "floatdi<mode>2"
[(set (match_operand:FP 0 "register_operand" "=f") [(set (match_operand:FP 0 "register_operand" "=f")
(float:FP (match_operand:DI 1 "register_operand" "d")))] (float:FP (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT" "TARGET_ZARCH && TARGET_HARD_FLOAT"
"c<xde>g<bt>r\t%0,%1" "c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )]) (set_attr "type" "itof<mode>" )])
...@@ -4237,7 +4286,7 @@ ...@@ -4237,7 +4286,7 @@
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) ) (match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(parallel
...@@ -4275,7 +4324,7 @@ ...@@ -4275,7 +4324,7 @@
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0"))) (match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
agfr\t%0,%2 agfr\t%0,%2
agf\t%0,%2" agf\t%0,%2"
...@@ -4288,7 +4337,7 @@ ...@@ -4288,7 +4337,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@ "@
algfr\t%0,%2 algfr\t%0,%2
algf\t%0,%2" algf\t%0,%2"
...@@ -4301,7 +4350,7 @@ ...@@ -4301,7 +4350,7 @@
(match_operand:DI 1 "register_operand" "0,0")) (match_operand:DI 1 "register_operand" "0,0"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@ "@
algfr\t%0,%2 algfr\t%0,%2
algf\t%0,%2" algf\t%0,%2"
...@@ -4313,7 +4362,7 @@ ...@@ -4313,7 +4362,7 @@
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0"))) (match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
algfr\t%0,%2 algfr\t%0,%2
algf\t%0,%2" algf\t%0,%2"
...@@ -4325,7 +4374,7 @@ ...@@ -4325,7 +4374,7 @@
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) ) (match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH" "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(parallel
...@@ -4645,7 +4694,7 @@ ...@@ -4645,7 +4694,7 @@
(minus:TI (match_operand:TI 1 "register_operand" "0") (minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) ) (match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(parallel
...@@ -4682,7 +4731,7 @@ ...@@ -4682,7 +4731,7 @@
(minus:DI (match_operand:DI 1 "register_operand" "0,0") (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
sgfr\t%0,%2 sgfr\t%0,%2
sgf\t%0,%2" sgf\t%0,%2"
...@@ -4696,7 +4745,7 @@ ...@@ -4696,7 +4745,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@ "@
slgfr\t%0,%2 slgfr\t%0,%2
slgf\t%0,%2" slgf\t%0,%2"
...@@ -4709,7 +4758,7 @@ ...@@ -4709,7 +4758,7 @@
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@ "@
slgfr\t%0,%2 slgfr\t%0,%2
slgf\t%0,%2" slgf\t%0,%2"
...@@ -4721,7 +4770,7 @@ ...@@ -4721,7 +4770,7 @@
(minus:DI (match_operand:DI 1 "register_operand" "0,0") (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
slgfr\t%0,%2 slgfr\t%0,%2
slgf\t%0,%2" slgf\t%0,%2"
...@@ -4733,7 +4782,7 @@ ...@@ -4733,7 +4782,7 @@
(minus:DI (match_operand:DI 1 "register_operand" "0") (minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) ) (match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH" "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(parallel
...@@ -5197,7 +5246,7 @@ ...@@ -5197,7 +5246,7 @@
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))] (match_operand:DI 1 "register_operand" "0,0")))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
msgfr\t%0,%2 msgfr\t%0,%2
msgf\t%0,%2" msgf\t%0,%2"
...@@ -5208,7 +5257,7 @@ ...@@ -5208,7 +5257,7 @@
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,RT,Os")))] (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
msgr\t%0,%2 msgr\t%0,%2
mghi\t%0,%h2 mghi\t%0,%h2
...@@ -5259,7 +5308,7 @@ ...@@ -5259,7 +5308,7 @@
(match_operand:SI 1 "register_operand" "%0,0,0")) (match_operand:SI 1 "register_operand" "%0,0,0"))
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"@ "@
mr\t%0,%2 mr\t%0,%2
m\t%0,%2 m\t%0,%2
...@@ -5278,7 +5327,7 @@ ...@@ -5278,7 +5327,7 @@
(match_operand:SI 1 "register_operand" "%0,0")) (match_operand:SI 1 "register_operand" "%0,0"))
(zero_extend:DI (zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH" "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@ "@
mlr\t%0,%2 mlr\t%0,%2
ml\t%0,%2" ml\t%0,%2"
...@@ -5342,7 +5391,7 @@ ...@@ -5342,7 +5391,7 @@
(set (match_operand:DI 3 "general_operand" "") (set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))]) (mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))] (clobber (match_dup 4))]
"TARGET_64BIT" "TARGET_ZARCH"
{ {
rtx insn, div_equal, mod_equal; rtx insn, div_equal, mod_equal;
...@@ -5370,7 +5419,7 @@ ...@@ -5370,7 +5419,7 @@
(match_operand:DI 2 "general_operand" "d,RT"))) (match_operand:DI 2 "general_operand" "d,RT")))
(const_int 64)) (const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
dsgr\t%0,%2 dsgr\t%0,%2
dsg\t%0,%2" dsg\t%0,%2"
...@@ -5388,7 +5437,7 @@ ...@@ -5388,7 +5437,7 @@
(const_int 64)) (const_int 64))
(zero_extend:TI (zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
dsgfr\t%0,%2 dsgfr\t%0,%2
dsgf\t%0,%2" dsgf\t%0,%2"
...@@ -5406,7 +5455,7 @@ ...@@ -5406,7 +5455,7 @@
(set (match_operand:DI 3 "general_operand" "") (set (match_operand:DI 3 "general_operand" "")
(umod:DI (match_dup 1) (match_dup 2)))]) (umod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))] (clobber (match_dup 4))]
"TARGET_64BIT" "TARGET_ZARCH"
{ {
rtx insn, div_equal, mod_equal, equal; rtx insn, div_equal, mod_equal, equal;
...@@ -5448,7 +5497,7 @@ ...@@ -5448,7 +5497,7 @@
(zero_extend:TI (zero_extend:TI
(truncate:DI (truncate:DI
(udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
"TARGET_64BIT" "TARGET_ZARCH"
"@ "@
dlgr\t%0,%2 dlgr\t%0,%2
dlg\t%0,%2" dlg\t%0,%2"
...@@ -5466,7 +5515,7 @@ ...@@ -5466,7 +5515,7 @@
(set (match_operand:SI 3 "general_operand" "") (set (match_operand:SI 3 "general_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))]) (mod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))] (clobber (match_dup 4))]
"!TARGET_64BIT" "!TARGET_ZARCH"
{ {
rtx insn, div_equal, mod_equal, equal; rtx insn, div_equal, mod_equal, equal;
...@@ -5506,7 +5555,7 @@ ...@@ -5506,7 +5555,7 @@
(zero_extend:DI (zero_extend:DI
(truncate:SI (truncate:SI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"@ "@
dr\t%0,%2 dr\t%0,%2
d\t%0,%2" d\t%0,%2"
...@@ -5524,7 +5573,7 @@ ...@@ -5524,7 +5573,7 @@
(set (match_operand:SI 3 "general_operand" "") (set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))]) (umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))] (clobber (match_dup 4))]
"!TARGET_64BIT && TARGET_CPU_ZARCH" "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{ {
rtx insn, div_equal, mod_equal, equal; rtx insn, div_equal, mod_equal, equal;
...@@ -5566,7 +5615,7 @@ ...@@ -5566,7 +5615,7 @@
(zero_extend:DI (zero_extend:DI
(truncate:SI (truncate:SI
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH" "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@ "@
dlr\t%0,%2 dlr\t%0,%2
dl\t%0,%2" dl\t%0,%2"
...@@ -5578,7 +5627,7 @@ ...@@ -5578,7 +5627,7 @@
(udiv:SI (match_operand:SI 1 "general_operand" "") (udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" ""))) (match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))] (clobber (match_dup 3))]
"!TARGET_64BIT && !TARGET_CPU_ZARCH" "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{ {
rtx insn, udiv_equal, umod_equal, equal; rtx insn, udiv_equal, umod_equal, equal;
...@@ -5664,7 +5713,7 @@ ...@@ -5664,7 +5713,7 @@
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "") (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" ""))) (match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))] (clobber (match_dup 3))]
"!TARGET_64BIT && !TARGET_CPU_ZARCH" "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{ {
rtx insn, udiv_equal, umod_equal, equal; rtx insn, udiv_equal, umod_equal, equal;
...@@ -5785,7 +5834,7 @@ ...@@ -5785,7 +5834,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_dup 1) (match_dup 2)))] (and:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
ngr\t%0,%2 ngr\t%0,%2
ng\t%0,%2" ng\t%0,%2"
...@@ -5798,7 +5847,7 @@ ...@@ -5798,7 +5847,7 @@
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */ /* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0" && s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@ "@
...@@ -5814,7 +5863,7 @@ ...@@ -5814,7 +5863,7 @@
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
# #
# #
...@@ -6104,7 +6153,7 @@ ...@@ -6104,7 +6153,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (match_dup 1) (match_dup 2)))] (ior:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
ogr\t%0,%2 ogr\t%0,%2
og\t%0,%2" og\t%0,%2"
...@@ -6117,7 +6166,7 @@ ...@@ -6117,7 +6166,7 @@
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
ogr\t%0,%2 ogr\t%0,%2
og\t%0,%2" og\t%0,%2"
...@@ -6130,7 +6179,7 @@ ...@@ -6130,7 +6179,7 @@
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
oihh\t%0,%i2 oihh\t%0,%i2
oihl\t%0,%i2 oihl\t%0,%i2
...@@ -6404,7 +6453,7 @@ ...@@ -6404,7 +6453,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(xor:DI (match_dup 1) (match_dup 2)))] (xor:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
xgr\t%0,%2 xgr\t%0,%2
xg\t%0,%2" xg\t%0,%2"
...@@ -6417,7 +6466,7 @@ ...@@ -6417,7 +6466,7 @@
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
xgr\t%0,%2 xgr\t%0,%2
xg\t%0,%2" xg\t%0,%2"
...@@ -6429,7 +6478,7 @@ ...@@ -6429,7 +6478,7 @@
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
xihf\t%0,%k2 xihf\t%0,%k2
xilf\t%0,%k2 xilf\t%0,%k2
...@@ -6676,7 +6725,7 @@ ...@@ -6676,7 +6725,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_dup 1))))] (neg:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1" "lcgfr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")])
...@@ -6685,7 +6734,7 @@ ...@@ -6685,7 +6734,7 @@
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"lcgfr\t%0,%1" "lcgfr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")])
...@@ -6727,7 +6776,7 @@ ...@@ -6727,7 +6776,7 @@
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d"))) (neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(parallel
...@@ -6822,7 +6871,7 @@ ...@@ -6822,7 +6871,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_dup 1))))] (abs:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1" "lpgfr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")])
...@@ -6831,7 +6880,7 @@ ...@@ -6831,7 +6880,7 @@
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"lpgfr\t%0,%1" "lpgfr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")])
...@@ -6940,7 +6989,7 @@ ...@@ -6940,7 +6989,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1" "lngfr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")])
...@@ -6950,7 +6999,7 @@ ...@@ -6950,7 +6999,7 @@
(neg:DI (abs:DI (sign_extend:DI (neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d"))))) (match_operand:SI 1 "register_operand" "d")))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
"lngfr\t%0,%1" "lngfr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")])
...@@ -7079,7 +7128,7 @@ ...@@ -7079,7 +7128,7 @@
(define_expand "clzdi2" (define_expand "clzdi2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(clz:DI (match_operand:DI 1 "register_operand" "d")))] (clz:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_EXTIMM && TARGET_64BIT" "TARGET_EXTIMM && TARGET_ZARCH"
{ {
rtx insn, clz_equal; rtx insn, clz_equal;
rtx wide_reg = gen_reg_rtx (TImode); rtx wide_reg = gen_reg_rtx (TImode);
...@@ -7109,7 +7158,7 @@ ...@@ -7109,7 +7158,7 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"(unsigned HOST_WIDE_INT) INTVAL (operands[2]) "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) 1 << 63 == (unsigned HOST_WIDE_INT) 1 << 63
&& TARGET_EXTIMM && TARGET_64BIT" && TARGET_EXTIMM && TARGET_ZARCH"
"flogr\t%0,%1" "flogr\t%0,%1"
[(set_attr "op_type" "RRE")]) [(set_attr "op_type" "RRE")])
...@@ -7166,7 +7215,7 @@ ...@@ -7166,7 +7215,7 @@
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0") (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"s<lr>dl\t%0,%Y2" "s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -7188,7 +7237,7 @@ ...@@ -7188,7 +7237,7 @@
(SHIFT:DI (match_operand:DI 1 "register_operand" "0") (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))] (match_operand:SI 3 "const_int_operand" "n"))))]
"!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"s<lr>dl\t%0,%Y2" "s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -7225,7 +7274,7 @@ ...@@ -7225,7 +7274,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))] (ashiftrt:DI (match_dup 1) (match_dup 2)))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2" "srda\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -7236,7 +7285,7 @@ ...@@ -7236,7 +7285,7 @@
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d"))] (clobber (match_scratch:DI 0 "=d"))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2" "srda\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -7246,7 +7295,7 @@ ...@@ -7246,7 +7295,7 @@
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"srda\t%0,%Y2" "srda\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -7301,7 +7350,7 @@ ...@@ -7301,7 +7350,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63" && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2" "srda\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
...@@ -7314,7 +7363,7 @@ ...@@ -7314,7 +7363,7 @@
(match_operand:SI 3 "const_int_operand" "n"))) (match_operand:SI 3 "const_int_operand" "n")))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d"))] (clobber (match_scratch:DI 0 "=d"))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63" && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2" "srda\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
...@@ -7326,7 +7375,7 @@ ...@@ -7326,7 +7375,7 @@
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n")))) (match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2" "srda\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -7680,7 +7729,7 @@ ...@@ -7680,7 +7729,7 @@
(subreg:DI (match_dup 2) 0))) (subreg:DI (match_dup 2) 0)))
(clobber (match_scratch:DI 4 "=X,&1,&?d")) (clobber (match_scratch:DI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
{ {
if (which_alternative != 0) if (which_alternative != 0)
return "#"; return "#";
...@@ -7723,7 +7772,7 @@ ...@@ -7723,7 +7772,7 @@
(subreg:SI (match_dup 2) 4))) (subreg:SI (match_dup 2) 4)))
(clobber (match_scratch:SI 4 "=X,&1,&?d")) (clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
{ {
if (which_alternative != 0) if (which_alternative != 0)
return "#"; return "#";
...@@ -7766,7 +7815,7 @@ ...@@ -7766,7 +7815,7 @@
(subreg:SI (match_dup 2) 0))) (subreg:SI (match_dup 2) 0)))
(clobber (match_scratch:SI 4 "=X,&1,&?d")) (clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH" "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{ {
if (which_alternative != 0) if (which_alternative != 0)
return "#"; return "#";
...@@ -7808,7 +7857,7 @@ ...@@ -7808,7 +7857,7 @@
emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
else else
FAIL; FAIL;
...@@ -7939,7 +7988,7 @@ ...@@ -7939,7 +7988,7 @@
(plus:DI (match_dup 1) (const_int -1))) (plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&1,&?d")) (clobber (match_scratch:DI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT" "TARGET_ZARCH"
{ {
if (which_alternative != 0) if (which_alternative != 0)
return "#"; return "#";
...@@ -8497,13 +8546,13 @@ ...@@ -8497,13 +8546,13 @@
; cds, cdsg ; cds, cdsg
(define_insn "*sync_compare_and_swap<mode>" (define_insn "*sync_compare_and_swap<mode>"
[(set (match_operand:DP 0 "register_operand" "=r") [(set (match_operand:DW 0 "register_operand" "=r")
(match_operand:DP 1 "memory_operand" "+Q")) (match_operand:DW 1 "memory_operand" "+Q"))
(set (match_dup 1) (set (match_dup 1)
(unspec_volatile:DP (unspec_volatile:DW
[(match_dup 1) [(match_dup 1)
(match_operand:DP 2 "register_operand" "0") (match_operand:DW 2 "register_operand" "0")
(match_operand:DP 3 "register_operand" "r")] (match_operand:DW 3 "register_operand" "r")]
UNSPECV_CAS)) UNSPECV_CAS))
(set (reg:CCZ1 CC_REGNUM) (set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))] (compare:CCZ1 (match_dup 1) (match_dup 2)))]
...@@ -8646,20 +8695,20 @@ ...@@ -8646,20 +8695,20 @@
(match_operand 1 "register_operand" "")] (match_operand 1 "register_operand" "")]
"" ""
{ {
enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
/* Copy the backchain to the first word, sp to the second and the /* Copy the backchain to the first word, sp to the second and the
literal pool base to the third. */ literal pool base to the third. */
rtx save_bc = adjust_address (operands[0], Pmode, 0);
rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
if (TARGET_BACKCHAIN) if (TARGET_BACKCHAIN)
{ emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
}
emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); emit_move_insn (save_sp, operands[1]);
emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); emit_move_insn (save_bp, base);
DONE; DONE;
}) })
...@@ -8669,18 +8718,21 @@ ...@@ -8669,18 +8718,21 @@
(match_operand 1 "memory_operand" "")] (match_operand 1 "memory_operand" "")]
"" ""
{ {
enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
rtx temp = NULL_RTX; rtx temp = NULL_RTX;
/* Restore the backchain from the first word, sp from the second and the /* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */ literal pool base from the third. */
rtx save_bc = adjust_address (operands[1], Pmode, 0);
rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
if (TARGET_BACKCHAIN) if (TARGET_BACKCHAIN)
temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); temp = force_reg (Pmode, save_bc);
emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); emit_move_insn (base, save_bp);
emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); emit_move_insn (operands[0], save_sp);
if (temp) if (temp)
emit_move_insn (s390_back_chain_rtx (), temp); emit_move_insn (s390_back_chain_rtx (), temp);
......
gcc/longlong.h
...@@ -318,6 +318,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -318,6 +318,7 @@ UDItype __umulsidi3 (USItype, USItype);
#endif #endif
#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
#if !defined (__zarch__)
#define smul_ppmm(xh, xl, m0, m1) \ #define smul_ppmm(xh, xl, m0, m1) \
do { \ do { \
union {DItype __ll; \ union {DItype __ll; \
...@@ -339,6 +340,28 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -339,6 +340,28 @@ UDItype __umulsidi3 (USItype, USItype);
: "0" (__x.__ll), "r" (d)); \ : "0" (__x.__ll), "r" (d)); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \ (q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0) } while (0)
#else
#define smul_ppmm(xh, xl, m0, m1) \
do { \
register SItype r0 __asm__ ("0"); \
register SItype r1 __asm__ ("1") = m0; \
\
__asm__ ("mr\t%%r0,%3" \
: "=r" (r0), "=r" (r1) \
: "r" (r1), "r" (m1)); \
(xh) = r1; (xl) = r0; \
} while (0)
#define sdiv_qrnnd(q, r, n1, n0, d) \
do { \
register SItype r0 __asm__ ("0") = n0; \
register SItype r1 __asm__ ("1") = n1; \
\
__asm__ ("dr\t%%r0,%3" \
: "=r" (r0), "=r" (r1) \
: "r" (r0), "r" (r1), "r" (d)); \
(q) = r0; (r) = r1; \
} while (0)
#endif /* __zarch__ */
#endif #endif
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
......
libjava/include/s390-signal.h
...@@ -39,6 +39,7 @@ static void _name (int, siginfo_t *_si __attribute__((unused)), \ ...@@ -39,6 +39,7 @@ static void _name (int, siginfo_t *_si __attribute__((unused)), \
and if dividend and divisor are as above, we simply return from the signal and if dividend and divisor are as above, we simply return from the signal
handler. This causes execution to continue after the instruction. handler. This causes execution to continue after the instruction.
Before returning, we the set result registers as expected. */ Before returning, we the set result registers as expected. */
#define UC_EXTENDED 0x00000001
#define HANDLE_DIVIDE_OVERFLOW \ #define HANDLE_DIVIDE_OVERFLOW \
do \ do \
...@@ -47,6 +48,15 @@ do \ ...@@ -47,6 +48,15 @@ do \
__builtin_extract_return_addr (_si->si_addr); \ __builtin_extract_return_addr (_si->si_addr); \
unsigned long *_regs = _uc->uc_mcontext.gregs; \ unsigned long *_regs = _uc->uc_mcontext.gregs; \
int _r1, _r2, _d2, _x2, _b2; \ int _r1, _r2, _d2, _x2, _b2; \
struct \
{ \
unsigned long int uc_flags; \
struct ucontext *uc_link; \
stack_t uc_stack; \
mcontext_t uc_mcontext; \
unsigned long sigmask[2]; \
unsigned long ext_regs[16]; \
} *_uc_ext = (typeof(_uc_ext))_uc; \
\ \
/* First, a couple of helper routines to decode instructions. */ \ /* First, a couple of helper routines to decode instructions. */ \
struct _decode \ struct _decode \
...@@ -119,8 +129,16 @@ do \ ...@@ -119,8 +129,16 @@ do \
{ \ { \
return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0); \ return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0); \
} \ } \
}; \
\ \
static inline int is_long_long_min_p (unsigned long *_regs, \
unsigned long *_ext_regs, \
int _r) \
{ \
return ((long long)_regs[_r] \
| (long long)_ext_regs[_r] << 32) == \
LONG_LONG_MIN; \
} \
}; \
\ \
/* DR r1,r2 */ \ /* DR r1,r2 */ \
if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2) \ if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2) \
...@@ -175,8 +193,58 @@ do \ ...@@ -175,8 +193,58 @@ do \
_regs[_r1] = 0; \ _regs[_r1] = 0; \
return; \ return; \
} \ } \
\ \
} \ /* The extended ucontext contains the upper halfs of the 64bit \
registers in 31bit applications. */ \
if (_uc->uc_flags & 1 == 1) \
{ \
/* DSGR r1,r2 */ \
if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2) \
&& (int) _regs[_r2] == -1 \
&& (int) _uc_ext->ext_regs[_r2] == -1 \
&& _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
_r1 + 1)) \
{ \
_regs[_r1] = 0; \
_uc_ext->ext_regs[_r1] = 0; \
return; \
} \
\
/* DSGFR r1,r2 */ \
if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2) \
&& (int) _regs[_r2] == -1 \
&& _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
_r1 + 1)) \
{ \
_regs[_r1] = 0; \
_uc_ext->ext_regs[_r1] = 0; \
return; \
} \
\
/* DSG r1,d2(x2,b2) */ \
if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2) \
&& *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1 \
&& *(int *) _decode::_eff (_regs, _d2 + 4, _x2, _b2) == -1 \
&& _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
_r1 + 1)) \
{ \
_regs[_r1] = 0; \
_uc_ext->ext_regs[_r1] = 0; \
return; \
} \
\
/* DSGF r1,d2(x2,b2) */ \
if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2) \
&& *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1 \
&& _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
_r1 + 1)) \
{ \
_regs[_r1] = 0; \
_uc_ext->ext_regs[_r1] = 0; \
return; \
} \
} \
} \
while (0) while (0)
/* For an explanation why we cannot simply use sigaction to /* For an explanation why we cannot simply use sigaction to
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment