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riscv-gcc-1
Commit 946732df by Jakub Jelinek Committed by Jakub Jelinek
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re PR target/91124 (gcc.target/i386/avx512vl-vpshldvd-2.c etc. FAIL) 

	PR target/91124
	* config/i386/sse.md (sse2_cvtpd2dq<mask_name>): Change into ...
	(sse2_cvtpd2dq): ... this.  Remove mask substitution macros.
	(sse2_cvtpd2dq_mask, sse2_cvtpd2dq_mask_1): New define_insns.
	(ufix_notruncv2dfv2si2<mask_name>): Change into ...
	(ufix_notruncv2dfv2si2): ... this.  Remove mask substitution macros.
	(ufix_notruncv2dfv2si2_mask, ufix_notruncv2dfv2si2_mask_1): New
	define_insns.
	(ufix_truncv2dfv2si2<mask_name>): Change into ...
	(ufix_truncv2dfv2si2): ... this.  Remove mask substitution macros.
	(ufix_truncv2dfv2si2_mask, ufix_truncv2dfv2si2_mask_1): New
	define_insns.
	(sse2_cvttpd2dq<mask_name>): Change into ...
	(sse2_cvttpd2dq): ... this.  Remove mask substitution macros.
	(sse2_cvttpd2dq_mask, sse2_cvttpd2dq_mask_1): New define_insns.
	(*sse2_cvtpd2dq<mask_name>): Change into ...
	(*sse2_cvtpd2dq): ... this.  Remove mask substitution macros.
	Add "C" constraint to const0_operand.
	(*sse2_cvtpd2dq_mask, *sse2_cvtpd2dq_mask_1): New define_insns.
	(sse2_cvtpd2ps_mask): Adjust expand to match *sse2_cvtpd2ps_mask
	changes.

From-SVN: r273409
parent 491b0b40
Showing with 202 additions and 20 deletions
gcc/ChangeLog
2019-07-11 Jakub Jelinek <jakub@redhat.com> 2019-07-11 Jakub Jelinek <jakub@redhat.com>
PR target/91124 PR target/91124
* config/i386/sse.md (sse2_cvtpd2dq<mask_name>): Change into ...
(sse2_cvtpd2dq): ... this. Remove mask substitution macros.
(sse2_cvtpd2dq_mask, sse2_cvtpd2dq_mask_1): New define_insns.
(ufix_notruncv2dfv2si2<mask_name>): Change into ...
(ufix_notruncv2dfv2si2): ... this. Remove mask substitution macros.
(ufix_notruncv2dfv2si2_mask, ufix_notruncv2dfv2si2_mask_1): New
define_insns.
(ufix_truncv2dfv2si2<mask_name>): Change into ...
(ufix_truncv2dfv2si2): ... this. Remove mask substitution macros.
(ufix_truncv2dfv2si2_mask, ufix_truncv2dfv2si2_mask_1): New
define_insns.
(sse2_cvttpd2dq<mask_name>): Change into ...
(sse2_cvttpd2dq): ... this. Remove mask substitution macros.
(sse2_cvttpd2dq_mask, sse2_cvttpd2dq_mask_1): New define_insns.
(*sse2_cvtpd2dq<mask_name>): Change into ...
(*sse2_cvtpd2dq): ... this. Remove mask substitution macros.
Add "C" constraint to const0_operand.
(*sse2_cvtpd2dq_mask, *sse2_cvtpd2dq_mask_1): New define_insns.
(sse2_cvtpd2ps_mask): Adjust expand to match *sse2_cvtpd2ps_mask
changes.
PR target/91124
* config/i386/i386-builtin-types.def * config/i386/i386-builtin-types.def
(V32HI_FTYPE_V32HI_V32HI_V32HI_INT, (V32HI_FTYPE_V32HI_V32HI_V32HI_INT,
V16HI_FTYPE_V16HI_V16HI_V16HI_INT, V8HI_FTYPE_V8HI_V8HI_V8HI_INT, V16HI_FTYPE_V16HI_V16HI_V16HI_INT, V8HI_FTYPE_V8HI_V8HI_V8HI_INT,
......
gcc/config/i386/sse.md
...@@ -5927,16 +5927,16 @@ ...@@ -5927,16 +5927,16 @@
(set_attr "btver2_decode" "vector") (set_attr "btver2_decode" "vector")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "sse2_cvtpd2dq<mask_name>" (define_insn "sse2_cvtpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI (vec_concat:V4SI
(unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm")] (unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm")]
UNSPEC_FIX_NOTRUNC) UNSPEC_FIX_NOTRUNC)
(const_vector:V2SI [(const_int 0) (const_int 0)])))] (const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2 && <mask_avx512vl_condition>" "TARGET_SSE2"
{ {
if (TARGET_AVX) if (TARGET_AVX)
return "vcvtpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"; return "vcvtpd2dq{x}\t{%1, %0|%0, %1}";
else else
return "cvtpd2dq\t{%1, %0|%0, %1}"; return "cvtpd2dq\t{%1, %0|%0, %1}";
} }
...@@ -5949,6 +5949,38 @@ ...@@ -5949,6 +5949,38 @@
(set_attr "athlon_decode" "vector") (set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")]) (set_attr "bdver1_decode" "double")])
(define_insn "sse2_cvtpd2dq_mask"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
UNSPEC_FIX_NOTRUNC)
(vec_select:V2SI
(match_operand:V4SI 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:QI 3 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvtpd2dq{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "*sse2_cvtpd2dq_mask_1"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
UNSPEC_FIX_NOTRUNC)
(const_vector:V2SI [(const_int 0) (const_int 0)])
(match_operand:QI 2 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvtpd2dq{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
;; For ufix_notrunc* insn patterns ;; For ufix_notrunc* insn patterns
(define_mode_attr pd2udqsuff (define_mode_attr pd2udqsuff
[(V8DF "") (V4DF "{y}")]) [(V8DF "") (V4DF "{y}")])
...@@ -5964,15 +5996,49 @@ ...@@ -5964,15 +5996,49 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_insn "ufix_notruncv2dfv2si2<mask_name>" (define_insn "ufix_notruncv2dfv2si2"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI (vec_concat:V4SI
(unspec:V2SI (unspec:V2SI
[(match_operand:V2DF 1 "nonimmediate_operand" "vm")] [(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
UNSPEC_UNSIGNED_FIX_NOTRUNC) UNSPEC_UNSIGNED_FIX_NOTRUNC)
(const_vector:V2SI [(const_int 0) (const_int 0)])))] (const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL" "TARGET_AVX512VL"
"vcvtpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" "vcvtpd2udq{x}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "ufix_notruncv2dfv2si2_mask"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(unspec:V2SI
[(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
UNSPEC_UNSIGNED_FIX_NOTRUNC)
(vec_select:V2SI
(match_operand:V4SI 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:QI 3 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvtpd2udq{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "*ufix_notruncv2dfv2si2_mask_1"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(unspec:V2SI
[(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
UNSPEC_UNSIGNED_FIX_NOTRUNC)
(const_vector:V2SI [(const_int 0) (const_int 0)])
(match_operand:QI 2 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvtpd2udq{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
...@@ -5987,13 +6053,43 @@ ...@@ -5987,13 +6053,43 @@
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "ufix_truncv2dfv2si2<mask_name>" (define_insn "ufix_truncv2dfv2si2"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI (vec_concat:V4SI
(unsigned_fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm")) (unsigned_fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))] (const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL" "TARGET_AVX512VL"
"vcvttpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" "vcvttpd2udq{x}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "ufix_truncv2dfv2si2_mask"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(unsigned_fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(vec_select:V2SI
(match_operand:V4SI 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:QI 3 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvttpd2udq{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "*ufix_truncv2dfv2si2_mask_1"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(unsigned_fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(const_vector:V2SI [(const_int 0) (const_int 0)])
(match_operand:QI 2 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvttpd2udq{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "prefix" "evex") (set_attr "prefix" "evex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
...@@ -6138,15 +6234,15 @@ ...@@ -6138,15 +6234,15 @@
"TARGET_AVX" "TARGET_AVX"
"operands[2] = CONST0_RTX (V4SImode);") "operands[2] = CONST0_RTX (V4SImode);")
(define_insn "sse2_cvttpd2dq<mask_name>" (define_insn "sse2_cvttpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI (vec_concat:V4SI
(fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm")) (fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))] (const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2 && <mask_avx512vl_condition>" "TARGET_SSE2"
{ {
if (TARGET_AVX) if (TARGET_AVX)
return "vcvttpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"; return "vcvttpd2dq{x}\t{%1, %0|%0, %1}";
else else
return "cvttpd2dq\t{%1, %0|%0, %1}"; return "cvttpd2dq\t{%1, %0|%0, %1}";
} }
...@@ -6157,6 +6253,36 @@ ...@@ -6157,6 +6253,36 @@
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "sse2_cvttpd2dq_mask"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(vec_select:V2SI
(match_operand:V4SI 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:QI 3 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvttpd2dq{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "*sse2_cvttpd2dq_mask_1"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(vec_merge:V2SI
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(const_vector:V2SI [(const_int 0) (const_int 0)])
(match_operand:QI 2 "register_operand" "Yk"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_AVX512VL"
"vcvttpd2dq{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
(define_insn "sse2_cvtsd2ss<round_name>" (define_insn "sse2_cvtsd2ss<round_name>"
[(set (match_operand:V4SF 0 "register_operand" "=x,x,v") [(set (match_operand:V4SF 0 "register_operand" "=x,x,v")
(vec_merge:V4SF (vec_merge:V4SF
...@@ -6276,26 +6402,28 @@ ...@@ -6276,26 +6402,28 @@
(define_expand "sse2_cvtpd2ps_mask" (define_expand "sse2_cvtpd2ps_mask"
[(set (match_operand:V4SF 0 "register_operand") [(set (match_operand:V4SF 0 "register_operand")
(vec_merge:V4SF (vec_concat:V4SF
(vec_concat:V4SF (vec_merge:V2SF
(float_truncate:V2SF (float_truncate:V2SF
(match_operand:V2DF 1 "vector_operand")) (match_operand:V2DF 1 "vector_operand"))
(match_dup 4)) (vec_select:V2SF
(match_operand:V4SF 2 "register_operand") (match_operand:V4SF 2 "nonimm_or_0_operand")
(match_operand:QI 3 "register_operand")))] (parallel [(const_int 0) (const_int 1)]))
(match_operand:QI 3 "register_operand"))
(match_dup 4)))]
"TARGET_SSE2" "TARGET_SSE2"
"operands[4] = CONST0_RTX (V2SFmode);") "operands[4] = CONST0_RTX (V2SFmode);")
(define_insn "*sse2_cvtpd2ps<mask_name>" (define_insn "*sse2_cvtpd2ps"
[(set (match_operand:V4SF 0 "register_operand" "=v") [(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_concat:V4SF (vec_concat:V4SF
(float_truncate:V2SF (float_truncate:V2SF
(match_operand:V2DF 1 "vector_operand" "vBm")) (match_operand:V2DF 1 "vector_operand" "vBm"))
(match_operand:V2SF 2 "const0_operand")))] (match_operand:V2SF 2 "const0_operand" "C")))]
"TARGET_SSE2 && <mask_avx512vl_condition>" "TARGET_SSE2"
{ {
if (TARGET_AVX) if (TARGET_AVX)
return "vcvtpd2ps{x}\t{%1, %0<mask_operand3>|%0<mask_operand3>, %1}"; return "vcvtpd2ps{x}\t{%1, %0|%0, %1}";
else else
return "cvtpd2ps\t{%1, %0|%0, %1}"; return "cvtpd2ps\t{%1, %0|%0, %1}";
} }
...@@ -6307,6 +6435,38 @@ ...@@ -6307,6 +6435,38 @@
(set_attr "prefix" "maybe_vex") (set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
(define_insn "*sse2_cvtpd2ps_mask"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_concat:V4SF
(vec_merge:V2SF
(float_truncate:V2SF
(match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(vec_select:V2SF
(match_operand:V4SF 2 "nonimm_or_0_operand" "0C")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:QI 3 "register_operand" "Yk"))
(match_operand:V2SF 4 "const0_operand" "C")))]
"TARGET_AVX512VL"
"vcvtpd2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "V4SF")])
(define_insn "*sse2_cvtpd2ps_mask_1"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_concat:V4SF
(vec_merge:V2SF
(float_truncate:V2SF
(match_operand:V2DF 1 "nonimmediate_operand" "vm"))
(match_operand:V2SF 3 "const0_operand" "C")
(match_operand:QI 2 "register_operand" "Yk"))
(match_operand:V2SF 4 "const0_operand" "C")))]
"TARGET_AVX512VL"
"vcvtpd2ps{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "V4SF")])
;; For <sse2_avx_avx512f>_cvtps2pd<avxsizesuffix> insn pattern ;; For <sse2_avx_avx512f>_cvtps2pd<avxsizesuffix> insn pattern
(define_mode_attr sf2dfmode (define_mode_attr sf2dfmode
[(V8DF "V8SF") (V4DF "V4SF")]) [(V8DF "V8SF") (V4DF "V4SF")])
......
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