Commit 9024f4b8 by Alan Modra Committed by Alan Modra

re PR target/25212 (unrecognizable insn for facerec with odd optimization set)

	PR target/25212
	* config/rs6000/rs6000.c (legitimate_indexed_address_p): Relax
	tests further when !strict && reload_in_progress.
	(print_operand): Check that both operands of indexed address are regs.
	(print_operand_address): Likewise.
	* config/rs6000/rs6000.h (INT_REG_OK_FOR_INDEX_P): Simplify.
	(INT_REG_OK_FOR_BASE_P): Correct.

From-SVN: r108167
parent 8a39029d
2005-12-08 Alan Modra <amodra@bigpond.net.au>
PR target/25212
* config/rs6000/rs6000.c (legitimate_indexed_address_p): Relax
tests further when !strict && reload_in_progress.
(print_operand): Check that both operands of indexed address are regs.
(print_operand_address): Likewise.
* config/rs6000/rs6000.h (INT_REG_OK_FOR_INDEX_P): Simplify.
(INT_REG_OK_FOR_BASE_P): Correct.
2005-12-07 J"orn Rennecke <joern.rennecke@st.com>
Preparation for PR rtl-optimization/20070 / part1
......
......@@ -2735,23 +2735,19 @@ legitimate_indexed_address_p (rtx x, int strict)
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
if (REG_P (op0) && REG_P (op1))
return ((INT_REG_OK_FOR_BASE_P (op0, strict)
&& INT_REG_OK_FOR_INDEX_P (op1, strict))
|| (INT_REG_OK_FOR_BASE_P (op1, strict)
&& INT_REG_OK_FOR_INDEX_P (op0, strict)));
/* Recognize the rtl generated by reload which we know will later be
replaced by a base reg. We rely on nothing but reload generating
this particular pattern, a reasonable assumption because it is not
canonical. */
else if (reload_in_progress
&& GET_CODE (op0) == PLUS
&& REG_P (XEXP (op0, 0))
&& GET_CODE (XEXP (op0, 1)) == CONST_INT
&& REG_P (op1))
return INT_REG_OK_FOR_INDEX_P (op1, strict);
return false;
replaced with proper base and index regs. */
if (!strict
&& reload_in_progress
&& (REG_P (op0) || GET_CODE (op0) == PLUS)
&& REG_P (op1))
return true;
return (REG_P (op0) && REG_P (op1)
&& ((INT_REG_OK_FOR_BASE_P (op0, strict)
&& INT_REG_OK_FOR_INDEX_P (op1, strict))
|| (INT_REG_OK_FOR_BASE_P (op1, strict)
&& INT_REG_OK_FOR_INDEX_P (op0, strict))));
}
inline bool
......@@ -10676,7 +10672,8 @@ print_operand (FILE *file, rtx x, int code)
else
{
gcc_assert (GET_CODE (tmp) == PLUS
&& GET_CODE (XEXP (tmp, 1)) == REG);
&& REG_P (XEXP (tmp, 0))
&& REG_P (XEXP (tmp, 1)));
if (REGNO (XEXP (tmp, 0)) == 0)
fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
......@@ -10736,6 +10733,7 @@ print_operand_address (FILE *file, rtx x)
}
else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
{
gcc_assert (REG_P (XEXP (x, 0)));
if (REGNO (XEXP (x, 0)) == 0)
fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
reg_names[ REGNO (XEXP (x, 0)) ]);
......
......@@ -1723,17 +1723,14 @@ typedef struct rs6000_args
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg in the non-strict case. */
#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
((! (STRICT) \
&& (REGNO (X) <= 31 \
|| REGNO (X) == ARG_POINTER_REGNUM \
|| REGNO (X) == FRAME_POINTER_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
|| ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| REGNO_OK_FOR_INDEX_P (REGNO (X)))
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg in the non-strict case. */
#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
(REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| REGNO_OK_FOR_BASE_P (REGNO (X)))
#define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
#define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
......
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