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riscv-gcc-1
Commit 8fe75e43 by Richard Henderson Committed by Richard Henderson
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i386.c (internal_label_prefix): Export. 

	* config/i386/i386.c (internal_label_prefix): Export.
	(internal_label_prefix_len, struct ix86_address,
	ix86_decompose_address, maybe_get_pool_constant,
	ix86_fp_compare_code_to_integer, ix86_fp_comparison_codes,
	memory_address_length): Export.
	(any_fp_register_operand, fp_register_operand,
	register_and_not_any_fp_reg_operand, register_and_not_fp_reg_operand,
	x86_64_general_operand, x86_64_szext_general_operand,
	x86_64_nonmemory_operand, x86_64_movabs_operand,
	x86_64_szext_nonmemory_operand, x86_64_immediate_operand,
	x86_64_zext_immediate_operand, const_int_1_31_operand,
	symbolic_operand, pic_symbolic_operand, local_symbolic_operand,
	tls_symbolic_operand, global_dynamic_symbolic_operand,
	local_dynamic_symbolic_operand, initial_exec_symbolic_operand,
	local_exec_symbolic_operand, call_insn_operand, sibcall_insn_operand,
	constant_call_address_operand, const0_operand, const1_operand,
	const248_operand, const_0_to_3_operand, const_0_to_7_operand,
	const_0_to_15_operand, const_0_to_255_operand, incdec_operand,
	shiftdi_operand, reg_no_sp_operand, mmx_reg_operand,
	general_no_elim_operand, nonmemory_no_elim_operand,
	index_register_operand, q_regs_operand, flags_reg_operand,
	non_q_regs_operand, zero_extended_scalar_load_operand,
	vector_move_operand, no_seg_address_operand, sse_comparison_operator,
	ix86_comparison_operator, ix86_carry_flag_operator,
	fcmov_comparison_operator, promotable_binary_operator,
	cmp_fp_expander_operand, ext_register_operand, binary_fp_operator,
	mult_operator, div_operator, arith_or_logical_operator,
	memory_displacement_operand, cmpsi_operand, long_memory_operand,
	aligned_operand): Move to predicates.md as define_predicates.
	(tls_symbolic_operand_1): Remove.
	(x86_64_sign_extended_value): Merge into x86_64_immediate_operand.
	(x86_64_zero_extended_value): Merge into x86_64_zext_immediate_operand.
	(legitimize_address): Merge tls_symbolic_operand contents.
	(ix86_expand_move): Likewise.
	* config/i386/i386-protos.h: Update for exports.
	* config/i386/i386.h (EXTRA_CONSTRAINT): Update for renames.
	(PREDICATE_CODES, SPECIAL_MODE_PREDICATES): Remove.
	* config/i386/i386.md: Include predicates.md.
	* config/i386/predicates.md: New file.

From-SVN: r85930
parent 1a6213c3
Showing with 986 additions and 1301 deletions
gcc/ChangeLog
2004-08-12 Richard Henderson <rth@redhat.com>
* config/i386/i386.c (internal_label_prefix): Export.
(internal_label_prefix_len, struct ix86_address,
ix86_decompose_address, maybe_get_pool_constant,
ix86_fp_compare_code_to_integer, ix86_fp_comparison_codes,
memory_address_length): Export.
(any_fp_register_operand, fp_register_operand,
register_and_not_any_fp_reg_operand, register_and_not_fp_reg_operand,
x86_64_general_operand, x86_64_szext_general_operand,
x86_64_nonmemory_operand, x86_64_movabs_operand,
x86_64_szext_nonmemory_operand, x86_64_immediate_operand,
x86_64_zext_immediate_operand, const_int_1_31_operand,
symbolic_operand, pic_symbolic_operand, local_symbolic_operand,
tls_symbolic_operand, global_dynamic_symbolic_operand,
local_dynamic_symbolic_operand, initial_exec_symbolic_operand,
local_exec_symbolic_operand, call_insn_operand, sibcall_insn_operand,
constant_call_address_operand, const0_operand, const1_operand,
const248_operand, const_0_to_3_operand, const_0_to_7_operand,
const_0_to_15_operand, const_0_to_255_operand, incdec_operand,
shiftdi_operand, reg_no_sp_operand, mmx_reg_operand,
general_no_elim_operand, nonmemory_no_elim_operand,
index_register_operand, q_regs_operand, flags_reg_operand,
non_q_regs_operand, zero_extended_scalar_load_operand,
vector_move_operand, no_seg_address_operand, sse_comparison_operator,
ix86_comparison_operator, ix86_carry_flag_operator,
fcmov_comparison_operator, promotable_binary_operator,
cmp_fp_expander_operand, ext_register_operand, binary_fp_operator,
mult_operator, div_operator, arith_or_logical_operator,
memory_displacement_operand, cmpsi_operand, long_memory_operand,
aligned_operand): Move to predicates.md as define_predicates.
(tls_symbolic_operand_1): Remove.
(x86_64_sign_extended_value): Merge into x86_64_immediate_operand.
(x86_64_zero_extended_value): Merge into x86_64_zext_immediate_operand.
(legitimize_address): Merge tls_symbolic_operand contents.
(ix86_expand_move): Likewise.
* config/i386/i386-protos.h: Update for exports.
* config/i386/i386.h (EXTRA_CONSTRAINT): Update for renames.
(PREDICATE_CODES, SPECIAL_MODE_PREDICATES): Remove.
* config/i386/i386.md: Include predicates.md.
* config/i386/predicates.md: New file.
2004-08-13 Mark Mitchell <mark@codesourcery.com> 2004-08-13 Mark Mitchell <mark@codesourcery.com>
PR c++/16924 PR c++/16924
......
gcc/config/i386/i386-protos.h
...@@ -156,8 +156,6 @@ extern int ix86_attr_length_address_default (rtx); ...@@ -156,8 +156,6 @@ extern int ix86_attr_length_address_default (rtx);
extern enum machine_mode ix86_fp_compare_mode (enum rtx_code); extern enum machine_mode ix86_fp_compare_mode (enum rtx_code);
extern int x86_64_sign_extended_value (rtx);
extern int x86_64_zero_extended_value (rtx);
extern rtx ix86_libcall_value (enum machine_mode); extern rtx ix86_libcall_value (enum machine_mode);
extern bool ix86_function_value_regno_p (int); extern bool ix86_function_value_regno_p (int);
extern bool ix86_function_arg_regno_p (int); extern bool ix86_function_arg_regno_p (int);
...@@ -227,3 +225,24 @@ extern void i386_pe_encode_section_info (tree, rtx, int); ...@@ -227,3 +225,24 @@ extern void i386_pe_encode_section_info (tree, rtx, int);
extern const char *i386_pe_strip_name_encoding (const char *); extern const char *i386_pe_strip_name_encoding (const char *);
extern const char *i386_pe_strip_name_encoding_full (const char *); extern const char *i386_pe_strip_name_encoding_full (const char *);
extern void i386_pe_output_labelref (FILE *, const char *); extern void i386_pe_output_labelref (FILE *, const char *);
extern rtx maybe_get_pool_constant (rtx);
extern char internal_label_prefix[16];
extern int internal_label_prefix_len;
enum ix86_address_seg { SEG_DEFAULT, SEG_FS, SEG_GS };
struct ix86_address
{
rtx base, index, disp;
HOST_WIDE_INT scale;
enum ix86_address_seg seg;
};
extern int ix86_decompose_address (rtx, struct ix86_address *);
extern int memory_address_length (rtx addr);
#ifdef RTX_CODE
extern void ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *,
enum rtx_code *, enum rtx_code *);
extern enum rtx_code ix86_fp_compare_code_to_integer (enum rtx_code);
#endif
gcc/config/i386/i386.c
...@@ -829,17 +829,14 @@ const char *ix86_branch_cost_string; ...@@ -829,17 +829,14 @@ const char *ix86_branch_cost_string;
const char *ix86_align_funcs_string; const char *ix86_align_funcs_string;
/* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */ /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
static char internal_label_prefix[16]; char internal_label_prefix[16];
static int internal_label_prefix_len; int internal_label_prefix_len;
static int local_symbolic_operand (rtx, enum machine_mode);
static int tls_symbolic_operand_1 (rtx, enum tls_model);
static void output_pic_addr_const (FILE *, rtx, int); static void output_pic_addr_const (FILE *, rtx, int);
static void put_condition_code (enum rtx_code, enum machine_mode, static void put_condition_code (enum rtx_code, enum machine_mode,
int, int, FILE *); int, int, FILE *);
static const char *get_some_local_dynamic_name (void); static const char *get_some_local_dynamic_name (void);
static int get_some_local_dynamic_name_1 (rtx *, void *); static int get_some_local_dynamic_name_1 (rtx *, void *);
static rtx maybe_get_pool_constant (rtx);
static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx); static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *, static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
rtx *); rtx *);
...@@ -850,7 +847,6 @@ static rtx get_thread_pointer (int); ...@@ -850,7 +847,6 @@ static rtx get_thread_pointer (int);
static rtx legitimize_tls_address (rtx, enum tls_model, int); static rtx legitimize_tls_address (rtx, enum tls_model, int);
static void get_pc_thunk_name (char [32], unsigned int); static void get_pc_thunk_name (char [32], unsigned int);
static rtx gen_push (rtx); static rtx gen_push (rtx);
static int memory_address_length (rtx addr);
static int ix86_flags_dependant (rtx, rtx, enum attr_type); static int ix86_flags_dependant (rtx, rtx, enum attr_type);
static int ix86_agi_dependant (rtx, rtx, enum attr_type); static int ix86_agi_dependant (rtx, rtx, enum attr_type);
static struct machine_function * ix86_init_machine_status (void); static struct machine_function * ix86_init_machine_status (void);
...@@ -880,14 +876,6 @@ static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, ...@@ -880,14 +876,6 @@ static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
tree, int *, int); tree, int *, int);
static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *); static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
struct ix86_address
{
rtx base, index, disp;
HOST_WIDE_INT scale;
enum ix86_address_seg { SEG_DEFAULT, SEG_FS, SEG_GS } seg;
};
static int ix86_decompose_address (rtx, struct ix86_address *);
static int ix86_address_cost (rtx); static int ix86_address_cost (rtx);
static bool ix86_cannot_force_const_mem (rtx); static bool ix86_cannot_force_const_mem (rtx);
static rtx ix86_delegitimize_address (rtx); static rtx ix86_delegitimize_address (rtx);
...@@ -902,9 +890,6 @@ static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int); ...@@ -902,9 +890,6 @@ static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx); static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
static rtx ix86_expand_store_builtin (enum insn_code, tree); static rtx ix86_expand_store_builtin (enum insn_code, tree);
static rtx safe_vector_operand (rtx, enum machine_mode); static rtx safe_vector_operand (rtx, enum machine_mode);
static enum rtx_code ix86_fp_compare_code_to_integer (enum rtx_code);
static void ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *,
enum rtx_code *, enum rtx_code *);
static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *); static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code); static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
static int ix86_fp_comparison_fcomi_cost (enum rtx_code code); static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
...@@ -3447,1010 +3432,93 @@ ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) ...@@ -3447,1010 +3432,93 @@ ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
size_int (src_offset))); size_int (src_offset)));
src = build_fold_indirect_ref (src_addr); src = build_fold_indirect_ref (src_addr);
dest_addr = fold_convert (addr_type, addr); dest_addr = fold_convert (addr_type, addr);
dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr, dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
size_int (INTVAL (XEXP (slot, 1))))); size_int (INTVAL (XEXP (slot, 1)))));
dest = build_fold_indirect_ref (dest_addr); dest = build_fold_indirect_ref (dest_addr);
t = build2 (MODIFY_EXPR, void_type_node, dest, src);
gimplify_and_add (t, pre_p);
}
}
if (needed_intregs)
{
t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
build_int_2 (needed_intregs * 8, 0));
t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
gimplify_and_add (t, pre_p);
}
if (needed_sseregs)
{
t =
build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
build_int_2 (needed_sseregs * 16, 0));
t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
gimplify_and_add (t, pre_p);
}
t = build1 (GOTO_EXPR, void_type_node, lab_over);
gimplify_and_add (t, pre_p);
t = build1 (LABEL_EXPR, void_type_node, lab_false);
append_to_statement_list (t, pre_p);
}
/* ... otherwise out of the overflow area. */
/* Care for on-stack alignment if needed. */
if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64)
t = ovf;
else
{
HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align - 1, 0));
t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
}
gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
gimplify_and_add (t2, pre_p);
t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
build_int_2 (rsize * UNITS_PER_WORD, 0));
t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
gimplify_and_add (t, pre_p);
if (container)
{
t = build1 (LABEL_EXPR, void_type_node, lab_over);
append_to_statement_list (t, pre_p);
}
ptrtype = build_pointer_type (type);
addr = fold_convert (ptrtype, addr);
if (indirect_p)
addr = build_fold_indirect_ref (addr);
return build_fold_indirect_ref (addr);
}
/* Return nonzero if OP is either a i387 or SSE fp register. */
int
any_fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return ANY_FP_REG_P (op);
}
/* Return nonzero if OP is an i387 fp register. */
int
fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return FP_REG_P (op);
}
/* Return nonzero if OP is a non-fp register_operand. */
int
register_and_not_any_fp_reg_operand (rtx op, enum machine_mode mode)
{
return register_operand (op, mode) && !ANY_FP_REG_P (op);
}
/* Return nonzero if OP is a register operand other than an
i387 fp register. */
int
register_and_not_fp_reg_operand (rtx op, enum machine_mode mode)
{
return register_operand (op, mode) && !FP_REG_P (op);
}
/* Return nonzero if OP is general operand representable on x86_64. */
int
x86_64_general_operand (rtx op, enum machine_mode mode)
{
if (!TARGET_64BIT)
return general_operand (op, mode);
if (nonimmediate_operand (op, mode))
return 1;
return x86_64_sign_extended_value (op);
}
/* Return nonzero if OP is general operand representable on x86_64
as either sign extended or zero extended constant. */
int
x86_64_szext_general_operand (rtx op, enum machine_mode mode)
{
if (!TARGET_64BIT)
return general_operand (op, mode);
if (nonimmediate_operand (op, mode))
return 1;
return x86_64_sign_extended_value (op) || x86_64_zero_extended_value (op);
}
/* Return nonzero if OP is nonmemory operand representable on x86_64. */
int
x86_64_nonmemory_operand (rtx op, enum machine_mode mode)
{
if (!TARGET_64BIT)
return nonmemory_operand (op, mode);
if (register_operand (op, mode))
return 1;
return x86_64_sign_extended_value (op);
}
/* Return nonzero if OP is nonmemory operand acceptable by movabs patterns. */
int
x86_64_movabs_operand (rtx op, enum machine_mode mode)
{
if (!TARGET_64BIT || !flag_pic)
return nonmemory_operand (op, mode);
if (register_operand (op, mode) || x86_64_sign_extended_value (op))
return 1;
if (CONSTANT_P (op) && !symbolic_reference_mentioned_p (op))
return 1;
return 0;
}
/* Return nonzero if OPNUM's MEM should be matched
in movabs* patterns. */
int
ix86_check_movabs (rtx insn, int opnum)
{
rtx set, mem;
set = PATTERN (insn);
if (GET_CODE (set) == PARALLEL)
set = XVECEXP (set, 0, 0);
if (GET_CODE (set) != SET)
abort ();
mem = XEXP (set, opnum);
while (GET_CODE (mem) == SUBREG)
mem = SUBREG_REG (mem);
if (GET_CODE (mem) != MEM)
abort ();
return (volatile_ok || !MEM_VOLATILE_P (mem));
}
/* Return nonzero if OP is nonmemory operand representable on x86_64. */
int
x86_64_szext_nonmemory_operand (rtx op, enum machine_mode mode)
{
if (!TARGET_64BIT)
return nonmemory_operand (op, mode);
if (register_operand (op, mode))
return 1;
return x86_64_sign_extended_value (op) || x86_64_zero_extended_value (op);
}
/* Return nonzero if OP is immediate operand representable on x86_64. */
int
x86_64_immediate_operand (rtx op, enum machine_mode mode)
{
if (!TARGET_64BIT)
return immediate_operand (op, mode);
return x86_64_sign_extended_value (op);
}
/* Return nonzero if OP is immediate operand representable on x86_64. */
int
x86_64_zext_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return x86_64_zero_extended_value (op);
}
/* Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand
for shift & compare patterns, as shifting by 0 does not change flags),
else return zero. */
int
const_int_1_31_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 1 && INTVAL (op) <= 31);
}
/* Returns 1 if OP is either a symbol reference or a sum of a symbol
reference and a constant. */
int
symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
switch (GET_CODE (op))
{
case SYMBOL_REF:
case LABEL_REF:
return 1;
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF
|| (GET_CODE (op) == UNSPEC
&& (XINT (op, 1) == UNSPEC_GOT
|| XINT (op, 1) == UNSPEC_GOTOFF
|| XINT (op, 1) == UNSPEC_GOTPCREL)))
return 1;
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 1)) != CONST_INT)
return 0;
op = XEXP (op, 0);
if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF)
return 1;
/* Only @GOTOFF gets offsets. */
if (GET_CODE (op) != UNSPEC
|| XINT (op, 1) != UNSPEC_GOTOFF)
return 0;
op = XVECEXP (op, 0, 0);
if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF)
return 1;
return 0;
default:
return 0;
}
}
/* Return true if the operand contains a @GOT or @GOTOFF reference. */
int
pic_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (GET_CODE (op) != CONST)
return 0;
op = XEXP (op, 0);
if (TARGET_64BIT)
{
if (GET_CODE (op) == UNSPEC
&& XINT (op, 1) == UNSPEC_GOTPCREL)
return 1;
if (GET_CODE (op) == PLUS
&& GET_CODE (XEXP (op, 0)) == UNSPEC
&& XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL)
return 1;
}
else
{
if (GET_CODE (op) == UNSPEC)
return 1;
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 1)) != CONST_INT)
return 0;
op = XEXP (op, 0);
if (GET_CODE (op) == UNSPEC)
return 1;
}
return 0;
}
/* Return true if OP is a symbolic operand that resolves locally. */
static int
local_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
op = XEXP (XEXP (op, 0), 0);
if (GET_CODE (op) == LABEL_REF)
return 1;
if (GET_CODE (op) != SYMBOL_REF)
return 0;
if (SYMBOL_REF_LOCAL_P (op))
return 1;
/* There is, however, a not insubstantial body of code in the rest of
the compiler that assumes it can just stick the results of
ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
/* ??? This is a hack. Should update the body of the compiler to
always create a DECL an invoke targetm.encode_section_info. */
if (strncmp (XSTR (op, 0), internal_label_prefix,
internal_label_prefix_len) == 0)
return 1;
return 0;
}
/* Test for various thread-local symbols. */
int
tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (GET_CODE (op) != SYMBOL_REF)
return 0;
return SYMBOL_REF_TLS_MODEL (op);
}
static inline int
tls_symbolic_operand_1 (rtx op, enum tls_model kind)
{
if (GET_CODE (op) != SYMBOL_REF)
return 0;
return SYMBOL_REF_TLS_MODEL (op) == kind;
}
int
global_dynamic_symbolic_operand (rtx op,
enum machine_mode mode ATTRIBUTE_UNUSED)
{
return tls_symbolic_operand_1 (op, TLS_MODEL_GLOBAL_DYNAMIC);
}
int
local_dynamic_symbolic_operand (rtx op,
enum machine_mode mode ATTRIBUTE_UNUSED)
{
return tls_symbolic_operand_1 (op, TLS_MODEL_LOCAL_DYNAMIC);
}
int
initial_exec_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return tls_symbolic_operand_1 (op, TLS_MODEL_INITIAL_EXEC);
}
int
local_exec_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return tls_symbolic_operand_1 (op, TLS_MODEL_LOCAL_EXEC);
}
/* Test for a valid operand for a call instruction. Don't allow the
arg pointer register or virtual regs since they may decay into
reg + const, which the patterns can't handle. */
int
call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
/* Disallow indirect through a virtual register. This leads to
compiler aborts when trying to eliminate them. */
if (GET_CODE (op) == REG
&& (op == arg_pointer_rtx
|| op == frame_pointer_rtx
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& REGNO (op) <= LAST_VIRTUAL_REGISTER)))
return 0;
/* Disallow `call 1234'. Due to varying assembler lameness this
gets either rejected or translated to `call .+1234'. */
if (GET_CODE (op) == CONST_INT)
return 0;
/* Explicitly allow SYMBOL_REF even if pic. */
if (GET_CODE (op) == SYMBOL_REF)
return 1;
/* Otherwise we can allow any general_operand in the address. */
return general_operand (op, Pmode);
}
/* Test for a valid operand for a call instruction. Don't allow the
arg pointer register or virtual regs since they may decay into
reg + const, which the patterns can't handle. */
int
sibcall_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
/* Disallow indirect through a virtual register. This leads to
compiler aborts when trying to eliminate them. */
if (GET_CODE (op) == REG
&& (op == arg_pointer_rtx
|| op == frame_pointer_rtx
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& REGNO (op) <= LAST_VIRTUAL_REGISTER)))
return 0;
/* Explicitly allow SYMBOL_REF even if pic. */
if (GET_CODE (op) == SYMBOL_REF)
return 1;
/* Otherwise we can only allow register operands. */
return register_operand (op, Pmode);
}
int
constant_call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
op = XEXP (XEXP (op, 0), 0);
return GET_CODE (op) == SYMBOL_REF;
}
/* Match exactly zero and one. */
int
const0_operand (rtx op, enum machine_mode mode)
{
return op == CONST0_RTX (mode);
}
int
const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return op == const1_rtx;
}
/* Match 2, 4, or 8. Used for leal multiplicands. */
int
const248_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return (GET_CODE (op) == CONST_INT
&& (INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8));
}
int
const_0_to_3_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 4);
}
int
const_0_to_7_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 8);
}
int
const_0_to_15_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 16);
}
int
const_0_to_255_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 256);
}
/* True if this is a constant appropriate for an increment or decrement. */
int
incdec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
/* On Pentium4, the inc and dec operations causes extra dependency on flag
registers, since carry flag is not set. */
if ((TARGET_PENTIUM4 || TARGET_NOCONA) && !optimize_size)
return 0;
return op == const1_rtx || op == constm1_rtx;
}
/* Return nonzero if OP is acceptable as operand of DImode shift
expander. */
int
shiftdi_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (TARGET_64BIT)
return nonimmediate_operand (op, mode);
else
return register_operand (op, mode);
}
/* Return false if this is the stack pointer, or any other fake
register eliminable to the stack pointer. Otherwise, this is
a register operand.
This is used to prevent esp from being used as an index reg.
Which would only happen in pathological cases. */
int
reg_no_sp_operand (rtx op, enum machine_mode mode)
{
rtx t = op;
if (GET_CODE (t) == SUBREG)
t = SUBREG_REG (t);
if (t == stack_pointer_rtx || t == arg_pointer_rtx || t == frame_pointer_rtx)
return 0;
return register_operand (op, mode);
}
int
mmx_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return MMX_REG_P (op);
}
/* Return false if this is any eliminable register. Otherwise
general_operand. */
int
general_no_elim_operand (rtx op, enum machine_mode mode)
{
rtx t = op;
if (GET_CODE (t) == SUBREG)
t = SUBREG_REG (t);
if (t == arg_pointer_rtx || t == frame_pointer_rtx
|| t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx
|| t == virtual_stack_dynamic_rtx)
return 0;
if (REG_P (t)
&& REGNO (t) >= FIRST_VIRTUAL_REGISTER
&& REGNO (t) <= LAST_VIRTUAL_REGISTER)
return 0;
return general_operand (op, mode);
}
/* Return false if this is any eliminable register. Otherwise
register_operand or const_int. */
int
nonmemory_no_elim_operand (rtx op, enum machine_mode mode)
{
rtx t = op;
if (GET_CODE (t) == SUBREG)
t = SUBREG_REG (t);
if (t == arg_pointer_rtx || t == frame_pointer_rtx
|| t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx
|| t == virtual_stack_dynamic_rtx)
return 0;
return GET_CODE (op) == CONST_INT || register_operand (op, mode);
}
/* Return false if this is any eliminable register or stack register,
otherwise work like register_operand. */
int
index_register_operand (rtx op, enum machine_mode mode)
{
rtx t = op;
if (GET_CODE (t) == SUBREG)
t = SUBREG_REG (t);
if (!REG_P (t))
return 0;
if (t == arg_pointer_rtx
|| t == frame_pointer_rtx
|| t == virtual_incoming_args_rtx
|| t == virtual_stack_vars_rtx
|| t == virtual_stack_dynamic_rtx
|| REGNO (t) == STACK_POINTER_REGNUM)
return 0;
return general_operand (op, mode);
}
/* Return true if op is a Q_REGS class register. */
int
q_regs_operand (rtx op, enum machine_mode mode)
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return ANY_QI_REG_P (op);
}
/* Return true if op is an flags register. */
int
flags_reg_operand (rtx op, enum machine_mode mode)
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
return REG_P (op) && REGNO (op) == FLAGS_REG && GET_MODE (op) != VOIDmode;
}
/* Return true if op is a NON_Q_REGS class register. */
int
non_q_regs_operand (rtx op, enum machine_mode mode)
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return NON_QI_REG_P (op);
}
int
zero_extended_scalar_load_operand (rtx op,
enum machine_mode mode ATTRIBUTE_UNUSED)
{
unsigned n_elts;
if (GET_CODE (op) != MEM)
return 0;
op = maybe_get_pool_constant (op);
if (!op)
return 0;
if (GET_CODE (op) != CONST_VECTOR)
return 0;
n_elts =
(GET_MODE_SIZE (GET_MODE (op)) /
GET_MODE_SIZE (GET_MODE_INNER (GET_MODE (op))));
for (n_elts--; n_elts > 0; n_elts--)
{
rtx elt = CONST_VECTOR_ELT (op, n_elts);
if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
return 0;
}
return 1;
}
/* Return 1 when OP is operand acceptable for standard SSE move. */
int
vector_move_operand (rtx op, enum machine_mode mode)
{
if (nonimmediate_operand (op, mode))
return 1;
if (GET_MODE (op) != mode && mode != VOIDmode)
return 0;
return (op == CONST0_RTX (GET_MODE (op)));
}
/* Return true if op if a valid address, and does not contain
a segment override. */
int
no_seg_address_operand (rtx op, enum machine_mode mode)
{
struct ix86_address parts;
if (! address_operand (op, mode))
return 0;
if (! ix86_decompose_address (op, &parts))
abort ();
return parts.seg == SEG_DEFAULT;
}
/* Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS
insns. */
int
sse_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
enum rtx_code code = GET_CODE (op);
switch (code)
{
/* Operations supported directly. */
case EQ:
case LT:
case LE:
case UNORDERED:
case NE:
case UNGE:
case UNGT:
case ORDERED:
return 1;
/* These are equivalent to ones above in non-IEEE comparisons. */
case UNEQ:
case UNLT:
case UNLE:
case LTGT:
case GE:
case GT:
return !TARGET_IEEE_FP;
default:
return 0;
}
}
/* Return 1 if OP is a valid comparison operator in valid mode. */
int
ix86_comparison_operator (rtx op, enum machine_mode mode)
{
enum machine_mode inmode;
enum rtx_code code = GET_CODE (op);
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
if (!COMPARISON_P (op))
return 0;
inmode = GET_MODE (XEXP (op, 0));
if (inmode == CCFPmode || inmode == CCFPUmode)
{
enum rtx_code second_code, bypass_code;
ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
return (bypass_code == NIL && second_code == NIL);
}
switch (code)
{
case EQ: case NE:
return 1;
case LT: case GE:
if (inmode == CCmode || inmode == CCGCmode
|| inmode == CCGOCmode || inmode == CCNOmode)
return 1;
return 0;
case LTU: case GTU: case LEU: case ORDERED: case UNORDERED: case GEU:
if (inmode == CCmode)
return 1;
return 0;
case GT: case LE:
if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
return 1;
return 0;
default:
return 0;
}
}
/* Return 1 if OP is a valid comparison operator testing carry flag
to be set. */
int
ix86_carry_flag_operator (rtx op, enum machine_mode mode)
{
enum machine_mode inmode;
enum rtx_code code = GET_CODE (op);
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
if (!COMPARISON_P (op))
return 0;
inmode = GET_MODE (XEXP (op, 0));
if (GET_CODE (XEXP (op, 0)) != REG
|| REGNO (XEXP (op, 0)) != 17
|| XEXP (op, 1) != const0_rtx)
return 0;
if (inmode == CCFPmode || inmode == CCFPUmode)
{
enum rtx_code second_code, bypass_code;
ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
if (bypass_code != NIL || second_code != NIL)
return 0;
code = ix86_fp_compare_code_to_integer (code);
}
else if (inmode != CCmode)
return 0;
return code == LTU;
}
/* Return 1 if OP is a comparison operator that can be issued by fcmov. */ t = build2 (MODIFY_EXPR, void_type_node, dest, src);
gimplify_and_add (t, pre_p);
}
}
int if (needed_intregs)
fcmov_comparison_operator (rtx op, enum machine_mode mode) {
{ t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
enum machine_mode inmode; build_int_2 (needed_intregs * 8, 0));
enum rtx_code code = GET_CODE (op); t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
gimplify_and_add (t, pre_p);
}
if (needed_sseregs)
{
t =
build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
build_int_2 (needed_sseregs * 16, 0));
t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
gimplify_and_add (t, pre_p);
}
if (mode != VOIDmode && GET_MODE (op) != mode) t = build1 (GOTO_EXPR, void_type_node, lab_over);
return 0; gimplify_and_add (t, pre_p);
if (!COMPARISON_P (op))
return 0;
inmode = GET_MODE (XEXP (op, 0));
if (inmode == CCFPmode || inmode == CCFPUmode)
{
enum rtx_code second_code, bypass_code;
ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); t = build1 (LABEL_EXPR, void_type_node, lab_false);
if (bypass_code != NIL || second_code != NIL) append_to_statement_list (t, pre_p);
return 0;
code = ix86_fp_compare_code_to_integer (code);
}
/* i387 supports just limited amount of conditional codes. */
switch (code)
{
case LTU: case GTU: case LEU: case GEU:
if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode)
return 1;
return 0;
case ORDERED: case UNORDERED:
case EQ: case NE:
return 1;
default:
return 0;
} }
}
/* Return 1 if OP is a binary operator that can be promoted to wider mode. */ /* ... otherwise out of the overflow area. */
int /* Care for on-stack alignment if needed. */
promotable_binary_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64)
{ t = ovf;
switch (GET_CODE (op)) else
{ {
case MULT: HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
/* Modern CPUs have same latency for HImode and SImode multiply, t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align - 1, 0));
but 386 and 486 do HImode multiply faster. */ t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
return ix86_tune > PROCESSOR_I486;
case PLUS:
case AND:
case IOR:
case XOR:
case ASHIFT:
return 1;
default:
return 0;
} }
} gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
/* Nearly general operand, but accept any const_double, since we wish
to be able to drop them into memory rather than have them get pulled
into registers. */
int
cmp_fp_expander_operand (rtx op, enum machine_mode mode)
{
if (mode != VOIDmode && mode != GET_MODE (op))
return 0;
if (GET_CODE (op) == CONST_DOUBLE)
return 1;
return general_operand (op, mode);
}
/* Match an SI or HImode register for a zero_extract. */
int
ext_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
int regno;
if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return 0;
if (!register_operand (op, VOIDmode))
return 0;
/* Be careful to accept only registers having upper parts. */
regno = REG_P (op) ? REGNO (op) : REGNO (SUBREG_REG (op));
return (regno > LAST_VIRTUAL_REGISTER || regno < 4);
}
/* Return 1 if this is a valid binary floating-point operation. t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
OP is the expression matched, and MODE is its mode. */ gimplify_and_add (t2, pre_p);
int t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
binary_fp_operator (rtx op, enum machine_mode mode) build_int_2 (rsize * UNITS_PER_WORD, 0));
{ t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
if (mode != VOIDmode && mode != GET_MODE (op)) gimplify_and_add (t, pre_p);
return 0;
switch (GET_CODE (op)) if (container)
{ {
case PLUS: t = build1 (LABEL_EXPR, void_type_node, lab_over);
case MINUS: append_to_statement_list (t, pre_p);
case MULT:
case DIV:
return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
default:
return 0;
} }
}
int ptrtype = build_pointer_type (type);
mult_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) addr = fold_convert (ptrtype, addr);
{
return GET_CODE (op) == MULT;
}
int
div_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return GET_CODE (op) == DIV;
}
int if (indirect_p)
arith_or_logical_operator (rtx op, enum machine_mode mode) addr = build_fold_indirect_ref (addr);
{ return build_fold_indirect_ref (addr);
return ((mode == VOIDmode || GET_MODE (op) == mode)
&& ARITHMETIC_P (op));
} }
/* Returns 1 if OP is memory operand with a displacement. */ /* Return nonzero if OPNUM's MEM should be matched
in movabs* patterns. */
int int
memory_displacement_operand (rtx op, enum machine_mode mode) ix86_check_movabs (rtx insn, int opnum)
{ {
struct ix86_address parts; rtx set, mem;
if (! memory_operand (op, mode))
return 0;
if (! ix86_decompose_address (XEXP (op, 0), &parts)) set = PATTERN (insn);
if (GET_CODE (set) == PARALLEL)
set = XVECEXP (set, 0, 0);
if (GET_CODE (set) != SET)
abort (); abort ();
mem = XEXP (set, opnum);
return parts.disp != NULL_RTX; while (GET_CODE (mem) == SUBREG)
} mem = SUBREG_REG (mem);
if (GET_CODE (mem) != MEM)
/* To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0,
re-recognize the operand to avoid a copy_to_mode_reg that will fail.
??? It seems likely that this will only work because cmpsi is an
expander, and no actual insns use this. */
int
cmpsi_operand (rtx op, enum machine_mode mode)
{
if (nonimmediate_operand (op, mode))
return 1;
if (GET_CODE (op) == AND
&& GET_MODE (op) == SImode
&& GET_CODE (XEXP (op, 0)) == ZERO_EXTRACT
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
&& GET_CODE (XEXP (XEXP (op, 0), 2)) == CONST_INT
&& INTVAL (XEXP (XEXP (op, 0), 1)) == 8
&& INTVAL (XEXP (XEXP (op, 0), 2)) == 8
&& GET_CODE (XEXP (op, 1)) == CONST_INT)
return 1;
return 0;
}
/* Returns 1 if OP is memory operand that can not be represented by the
modRM array. */
int
long_memory_operand (rtx op, enum machine_mode mode)
{
if (! memory_operand (op, mode))
return 0;
return memory_address_length (op) != 0;
}
/* Return nonzero if the rtx is known aligned. */
int
aligned_operand (rtx op, enum machine_mode mode)
{
struct ix86_address parts;
if (!general_operand (op, mode))
return 0;
/* Registers and immediate operands are always "aligned". */
if (GET_CODE (op) != MEM)
return 1;
/* Don't even try to do any aligned optimizations with volatiles. */
if (MEM_VOLATILE_P (op))
return 0;
op = XEXP (op, 0);
/* Pushes and pops are only valid on the stack pointer. */
if (GET_CODE (op) == PRE_DEC
|| GET_CODE (op) == POST_INC)
return 1;
/* Decode the address. */
if (! ix86_decompose_address (op, &parts))
abort (); abort ();
return (volatile_ok || !MEM_VOLATILE_P (mem));
/* Look for some component that isn't known to be aligned. */
if (parts.index)
{
if (parts.scale < 4
&& REGNO_POINTER_ALIGN (REGNO (parts.index)) < 32)
return 0;
}
if (parts.base)
{
if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
return 0;
}
if (parts.disp)
{
if (GET_CODE (parts.disp) != CONST_INT
|| (INTVAL (parts.disp) & 3) != 0)
return 0;
}
/* Didn't find one -- this must be an aligned address. */
return 1;
} }
/* Initialize the table of extra 80387 mathematical constants. */ /* Initialize the table of extra 80387 mathematical constants. */
...@@ -4644,196 +3712,6 @@ ix86_can_use_return_insn_p (void) ...@@ -4644,196 +3712,6 @@ ix86_can_use_return_insn_p (void)
return frame.to_allocate == 0 && frame.nregs == 0; return frame.to_allocate == 0 && frame.nregs == 0;
} }
/* Return 1 if VALUE can be stored in the sign extended immediate field. */
int
x86_64_sign_extended_value (rtx value)
{
switch (GET_CODE (value))
{
/* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
to be at least 32 and this all acceptable constants are
represented as CONST_INT. */
case CONST_INT:
if (HOST_BITS_PER_WIDE_INT == 32)
return 1;
else
{
HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (value), DImode);
return trunc_int_for_mode (val, SImode) == val;
}
break;
/* For certain code models, the symbolic references are known to fit.
in CM_SMALL_PIC model we know it fits if it is local to the shared
library. Don't count TLS SYMBOL_REFs here, since they should fit
only if inside of UNSPEC handled below. */
case SYMBOL_REF:
/* TLS symbols are not constant. */
if (tls_symbolic_operand (value, Pmode))
return false;
return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL);
/* For certain code models, the code is near as well. */
case LABEL_REF:
return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
|| ix86_cmodel == CM_KERNEL);
/* We also may accept the offsetted memory references in certain special
cases. */
case CONST:
if (GET_CODE (XEXP (value, 0)) == UNSPEC)
switch (XINT (XEXP (value, 0), 1))
{
case UNSPEC_GOTPCREL:
case UNSPEC_DTPOFF:
case UNSPEC_GOTNTPOFF:
case UNSPEC_NTPOFF:
return 1;
default:
break;
}
if (GET_CODE (XEXP (value, 0)) == PLUS)
{
rtx op1 = XEXP (XEXP (value, 0), 0);
rtx op2 = XEXP (XEXP (value, 0), 1);
HOST_WIDE_INT offset;
if (ix86_cmodel == CM_LARGE)
return 0;
if (GET_CODE (op2) != CONST_INT)
return 0;
offset = trunc_int_for_mode (INTVAL (op2), DImode);
switch (GET_CODE (op1))
{
case SYMBOL_REF:
/* For CM_SMALL assume that latest object is 16MB before
end of 31bits boundary. We may also accept pretty
large negative constants knowing that all objects are
in the positive half of address space. */
if (ix86_cmodel == CM_SMALL
&& offset < 16*1024*1024
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
/* For CM_KERNEL we know that all object resist in the
negative half of 32bits address space. We may not
accept negative offsets, since they may be just off
and we may accept pretty large positive ones. */
if (ix86_cmodel == CM_KERNEL
&& offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
break;
case LABEL_REF:
/* These conditions are similar to SYMBOL_REF ones, just the
constraints for code models differ. */
if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
&& offset < 16*1024*1024
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
if (ix86_cmodel == CM_KERNEL
&& offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
break;
case UNSPEC:
switch (XINT (op1, 1))
{
case UNSPEC_DTPOFF:
case UNSPEC_NTPOFF:
if (offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
}
break;
default:
return 0;
}
}
return 0;
default:
return 0;
}
}
/* Return 1 if VALUE can be stored in the zero extended immediate field. */
int
x86_64_zero_extended_value (rtx value)
{
switch (GET_CODE (value))
{
case CONST_DOUBLE:
if (HOST_BITS_PER_WIDE_INT == 32)
return (GET_MODE (value) == VOIDmode
&& !CONST_DOUBLE_HIGH (value));
else
return 0;
case CONST_INT:
if (HOST_BITS_PER_WIDE_INT == 32)
return INTVAL (value) >= 0;
else
return !(INTVAL (value) & ~(HOST_WIDE_INT) 0xffffffff);
break;
/* For certain code models, the symbolic references are known to fit. */
case SYMBOL_REF:
/* TLS symbols are not constant. */
if (tls_symbolic_operand (value, Pmode))
return false;
return ix86_cmodel == CM_SMALL;
/* For certain code models, the code is near as well. */
case LABEL_REF:
return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
/* We also may accept the offsetted memory references in certain special
cases. */
case CONST:
if (GET_CODE (XEXP (value, 0)) == PLUS)
{
rtx op1 = XEXP (XEXP (value, 0), 0);
rtx op2 = XEXP (XEXP (value, 0), 1);
if (ix86_cmodel == CM_LARGE)
return 0;
switch (GET_CODE (op1))
{
case SYMBOL_REF:
return 0;
/* For small code model we may accept pretty large positive
offsets, since one bit is available for free. Negative
offsets are limited by the size of NULL pointer area
specified by the ABI. */
if (ix86_cmodel == CM_SMALL
&& GET_CODE (op2) == CONST_INT
&& trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
&& (trunc_int_for_mode (INTVAL (op2), SImode)
== INTVAL (op2)))
return 1;
/* ??? For the kernel, we may accept adjustment of
-0x10000000, since we know that it will just convert
negative address space to positive, but perhaps this
is not worthwhile. */
break;
case LABEL_REF:
/* These conditions are similar to SYMBOL_REF ones, just the
constraints for code models differ. */
if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
&& GET_CODE (op2) == CONST_INT
&& trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
&& (trunc_int_for_mode (INTVAL (op2), SImode)
== INTVAL (op2)))
return 1;
break;
default:
return 0;
}
}
return 0;
default:
return 0;
}
}
/* Value should be nonzero if functions must have frame pointers. /* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms may Zero means the frame pointer need not be set up (and parms may
be accessed via the stack pointer) in functions that seem suitable. */ be accessed via the stack pointer) in functions that seem suitable. */
...@@ -5664,7 +4542,7 @@ ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, ...@@ -5664,7 +4542,7 @@ ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
grossly off. Return -1 if the address contains ASHIFT, so it is not grossly off. Return -1 if the address contains ASHIFT, so it is not
strictly valid, but still used for computing length of lea instruction. */ strictly valid, but still used for computing length of lea instruction. */
static int int
ix86_decompose_address (rtx addr, struct ix86_address *out) ix86_decompose_address (rtx addr, struct ix86_address *out)
{ {
rtx base = NULL_RTX; rtx base = NULL_RTX;
...@@ -6328,7 +5206,8 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) ...@@ -6328,7 +5206,8 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
reason = "displacement is not constant"; reason = "displacement is not constant";
goto report_error; goto report_error;
} }
else if (TARGET_64BIT && !x86_64_sign_extended_value (disp)) else if (TARGET_64BIT
&& !x86_64_immediate_operand (disp, VOIDmode))
{ {
reason = "displacement is out of range"; reason = "displacement is out of range";
goto report_error; goto report_error;
...@@ -6705,12 +5584,13 @@ legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) ...@@ -6705,12 +5584,13 @@ legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
debug_rtx (x); debug_rtx (x);
} }
log = tls_symbolic_operand (x, mode); log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
if (log) if (log)
return legitimize_tls_address (x, log, false); return legitimize_tls_address (x, log, false);
if (GET_CODE (x) == CONST if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
&& (log = tls_symbolic_operand (XEXP (XEXP (x, 0), 0), Pmode))) && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
&& (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
{ {
rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false); rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1)); return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
...@@ -8457,7 +7337,7 @@ ix86_expand_clear (rtx dest) ...@@ -8457,7 +7337,7 @@ ix86_expand_clear (rtx dest)
/* X is an unchanging MEM. If it is a constant pool reference, return /* X is an unchanging MEM. If it is a constant pool reference, return
the constant pool rtx, else NULL. */ the constant pool rtx, else NULL. */
static rtx rtx
maybe_get_pool_constant (rtx x) maybe_get_pool_constant (rtx x)
{ {
x = ix86_delegitimize_address (XEXP (x, 0)); x = ix86_delegitimize_address (XEXP (x, 0));
...@@ -8478,7 +7358,7 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) ...@@ -8478,7 +7358,7 @@ ix86_expand_move (enum machine_mode mode, rtx operands[])
op0 = operands[0]; op0 = operands[0];
op1 = operands[1]; op1 = operands[1];
model = tls_symbolic_operand (op1, Pmode); model = GET_CODE (op1) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (op1) : 0;
if (model) if (model)
{ {
op1 = legitimize_tls_address (op1, model, true); op1 = legitimize_tls_address (op1, model, true);
...@@ -8527,7 +7407,7 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) ...@@ -8527,7 +7407,7 @@ ix86_expand_move (enum machine_mode mode, rtx operands[])
to get them CSEed. */ to get them CSEed. */
if (TARGET_64BIT && mode == DImode if (TARGET_64BIT && mode == DImode
&& immediate_operand (op1, mode) && immediate_operand (op1, mode)
&& !x86_64_zero_extended_value (op1) && !x86_64_zext_immediate_operand (op1, VOIDmode)
&& !register_operand (op0, mode) && !register_operand (op0, mode)
&& optimize && !reload_completed && !reload_in_progress) && optimize && !reload_completed && !reload_in_progress)
op1 = copy_to_mode_reg (mode, op1); op1 = copy_to_mode_reg (mode, op1);
...@@ -9045,7 +7925,8 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) ...@@ -9045,7 +7925,8 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
/* Convert comparison codes we use to represent FP comparison to integer /* Convert comparison codes we use to represent FP comparison to integer
code that will result in proper branch. Return UNKNOWN if no such code code that will result in proper branch. Return UNKNOWN if no such code
is available. */ is available. */
static enum rtx_code
enum rtx_code
ix86_fp_compare_code_to_integer (enum rtx_code code) ix86_fp_compare_code_to_integer (enum rtx_code code)
{ {
switch (code) switch (code)
...@@ -9080,7 +7961,8 @@ ix86_fp_compare_code_to_integer (enum rtx_code code) ...@@ -9080,7 +7961,8 @@ ix86_fp_compare_code_to_integer (enum rtx_code code)
branch around FIRST_CODE and SECOND_CODE. If some of branches branch around FIRST_CODE and SECOND_CODE. If some of branches
is not required, set value to NIL. is not required, set value to NIL.
We never require more than two branches. */ We never require more than two branches. */
static void
void
ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code, ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
enum rtx_code *first_code, enum rtx_code *first_code,
enum rtx_code *second_code) enum rtx_code *second_code)
...@@ -10142,7 +9024,8 @@ ix86_expand_int_movcc (rtx operands[]) ...@@ -10142,7 +9024,8 @@ ix86_expand_int_movcc (rtx operands[])
if ((diff == 1 || diff == 2 || diff == 4 || diff == 8 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
|| diff == 3 || diff == 5 || diff == 9) || diff == 3 || diff == 5 || diff == 9)
&& ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL) && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
&& (mode != DImode || x86_64_sign_extended_value (GEN_INT (cf)))) && (mode != DImode
|| x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
{ {
/* /*
* xorl dest,dest * xorl dest,dest
...@@ -11220,8 +10103,9 @@ ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp) ...@@ -11220,8 +10103,9 @@ ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
/* Figure out proper mode for counter. For 32bits it is always SImode, /* Figure out proper mode for counter. For 32bits it is always SImode,
for 64bits use SImode when possible, otherwise DImode. for 64bits use SImode when possible, otherwise DImode.
Set count to number of bytes copied when known at compile time. */ Set count to number of bytes copied when known at compile time. */
if (!TARGET_64BIT || GET_MODE (count_exp) == SImode if (!TARGET_64BIT
|| x86_64_zero_extended_value (count_exp)) || GET_MODE (count_exp) == SImode
|| x86_64_zext_immediate_operand (count_exp, VOIDmode))
counter_mode = SImode; counter_mode = SImode;
else else
counter_mode = DImode; counter_mode = DImode;
...@@ -11498,8 +10382,9 @@ ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp) ...@@ -11498,8 +10382,9 @@ ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp)
/* Figure out proper mode for counter. For 32bits it is always SImode, /* Figure out proper mode for counter. For 32bits it is always SImode,
for 64bits use SImode when possible, otherwise DImode. for 64bits use SImode when possible, otherwise DImode.
Set count to number of bytes copied when known at compile time. */ Set count to number of bytes copied when known at compile time. */
if (!TARGET_64BIT || GET_MODE (count_exp) == SImode if (!TARGET_64BIT
|| x86_64_zero_extended_value (count_exp)) || GET_MODE (count_exp) == SImode
|| x86_64_zext_immediate_operand (count_exp, VOIDmode))
counter_mode = SImode; counter_mode = SImode;
else else
counter_mode = DImode; counter_mode = DImode;
...@@ -12127,7 +11012,7 @@ ix86_tls_get_addr (void) ...@@ -12127,7 +11012,7 @@ ix86_tls_get_addr (void)
/* Calculate the length of the memory address in the instruction /* Calculate the length of the memory address in the instruction
encoding. Does not include the one-byte modrm, opcode, or prefix. */ encoding. Does not include the one-byte modrm, opcode, or prefix. */
static int int
memory_address_length (rtx addr) memory_address_length (rtx addr)
{ {
struct ix86_address parts; struct ix86_address parts;
...@@ -12701,7 +11586,7 @@ x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) ...@@ -12701,7 +11586,7 @@ x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
/* Try to load address using shorter movl instead of movabs. /* Try to load address using shorter movl instead of movabs.
We may want to support movq for kernel mode, but kernel does not use We may want to support movq for kernel mode, but kernel does not use
trampolines at the moment. */ trampolines at the moment. */
if (x86_64_zero_extended_value (fnaddr)) if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
{ {
fnaddr = copy_to_mode_reg (DImode, fnaddr); fnaddr = copy_to_mode_reg (DImode, fnaddr);
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)), emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
...@@ -14984,9 +13869,9 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) ...@@ -14984,9 +13869,9 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
case CONST: case CONST:
case LABEL_REF: case LABEL_REF:
case SYMBOL_REF: case SYMBOL_REF:
if (TARGET_64BIT && !x86_64_sign_extended_value (x)) if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
*total = 3; *total = 3;
else if (TARGET_64BIT && !x86_64_zero_extended_value (x)) else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
*total = 2; *total = 2;
else if (flag_pic && SYMBOLIC_CONST (x) else if (flag_pic && SYMBOLIC_CONST (x)
&& (!TARGET_64BIT && (!TARGET_64BIT
......
gcc/config/i386/i386.h
...@@ -1502,10 +1502,10 @@ enum reg_class ...@@ -1502,10 +1502,10 @@ enum reg_class
the constraint letter C. If C is not defined as an extra the constraint letter C. If C is not defined as an extra
constraint, the value returned should be 0 regardless of VALUE. */ constraint, the value returned should be 0 regardless of VALUE. */
#define EXTRA_CONSTRAINT(VALUE, D) \ #define EXTRA_CONSTRAINT(VALUE, D) \
((D) == 'e' ? x86_64_sign_extended_value (VALUE) \ ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
: (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \ : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
: (D) == 'C' ? standard_sse_constant_p (VALUE) \ : (D) == 'C' ? standard_sse_constant_p (VALUE) \
: 0) : 0)
/* Place additional restrictions on the register class to use when it /* Place additional restrictions on the register class to use when it
...@@ -2830,94 +2830,6 @@ do { \ ...@@ -2830,94 +2830,6 @@ do { \
#define RET return "" #define RET return ""
#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
/* Define the codes that are matched by predicates in i386.c. */
#define PREDICATE_CODES \
{"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
SYMBOL_REF, LABEL_REF, CONST}}, \
{"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
SYMBOL_REF, LABEL_REF, CONST}}, \
{"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
SYMBOL_REF, LABEL_REF, CONST}}, \
{"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
SYMBOL_REF, LABEL_REF, CONST}}, \
{"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
SYMBOL_REF, LABEL_REF, CONST}}, \
{"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
SYMBOL_REF, LABEL_REF, CONST}}, \
{"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF}}, \
{"shiftdi_operand", {SUBREG, REG, MEM}}, \
{"const_int_1_31_operand", {CONST_INT}}, \
{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
{"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM}}, \
{"pic_symbolic_operand", {CONST}}, \
{"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
{"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \
{"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
{"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
{"const1_operand", {CONST_INT}}, \
{"const248_operand", {CONST_INT}}, \
{"const_0_to_3_operand", {CONST_INT}}, \
{"const_0_to_7_operand", {CONST_INT}}, \
{"const_0_to_15_operand", {CONST_INT}}, \
{"const_0_to_255_operand", {CONST_INT}}, \
{"incdec_operand", {CONST_INT}}, \
{"mmx_reg_operand", {REG}}, \
{"reg_no_sp_operand", {SUBREG, REG}}, \
{"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
{"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
{"index_register_operand", {SUBREG, REG}}, \
{"flags_reg_operand", {REG}}, \
{"q_regs_operand", {SUBREG, REG}}, \
{"non_q_regs_operand", {SUBREG, REG}}, \
{"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
GE, UNGE, LTGT, UNEQ}}, \
{"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
}}, \
{"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
GTU, UNORDERED, ORDERED, UNLE, UNLT, \
UNGE, UNGT, LTGT, UNEQ }}, \
{"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \
GE, UNGE, LTGT, UNEQ}}, \
{"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
{"ext_register_operand", {SUBREG, REG}}, \
{"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
{"mult_operator", {MULT}}, \
{"div_operator", {DIV}}, \
{"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
LSHIFTRT, ROTATERT}}, \
{"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
{"memory_displacement_operand", {MEM}}, \
{"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM, AND}}, \
{"long_memory_operand", {MEM}}, \
{"tls_symbolic_operand", {SYMBOL_REF}}, \
{"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
{"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
{"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
{"local_exec_symbolic_operand", {SYMBOL_REF}}, \
{"any_fp_register_operand", {REG}}, \
{"register_and_not_any_fp_reg_operand", {REG}}, \
{"fp_register_operand", {REG}}, \
{"register_and_not_fp_reg_operand", {REG}}, \
{"zero_extended_scalar_load_operand", {MEM}}, \
{"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \
{"no_seg_address_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM, PLUS, MULT}},
/* A list of predicates that do special things with modes, and so
should not elicit warnings for VOIDmode match_operand. */
#define SPECIAL_MODE_PREDICATES \
"ext_register_operand",
/* Which processor to schedule for. The cpu attribute defines a list that /* Which processor to schedule for. The cpu attribute defines a list that
mirrors this list, so changes to i386.md must be made at the same time. */ mirrors this list, so changes to i386.md must be made at the same time. */
......
gcc/config/i386/i386.md
;; GCC machine description for IA-32 and x86-64. ;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
;; 2001, 2002, 2003, 2004 ;; 2001, 2002, 2003, 2004
...@@ -426,10 +425,18 @@ ...@@ -426,10 +425,18 @@
[(set_attr "length" "128") [(set_attr "length" "128")
(set_attr "type" "multi")]) (set_attr "type" "multi")])
;; Scheduling descriptions
(include "pentium.md") (include "pentium.md")
(include "ppro.md") (include "ppro.md")
(include "k6.md") (include "k6.md")
(include "athlon.md") (include "athlon.md")
;; Operand and operator predicates
(include "predicates.md")
;; Compare instructions. ;; Compare instructions.
......
gcc/config/i386/predicates.md 0 → 100644
;; Predicate definitions for IA-32 and x86-64.
;; Copyright (C) 2004 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
;; Return nonzero if OP is either a i387 or SSE fp register.
(define_predicate "any_fp_register_operand"
(and (match_code "reg")
(match_test "ANY_FP_REGNO_P (REGNO (op))")))
;; Return nonzero if OP is an i387 fp register.
(define_predicate "fp_register_operand"
(and (match_code "reg")
(match_test "FP_REGNO_P (REGNO (op))")))
;; Return nonzero if OP is a non-fp register_operand.
(define_predicate "register_and_not_any_fp_reg_operand"
(and (match_code "reg")
(not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
;; Return nonzero if OP is a register operand other than an i387 fp register.
(define_predicate "register_and_not_fp_reg_operand"
(and (match_code "reg")
(not (match_test "FP_REGNO_P (REGNO (op))"))))
;; True if the operand is an MMX register.
(define_predicate "mmx_reg_operand"
(and (match_code "reg")
(match_test "MMX_REGNO_P (REGNO (op))")))
;; True if the operand is a Q_REGS class register.
(define_predicate "q_regs_operand"
(match_operand 0 "register_operand")
{
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return ANY_QI_REG_P (op);
})
;; Return true if op is a NON_Q_REGS class register.
(define_predicate "non_q_regs_operand"
(match_operand 0 "register_operand")
{
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return NON_QI_REG_P (op);
})
;; Match an SI or HImode register for a zero_extract.
(define_special_predicate "ext_register_operand"
(match_operand 0 "register_operand")
{
if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
/* Be careful to accept only registers having upper parts. */
return REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) < 4;
})
;; Return true if op is the flags register.
(define_predicate "flags_reg_operand"
(and (match_code "reg")
(match_test "REGNO (op) == FLAGS_REG")))
;; Return 1 if VALUE can be stored in a sign extended immediate field.
(define_predicate "x86_64_immediate_operand"
(match_code "const_int,symbol_ref,label_ref,const")
{
if (!TARGET_64BIT)
return immediate_operand (op, mode);
switch (GET_CODE (op))
{
case CONST_INT:
/* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
to be at least 32 and this all acceptable constants are
represented as CONST_INT. */
if (HOST_BITS_PER_WIDE_INT == 32)
return 1;
else
{
HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
return trunc_int_for_mode (val, SImode) == val;
}
break;
case SYMBOL_REF:
/* For certain code models, the symbolic references are known to fit.
in CM_SMALL_PIC model we know it fits if it is local to the shared
library. Don't count TLS SYMBOL_REFs here, since they should fit
only if inside of UNSPEC handled below. */
/* TLS symbols are not constant. */
if (tls_symbolic_operand (op, Pmode))
return false;
return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL);
case LABEL_REF:
/* For certain code models, the code is near as well. */
return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
|| ix86_cmodel == CM_KERNEL);
case CONST:
/* We also may accept the offsetted memory references in certain
special cases. */
if (GET_CODE (XEXP (op, 0)) == UNSPEC)
switch (XINT (XEXP (op, 0), 1))
{
case UNSPEC_GOTPCREL:
case UNSPEC_DTPOFF:
case UNSPEC_GOTNTPOFF:
case UNSPEC_NTPOFF:
return 1;
default:
break;
}
if (GET_CODE (XEXP (op, 0)) == PLUS)
{
rtx op1 = XEXP (XEXP (op, 0), 0);
rtx op2 = XEXP (XEXP (op, 0), 1);
HOST_WIDE_INT offset;
if (ix86_cmodel == CM_LARGE)
return 0;
if (GET_CODE (op2) != CONST_INT)
return 0;
offset = trunc_int_for_mode (INTVAL (op2), DImode);
switch (GET_CODE (op1))
{
case SYMBOL_REF:
/* For CM_SMALL assume that latest object is 16MB before
end of 31bits boundary. We may also accept pretty
large negative constants knowing that all objects are
in the positive half of address space. */
if (ix86_cmodel == CM_SMALL
&& offset < 16*1024*1024
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
/* For CM_KERNEL we know that all object resist in the
negative half of 32bits address space. We may not
accept negative offsets, since they may be just off
and we may accept pretty large positive ones. */
if (ix86_cmodel == CM_KERNEL
&& offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
break;
case LABEL_REF:
/* These conditions are similar to SYMBOL_REF ones, just the
constraints for code models differ. */
if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
&& offset < 16*1024*1024
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
if (ix86_cmodel == CM_KERNEL
&& offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
break;
case UNSPEC:
switch (XINT (op1, 1))
{
case UNSPEC_DTPOFF:
case UNSPEC_NTPOFF:
if (offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
}
break;
default:
break;
}
}
break;
default:
abort ();
}
return 0;
})
;; Return 1 if VALUE can be stored in the zero extended immediate field.
(define_predicate "x86_64_zext_immediate_operand"
(match_code "const_double,const_int,symbol_ref,label_ref,const")
{
switch (GET_CODE (op))
{
case CONST_DOUBLE:
if (HOST_BITS_PER_WIDE_INT == 32)
return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
else
return 0;
case CONST_INT:
if (HOST_BITS_PER_WIDE_INT == 32)
return INTVAL (op) >= 0;
else
return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
case SYMBOL_REF:
/* For certain code models, the symbolic references are known to fit. */
/* TLS symbols are not constant. */
if (tls_symbolic_operand (op, Pmode))
return false;
return ix86_cmodel == CM_SMALL;
case LABEL_REF:
/* For certain code models, the code is near as well. */
return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
case CONST:
/* We also may accept the offsetted memory references in certain
special cases. */
if (GET_CODE (XEXP (op, 0)) == PLUS)
{
rtx op1 = XEXP (XEXP (op, 0), 0);
rtx op2 = XEXP (XEXP (op, 0), 1);
if (ix86_cmodel == CM_LARGE)
return 0;
switch (GET_CODE (op1))
{
case SYMBOL_REF:
/* For small code model we may accept pretty large positive
offsets, since one bit is available for free. Negative
offsets are limited by the size of NULL pointer area
specified by the ABI. */
if (ix86_cmodel == CM_SMALL
&& GET_CODE (op2) == CONST_INT
&& trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
&& trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
return 1;
/* ??? For the kernel, we may accept adjustment of
-0x10000000, since we know that it will just convert
negative address space to positive, but perhaps this
is not worthwhile. */
break;
case LABEL_REF:
/* These conditions are similar to SYMBOL_REF ones, just the
constraints for code models differ. */
if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
&& GET_CODE (op2) == CONST_INT
&& trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
&& trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
return 1;
break;
default:
return 0;
}
}
break;
default:
abort ();
}
return 0;
})
;; Return nonzero if OP is general operand representable on x86_64.
(define_predicate "x86_64_general_operand"
(if_then_else (match_test "TARGET_64BIT")
(ior (match_operand 0 "nonimmediate_operand")
(match_operand 0 "x86_64_immediate_operand"))
(match_operand 0 "general_operand")))
;; Return nonzero if OP is general operand representable on x86_64
;; as either sign extended or zero extended constant.
(define_predicate "x86_64_szext_general_operand"
(if_then_else (match_test "TARGET_64BIT")
(ior (match_operand 0 "nonimmediate_operand")
(ior (match_operand 0 "x86_64_immediate_operand")
(match_operand 0 "x86_64_zext_immediate_operand")))
(match_operand 0 "general_operand")))
;; Return nonzero if OP is nonmemory operand representable on x86_64.
(define_predicate "x86_64_nonmemory_operand"
(if_then_else (match_test "TARGET_64BIT")
(ior (match_operand 0 "register_operand")
(match_operand 0 "x86_64_immediate_operand"))
(match_operand 0 "nonmemory_operand")))
;; Return nonzero if OP is nonmemory operand representable on x86_64.
(define_predicate "x86_64_szext_nonmemory_operand"
(if_then_else (match_test "TARGET_64BIT")
(ior (match_operand 0 "register_operand")
(ior (match_operand 0 "x86_64_immediate_operand")
(match_operand 0 "x86_64_zext_immediate_operand")))
(match_operand 0 "nonmemory_operand")))
;; Return nonzero if OP is nonmemory operand acceptable by movabs patterns.
(define_predicate "x86_64_movabs_operand"
(if_then_else (match_test "!TARGET_64BIT || !flag_pic")
(match_operand 0 "nonmemory_operand")
(ior (match_operand 0 "register_operand")
(and (match_operand 0 "const_double_operand")
(match_test "GET_MODE_SIZE (mode) <= 8")))))
;; Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand
;; for shift & compare patterns, as shifting by 0 does not change flags).
(define_predicate "const_int_1_31_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 1 && INTVAL (op) <= 31")))
;; Returns nonzero if OP is either a symbol reference or a sum of a symbol
;; reference and a constant.
(define_predicate "symbolic_operand"
(match_code "symbol_ref,label_ref,const")
{
switch (GET_CODE (op))
{
case SYMBOL_REF:
case LABEL_REF:
return 1;
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF
|| (GET_CODE (op) == UNSPEC
&& (XINT (op, 1) == UNSPEC_GOT
|| XINT (op, 1) == UNSPEC_GOTOFF
|| XINT (op, 1) == UNSPEC_GOTPCREL)))
return 1;
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 1)) != CONST_INT)
return 0;
op = XEXP (op, 0);
if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF)
return 1;
/* Only @GOTOFF gets offsets. */
if (GET_CODE (op) != UNSPEC
|| XINT (op, 1) != UNSPEC_GOTOFF)
return 0;
op = XVECEXP (op, 0, 0);
if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF)
return 1;
return 0;
default:
abort ();
}
})
;; Return true if the operand contains a @GOT or @GOTOFF reference.
(define_predicate "pic_symbolic_operand"
(match_code "const")
{
op = XEXP (op, 0);
if (TARGET_64BIT)
{
if (GET_CODE (op) == UNSPEC
&& XINT (op, 1) == UNSPEC_GOTPCREL)
return 1;
if (GET_CODE (op) == PLUS
&& GET_CODE (XEXP (op, 0)) == UNSPEC
&& XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL)
return 1;
}
else
{
if (GET_CODE (op) == UNSPEC)
return 1;
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 1)) != CONST_INT)
return 0;
op = XEXP (op, 0);
if (GET_CODE (op) == UNSPEC)
return 1;
}
return 0;
})
;; Return true if OP is a symbolic operand that resolves locally.
(define_predicate "local_symbolic_operand"
(match_code "const,label_ref,symbol_ref")
{
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
op = XEXP (XEXP (op, 0), 0);
if (GET_CODE (op) == LABEL_REF)
return 1;
if (GET_CODE (op) != SYMBOL_REF)
return 0;
if (SYMBOL_REF_LOCAL_P (op))
return 1;
/* There is, however, a not insubstantial body of code in the rest of
the compiler that assumes it can just stick the results of
ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
/* ??? This is a hack. Should update the body of the compiler to
always create a DECL an invoke targetm.encode_section_info. */
if (strncmp (XSTR (op, 0), internal_label_prefix,
internal_label_prefix_len) == 0)
return 1;
return 0;
})
;; Test for various thread-local symbols.
(define_predicate "tls_symbolic_operand"
(and (match_code "symbol_ref")
(match_test "SYMBOL_REF_TLS_MODEL (op) != 0")))
(define_predicate "global_dynamic_symbolic_operand"
(and (match_code "symbol_ref")
(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC")))
(define_predicate "local_dynamic_symbolic_operand"
(and (match_code "symbol_ref")
(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC")))
(define_predicate "initial_exec_symbolic_operand"
(and (match_code "symbol_ref")
(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC")))
(define_predicate "local_exec_symbolic_operand"
(and (match_code "symbol_ref")
(match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC")))
;; Test for a pc-relative call operand
(define_predicate "constant_call_address_operand"
(ior (match_code "symbol_ref")
(match_operand 0 "local_symbolic_operand")))
;; True for any non-virtual or eliminable register. Used in places where
;; instantiation of such a register may cause the pattern to not be recognized.
(define_predicate "register_no_elim_operand"
(match_operand 0 "register_operand")
{
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return !(op == arg_pointer_rtx
|| op == frame_pointer_rtx
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& REGNO (op) <= LAST_VIRTUAL_REGISTER));
})
;; Similarly, but include the stack pointer. This is used to prevent esp
;; from being used as an index reg.
(define_predicate "index_register_operand"
(match_operand 0 "register_operand")
{
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return !(op == stack_pointer_rtx
|| op == arg_pointer_rtx
|| op == frame_pointer_rtx
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& REGNO (op) <= LAST_VIRTUAL_REGISTER));
})
;; Return false if this is any eliminable register. Otherwise general_operand.
(define_predicate "general_no_elim_operand"
(if_then_else (match_code "reg,subreg")
(match_operand 0 "register_no_elim_operand")
(match_operand 0 "general_operand")))
;; Return false if this is any eliminable register. Otherwise
;; register_operand or a constant.
(define_predicate "nonmemory_no_elim_operand"
(ior (match_operand 0 "register_no_elim_operand")
(match_operand 0 "immediate_operand")))
;; Test for a valid operand for a call instruction.
(define_predicate "call_insn_operand"
(ior (match_operand 0 "constant_call_address_operand")
(ior (match_operand 0 "register_no_elim_operand")
(match_operand 0 "memory_operand"))))
;; Simiarly, but for tail calls, in which we cannot allow memory references.
(define_predicate "sibcall_insn_operand"
(ior (match_operand 0 "constant_call_address_operand")
(match_operand 0 "register_no_elim_operand")))
;; Match exactly zero.
(define_predicate "const0_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST0_RTX (mode)")))
;; Match exactly one.
(define_predicate "const1_operand"
(and (match_code "const_int")
(match_test "op == const1_rtx")))
;; Match 2, 4, or 8. Used for leal multiplicands.
(define_predicate "const248_operand"
(match_code "const_int")
{
HOST_WIDE_INT i = INTVAL (op);
return i == 2 || i == 4 || i == 8;
})
;; Match 0 to 3.
(define_predicate "const_0_to_3_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 3")))
;; Match 0 to 7.
(define_predicate "const_0_to_7_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
;; Match 0 to 15.
(define_predicate "const_0_to_15_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
;; Match 0 to 255.
(define_predicate "const_0_to_255_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 255")))
;; True if this is a constant appropriate for an increment or decrement.
(define_predicate "incdec_operand"
(match_code "const_int")
{
/* On Pentium4, the inc and dec operations causes extra dependency on flag
registers, since carry flag is not set. */
if ((TARGET_PENTIUM4 || TARGET_NOCONA) && !optimize_size)
return 0;
return op == const1_rtx || op == constm1_rtx;
})
;; True if OP is acceptable as operand of DImode shift expander.
(define_predicate "shiftdi_operand"
(if_then_else (match_test "TARGET_64BIT")
(match_operand 0 "nonimmediate_operand")
(match_operand 0 "register_operand")))
;; Return true if OP is a vector load from the constant pool with just
;; the first element non-zero.
(define_predicate "zero_extended_scalar_load_operand"
(match_code "mem")
{
unsigned n_elts;
op = maybe_get_pool_constant (op);
if (!op)
return 0;
if (GET_CODE (op) != CONST_VECTOR)
return 0;
n_elts =
(GET_MODE_SIZE (GET_MODE (op)) /
GET_MODE_SIZE (GET_MODE_INNER (GET_MODE (op))));
for (n_elts--; n_elts > 0; n_elts--)
{
rtx elt = CONST_VECTOR_ELT (op, n_elts);
if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
return 0;
}
return 1;
})
;; Return 1 when OP is operand acceptable for standard SSE move.
(define_predicate "vector_move_operand"
(ior (match_operand 0 "nonimmediate_operand")
(match_operand 0 "const0_operand")))
;; Return true if op if a valid address, and does not contain
;; a segment override.
(define_special_predicate "no_seg_address_operand"
(match_operand 0 "address_operand")
{
struct ix86_address parts;
if (! ix86_decompose_address (op, &parts))
abort ();
return parts.seg == SEG_DEFAULT;
})
;; Return nonzero if the rtx is known aligned.
(define_predicate "aligned_operand"
(match_operand 0 "general_operand")
{
struct ix86_address parts;
/* Registers and immediate operands are always "aligned". */
if (GET_CODE (op) != MEM)
return 1;
/* Don't even try to do any aligned optimizations with volatiles. */
if (MEM_VOLATILE_P (op))
return 0;
op = XEXP (op, 0);
/* Pushes and pops are only valid on the stack pointer. */
if (GET_CODE (op) == PRE_DEC
|| GET_CODE (op) == POST_INC)
return 1;
/* Decode the address. */
if (!ix86_decompose_address (op, &parts))
abort ();
/* Look for some component that isn't known to be aligned. */
if (parts.index)
{
if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
return 0;
}
if (parts.base)
{
if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
return 0;
}
if (parts.disp)
{
if (GET_CODE (parts.disp) != CONST_INT
|| (INTVAL (parts.disp) & 3) != 0)
return 0;
}
/* Didn't find one -- this must be an aligned address. */
return 1;
})
;; Returns 1 if OP is memory operand with a displacement.
(define_predicate "memory_displacement_operand"
(match_operand 0 "memory_operand")
{
struct ix86_address parts;
if (!ix86_decompose_address (XEXP (op, 0), &parts))
abort ();
return parts.disp != NULL_RTX;
})
;; Returns 1 if OP is memory operand that can not be represented
;; by the modRM array.
(define_predicate "long_memory_operand"
(and (match_operand 0 "memory_operand")
(match_test "memory_address_length (op) != 0")))
;; Return 1 if OP is a comparison operator that can be issued by fcmov.
(define_predicate "fcmov_comparison_operator"
(match_operand 0 "comparison_operator")
{
enum machine_mode inmode = GET_MODE (XEXP (op, 0));
enum rtx_code code = GET_CODE (op);
if (inmode == CCFPmode || inmode == CCFPUmode)
{
enum rtx_code second_code, bypass_code;
ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
if (bypass_code != NIL || second_code != NIL)
return 0;
code = ix86_fp_compare_code_to_integer (code);
}
/* i387 supports just limited amount of conditional codes. */
switch (code)
{
case LTU: case GTU: case LEU: case GEU:
if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode)
return 1;
return 0;
case ORDERED: case UNORDERED:
case EQ: case NE:
return 1;
default:
return 0;
}
})
;; Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS insns.
;; The first set are supported directly; the second set can't be done with
;; full IEEE support, i.e. NaNs.
;;
;; ??? It would seem that we have a lot of uses of this predicate that pass
;; it the wrong mode. We got away with this because the old function didn't
;; check the mode at all. Mirror that for now by calling this a special
;; predicate.
(define_special_predicate "sse_comparison_operator"
(ior (match_code "eq,lt,le,unordered,ne,unge,ungt,ordered")
(and (match_code "uneq,unlt,unle,ltgt,ge,gt")
(match_code "!TARGET_IEEE_FP"))))
;; Return 1 if OP is a valid comparison operator in valid mode.
(define_predicate "ix86_comparison_operator"
(match_operand 0 "comparison_operator")
{
enum machine_mode inmode = GET_MODE (XEXP (op, 0));
enum rtx_code code = GET_CODE (op);
if (inmode == CCFPmode || inmode == CCFPUmode)
{
enum rtx_code second_code, bypass_code;
ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
return (bypass_code == NIL && second_code == NIL);
}
switch (code)
{
case EQ: case NE:
return 1;
case LT: case GE:
if (inmode == CCmode || inmode == CCGCmode
|| inmode == CCGOCmode || inmode == CCNOmode)
return 1;
return 0;
case LTU: case GTU: case LEU: case ORDERED: case UNORDERED: case GEU:
if (inmode == CCmode)
return 1;
return 0;
case GT: case LE:
if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
return 1;
return 0;
default:
return 0;
}
})
;; Return 1 if OP is a valid comparison operator testing carry flag to be set.
(define_predicate "ix86_carry_flag_operator"
(match_code "ltu,lt,unlt,gt,ungt,le,unle,ge,unge,ltgt,uneq")
{
enum machine_mode inmode = GET_MODE (XEXP (op, 0));
enum rtx_code code = GET_CODE (op);
if (GET_CODE (XEXP (op, 0)) != REG
|| REGNO (XEXP (op, 0)) != FLAGS_REG
|| XEXP (op, 1) != const0_rtx)
return 0;
if (inmode == CCFPmode || inmode == CCFPUmode)
{
enum rtx_code second_code, bypass_code;
ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
if (bypass_code != NIL || second_code != NIL)
return 0;
code = ix86_fp_compare_code_to_integer (code);
}
else if (inmode != CCmode)
return 0;
return code == LTU;
})
;; Nearly general operand, but accept any const_double, since we wish
;; to be able to drop them into memory rather than have them get pulled
;; into registers.
(define_predicate "cmp_fp_expander_operand"
(ior (match_code "const_double")
(match_operand 0 "general_operand")))
;; Return true if this is a valid binary floating-point operation.
(define_predicate "binary_fp_operator"
(match_code "plus,minus,mult,div"))
;; Return true if this is a multiply operation.
(define_predicate "mult_operator"
(match_code "mult"))
;; Return true if this is a division operation.
(define_predicate "div_operator"
(match_code "div"))
;; Return true for ARITHMETIC_P.
(define_predicate "arith_or_logical_operator"
(match_code "PLUS,MULT,AND,IOR,XOR,SMIN,SMAX,UMIN,UMAX,COMPARE,MINUS,DIV,
MOD,UDIV,UMOD,ASHIFT,ROTATE,ASHIFTRT,LSHIFTRT,ROTATERT"))
;; Return 1 if OP is a binary operator that can be promoted to wider mode.
;; Modern CPUs have same latency for HImode and SImode multiply,
;; but 386 and 486 do HImode multiply faster. */
(define_predicate "promotable_binary_operator"
(ior (match_code "plus,and,ior,xor,ashift")
(and (match_code "mult")
(match_test "ix86_tune > PROCESSOR_I486"))))
;; To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0,
;; re-recognize the operand to avoid a copy_to_mode_reg that will fail.
;;
;; ??? It seems likely that this will only work because cmpsi is an
;; expander, and no actual insns use this.
(define_predicate "cmpsi_operand_1"
(match_code "and")
{
return (GET_MODE (op) == SImode
&& GET_CODE (XEXP (op, 0)) == ZERO_EXTRACT
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
&& GET_CODE (XEXP (XEXP (op, 0), 2)) == CONST_INT
&& INTVAL (XEXP (XEXP (op, 0), 1)) == 8
&& INTVAL (XEXP (XEXP (op, 0), 2)) == 8
&& GET_CODE (XEXP (op, 1)) == CONST_INT);
})
(define_predicate "cmpsi_operand"
(ior (match_operand 0 "nonimmediate_operand")
(match_operand 0 "cmpsi_operand_1")))
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