Skip to content

R
riscv-gcc-1
Commit 8ee41eaf by Richard Henderson Committed by Richard Henderson
Options

i386.md: Use define_constants for unspec numbers. 

        * config/i386/i386.md: Use define_constants for unspec numbers.
        * config/i386/i386.c: Likewise.

From-SVN: r53448
parent 3b7dcffa
Showing with 259 additions and 193 deletions
gcc/ChangeLog
2002-05-14 Richard Henderson <rth@redhat.com>
* config/i386/i386.md: Use define_constants for unspec numbers.
* config/i386/i386.c: Likewise.
2002-05-13 Mark Mitchell <mark@codesourcery.com> 2002-05-13 Mark Mitchell <mark@codesourcery.com>
* fixinc/inclhack.def (winidss_valist): Limit applicability. * fixinc/inclhack.def (winidss_valist): Limit applicability.
......
gcc/config/i386/i386.c
...@@ -2885,9 +2885,9 @@ symbolic_operand (op, mode) ...@@ -2885,9 +2885,9 @@ symbolic_operand (op, mode)
if (GET_CODE (op) == SYMBOL_REF if (GET_CODE (op) == SYMBOL_REF
|| GET_CODE (op) == LABEL_REF || GET_CODE (op) == LABEL_REF
|| (GET_CODE (op) == UNSPEC || (GET_CODE (op) == UNSPEC
&& (XINT (op, 1) == 6 && (XINT (op, 1) == UNSPEC_GOT
|| XINT (op, 1) == 7 || XINT (op, 1) == UNSPEC_GOTOFF
|| XINT (op, 1) == 15))) || XINT (op, 1) == UNSPEC_GOTPCREL)))
return 1; return 1;
if (GET_CODE (op) != PLUS if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 1)) != CONST_INT) || GET_CODE (XEXP (op, 1)) != CONST_INT)
...@@ -2899,7 +2899,7 @@ symbolic_operand (op, mode) ...@@ -2899,7 +2899,7 @@ symbolic_operand (op, mode)
return 1; return 1;
/* Only @GOTOFF gets offsets. */ /* Only @GOTOFF gets offsets. */
if (GET_CODE (op) != UNSPEC if (GET_CODE (op) != UNSPEC
|| XINT (op, 1) != 7) || XINT (op, 1) != UNSPEC_GOTOFF)
return 0; return 0;
op = XVECEXP (op, 0, 0); op = XVECEXP (op, 0, 0);
...@@ -3649,8 +3649,7 @@ x86_64_sign_extended_value (value) ...@@ -3649,8 +3649,7 @@ x86_64_sign_extended_value (value)
cases. */ cases. */
case CONST: case CONST:
if (GET_CODE (XEXP (value, 0)) == UNSPEC if (GET_CODE (XEXP (value, 0)) == UNSPEC
&& XVECLEN (XEXP (value, 0), 0) == 1 && XINT (XEXP (value, 0), 1) == UNSPEC_GOTPCREL)
&& XINT (XEXP (value, 0), 1) == 15)
return 1; return 1;
else if (GET_CODE (XEXP (value, 0)) == PLUS) else if (GET_CODE (XEXP (value, 0)) == PLUS)
{ {
...@@ -4629,8 +4628,7 @@ ix86_find_base_term (x) ...@@ -4629,8 +4628,7 @@ ix86_find_base_term (x)
|| GET_CODE (XEXP (term, 1)) == CONST_DOUBLE)) || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
term = XEXP (term, 0); term = XEXP (term, 0);
if (GET_CODE (term) != UNSPEC if (GET_CODE (term) != UNSPEC
|| XVECLEN (term, 0) != 1 || XINT (term, 1) != UNSPEC_GOTPCREL)
|| XINT (term, 1) != 15)
return x; return x;
term = XVECEXP (term, 0, 0); term = XVECEXP (term, 0, 0);
...@@ -4653,8 +4651,7 @@ ix86_find_base_term (x) ...@@ -4653,8 +4651,7 @@ ix86_find_base_term (x)
term = XEXP (term, 0); term = XEXP (term, 0);
if (GET_CODE (term) != UNSPEC if (GET_CODE (term) != UNSPEC
|| XVECLEN (term, 0) != 1 || XINT (term, 1) != UNSPEC_GOTOFF)
|| XINT (term, 1) != 7)
return x; return x;
term = XVECEXP (term, 0, 0); term = XVECEXP (term, 0, 0);
...@@ -4699,8 +4696,7 @@ legitimate_pic_address_disp_p (disp) ...@@ -4699,8 +4696,7 @@ legitimate_pic_address_disp_p (disp)
/* We are unsafe to allow PLUS expressions. This limit allowed distance /* We are unsafe to allow PLUS expressions. This limit allowed distance
of GOT tables. We should not need these anyway. */ of GOT tables. We should not need these anyway. */
if (GET_CODE (disp) != UNSPEC if (GET_CODE (disp) != UNSPEC
|| XVECLEN (disp, 0) != 1 || XINT (disp, 1) != UNSPEC_GOTPCREL)
|| XINT (disp, 1) != 15)
return 0; return 0;
if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
...@@ -4716,17 +4712,15 @@ legitimate_pic_address_disp_p (disp) ...@@ -4716,17 +4712,15 @@ legitimate_pic_address_disp_p (disp)
disp = XEXP (disp, 0); disp = XEXP (disp, 0);
} }
if (GET_CODE (disp) != UNSPEC if (GET_CODE (disp) != UNSPEC)
|| XVECLEN (disp, 0) != 1)
return 0; return 0;
/* Must be @GOT or @GOTOFF. */ /* Must be @GOT or @GOTOFF. */
switch (XINT (disp, 1)) switch (XINT (disp, 1))
{ {
case 6: /* @GOT */ case UNSPEC_GOT:
return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF; return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
case UNSPEC_GOTOFF:
case 7: /* @GOTOFF */
return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode); return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
} }
...@@ -4998,7 +4992,7 @@ legitimize_pic_address (orig, reg) ...@@ -4998,7 +4992,7 @@ legitimize_pic_address (orig, reg)
base address (@GOTOFF). */ base address (@GOTOFF). */
current_function_uses_pic_offset_table = 1; current_function_uses_pic_offset_table = 1;
new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 7); new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
new = gen_rtx_CONST (Pmode, new); new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
...@@ -5014,7 +5008,7 @@ legitimize_pic_address (orig, reg) ...@@ -5014,7 +5008,7 @@ legitimize_pic_address (orig, reg)
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
current_function_uses_pic_offset_table = 1; current_function_uses_pic_offset_table = 1;
new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 15); new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
new = gen_rtx_CONST (Pmode, new); new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_MEM (Pmode, new); new = gen_rtx_MEM (Pmode, new);
RTX_UNCHANGING_P (new) = 1; RTX_UNCHANGING_P (new) = 1;
...@@ -5034,7 +5028,7 @@ legitimize_pic_address (orig, reg) ...@@ -5034,7 +5028,7 @@ legitimize_pic_address (orig, reg)
Global Offset Table (@GOT). */ Global Offset Table (@GOT). */
current_function_uses_pic_offset_table = 1; current_function_uses_pic_offset_table = 1;
new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 6); new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
new = gen_rtx_CONST (Pmode, new); new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
new = gen_rtx_MEM (Pmode, new); new = gen_rtx_MEM (Pmode, new);
...@@ -5075,7 +5069,8 @@ legitimize_pic_address (orig, reg) ...@@ -5075,7 +5069,8 @@ legitimize_pic_address (orig, reg)
if (!TARGET_64BIT) if (!TARGET_64BIT)
{ {
current_function_uses_pic_offset_table = 1; current_function_uses_pic_offset_table = 1;
new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), 7); new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
UNSPEC_GOTOFF);
new = gen_rtx_PLUS (Pmode, new, op1); new = gen_rtx_PLUS (Pmode, new, op1);
new = gen_rtx_CONST (Pmode, new); new = gen_rtx_CONST (Pmode, new);
new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
...@@ -5394,16 +5389,16 @@ output_pic_addr_const (file, x, code) ...@@ -5394,16 +5389,16 @@ output_pic_addr_const (file, x, code)
output_pic_addr_const (file, XVECEXP (x, 0, 0), code); output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
switch (XINT (x, 1)) switch (XINT (x, 1))
{ {
case 6: case UNSPEC_GOT:
fputs ("@GOT", file); fputs ("@GOT", file);
break; break;
case 7: case UNSPEC_GOTOFF:
fputs ("@GOTOFF", file); fputs ("@GOTOFF", file);
break; break;
case 8: case UNSPEC_PLT:
fputs ("@PLT", file); fputs ("@PLT", file);
break; break;
case 15: case UNSPEC_GOTPCREL:
fputs ("@GOTPCREL(%RIP)", file); fputs ("@GOTPCREL(%RIP)", file);
break; break;
default: default:
...@@ -5456,7 +5451,7 @@ i386_simplify_dwarf_addr (orig_x) ...@@ -5456,7 +5451,7 @@ i386_simplify_dwarf_addr (orig_x)
{ {
if (GET_CODE (x) != CONST if (GET_CODE (x) != CONST
|| GET_CODE (XEXP (x, 0)) != UNSPEC || GET_CODE (XEXP (x, 0)) != UNSPEC
|| XINT (XEXP (x, 0), 1) != 15 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
|| GET_CODE (orig_x) != MEM) || GET_CODE (orig_x) != MEM)
return orig_x; return orig_x;
return XVECEXP (XEXP (x, 0), 0, 0); return XVECEXP (XEXP (x, 0), 0, 0);
...@@ -5492,8 +5487,8 @@ i386_simplify_dwarf_addr (orig_x) ...@@ -5492,8 +5487,8 @@ i386_simplify_dwarf_addr (orig_x)
x = XEXP (XEXP (x, 1), 0); x = XEXP (XEXP (x, 1), 0);
if (GET_CODE (x) == UNSPEC if (GET_CODE (x) == UNSPEC
&& ((XINT (x, 1) == 6 && GET_CODE (orig_x) == MEM) && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
|| (XINT (x, 1) == 7 && GET_CODE (orig_x) != MEM))) || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
{ {
if (y) if (y)
return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0)); return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
...@@ -5503,8 +5498,9 @@ i386_simplify_dwarf_addr (orig_x) ...@@ -5503,8 +5498,9 @@ i386_simplify_dwarf_addr (orig_x)
if (GET_CODE (x) == PLUS if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == UNSPEC && GET_CODE (XEXP (x, 0)) == UNSPEC
&& GET_CODE (XEXP (x, 1)) == CONST_INT && GET_CODE (XEXP (x, 1)) == CONST_INT
&& ((XINT (XEXP (x, 0), 1) == 6 && GET_CODE (orig_x) == MEM) && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
|| (XINT (XEXP (x, 0), 1) == 7 && GET_CODE (orig_x) != MEM))) || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
&& GET_CODE (orig_x) != MEM)))
{ {
x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1)); x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
if (y) if (y)
...@@ -7492,7 +7488,7 @@ ix86_expand_fp_compare (code, op0, op1, scratch, second_test, bypass_test) ...@@ -7492,7 +7488,7 @@ ix86_expand_fp_compare (code, op0, op1, scratch, second_test, bypass_test)
else else
{ {
tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1); tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9); tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
if (!scratch) if (!scratch)
scratch = gen_reg_rtx (HImode); scratch = gen_reg_rtx (HImode);
emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2)); emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
...@@ -7515,7 +7511,7 @@ ix86_expand_fp_compare (code, op0, op1, scratch, second_test, bypass_test) ...@@ -7515,7 +7511,7 @@ ix86_expand_fp_compare (code, op0, op1, scratch, second_test, bypass_test)
{ {
/* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */ /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1); tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9); tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
if (!scratch) if (!scratch)
scratch = gen_reg_rtx (HImode); scratch = gen_reg_rtx (HImode);
emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2)); emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
......
gcc/config/i386/i386.md
...@@ -49,62 +49,63 @@ ...@@ -49,62 +49,63 @@
;; 'k' Likewise, print the SImode name of the register. ;; 'k' Likewise, print the SImode name of the register.
;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
;; 'y' Print "st(0)" instead of "st" as a register. ;; 'y' Print "st(0)" instead of "st" as a register.
;;
;; UNSPEC usage: ;; UNSPEC usage:
;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
;; operand 0 is the memory address to scan. (define_constants
;; operand 1 is a register containing the value to scan for. The mode [(UNSPEC_SCAS 0)
;; of the scas opcode will be the same as the mode of this operand. (UNSPEC_SIN 1)
;; operand 2 is the known alignment of operand 0. (UNSPEC_COS 2)
;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT. (UNSPEC_STACK_PROBE 3)
;; operand 0 is the argument for `sin'. (UNSPEC_STACK_ALLOC 4)
;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT. (UNSPEC_BSF 5)
;; operand 0 is the argument for `cos'. (UNSPEC_GOT 6)
;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is (UNSPEC_GOTOFF 7)
;; always SImode. operand 0 is the size of the stack allocation. (UNSPEC_PLT 8)
;; 4 This is the source of a fake SET of the frame pointer which is used to (UNSPEC_FNSTSW 9)
;; prevent insns referencing it being scheduled across the initial (UNSPEC_SAHF 10)
;; decrement of the stack pointer. (UNSPEC_FSTCW 11)
;; 5 This is a `bsf' operation. (UNSPEC_ADD_CARRY 12)
;; 6 This is the @GOT offset of a PIC address. (UNSPEC_SSE_PROLOGUE_SAVE 13)
;; 7 This is the @GOTOFF offset of a PIC address. (UNSPEC_FLDCW 14)
;; 8 This is a reference to a symbol's @PLT address. (UNSPEC_GOTPCREL 15)
;; 9 This is an `fnstsw' operation.
;; 10 This is a `sahf' operation. ; For SSE/MMX support:
;; 11 This is a `fstcw' operation (UNSPEC_FIX 30)
;; 12 This is behaviour of add when setting carry flag. (UNSPEC_MASKMOV 32)
;; 13 This is a `eh_return' placeholder. (UNSPEC_MOVMSK 33)
(UNSPEC_MOVNT 34)
;; For SSE/MMX support: (UNSPEC_MOVA 38)
;; 30 This is `fix', guaranteed to be truncating. (UNSPEC_MOVU 39)
;; 31 This is a `emms' operation. (UNSPEC_SHUFFLE 41)
;; 32 This is a `maskmov' operation. (UNSPEC_RCP 42)
;; 33 This is a `movmsk' operation. (UNSPEC_RSQRT 43)
;; 34 This is a `non-temporal' move. (UNSPEC_SFENCE 44)
;; 36 This is used to distinguish COMISS from UCOMISS. (UNSPEC_NOP 45) ; prevents combiner cleverness
;; 37 This is a `ldmxcsr' operation. (UNSPEC_PAVGUSB 49)
;; 38 This is a forced `movaps' instruction (rather than whatever movti does) (UNSPEC_PFRCP 50)
;; 39 This is a forced `movups' instruction (rather than whatever movti does) (UNSPEC_PFRCPIT1 51)
;; 40 This is a `stmxcsr' operation. (UNSPEC_PFRCPIT2 52)
;; 41 This is a `shuffle' operation. (UNSPEC_PFRSQRT 53)
;; 42 This is a `rcp' operation. (UNSPEC_PFRSQIT1 54)
;; 43 This is a `rsqsrt' operation. (UNSPEC_PSHUFLW 55)
;; 44 This is a `sfence' operation. (UNSPEC_PSHUFHW 56)
;; 45 This is a noop to prevent excessive combiner cleverness. (UNSPEC_MFENCE 59)
;; 46 This is a `femms' operation. (UNSPEC_LFENCE 60)
;; 49 This is a 'pavgusb' operation. (UNSPEC_PSADBW 61)
;; 50 This is a `pfrcp' operation. ])
;; 51 This is a `pfrcpit1' operation.
;; 52 This is a `pfrcpit2' operation. (define_constants
;; 53 This is a `pfrsqrt' operation. [(UNSPECV_BLOCKAGE 0)
;; 54 This is a `pfrsqrit1' operation. (UNSPECV_PROLOGUE_SET_GOT 1)
;; 55 This is a `pshuflw' operation. (UNSPECV_PROLOGUE_GET_PC 2)
;; 56 This is a `pshufhw' operation. (UNSPECV_EH_RETURN 13)
;; 57 This is a `clflush' operation. (UNSPECV_EMMS 31)
;; 58 This is a `sfence' operation. (UNSPECV_LDMXCSR 37)
;; 59 This is a `mfence' operation. (UNSPECV_STMXCSR 40)
;; 60 This is a `lfence' operation. (UNSPECV_FEMMS 46)
;; 61 This is a `psadbw' operation. (UNSPECV_CLFLUSH 57)
])
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; from i386.c. ;; from i386.c.
...@@ -722,7 +723,8 @@ ...@@ -722,7 +723,8 @@
[(set (match_operand:HI 0 "register_operand" "=a") [(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI (unspec:HI
[(compare:CCFP (match_operand 1 "register_operand" "f") [(compare:CCFP (match_operand 1 "register_operand" "f")
(match_operand 2 "const0_operand" "X"))] 9))] (match_operand 2 "const0_operand" "X"))]
UNSPEC_FNSTSW))]
"TARGET_80387 "TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1])) && FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])" && GET_MODE (operands[1]) == GET_MODE (operands[2])"
...@@ -753,7 +755,8 @@ ...@@ -753,7 +755,8 @@
(unspec:HI (unspec:HI
[(compare:CCFP [(compare:CCFP
(match_operand:SF 1 "register_operand" "f") (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))] (match_operand:SF 2 "nonimmediate_operand" "fm"))]
UNSPEC_FNSTSW))]
"TARGET_80387" "TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);" "* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "fcmp") [(set_attr "type" "fcmp")
...@@ -774,7 +777,8 @@ ...@@ -774,7 +777,8 @@
(unspec:HI (unspec:HI
[(compare:CCFP [(compare:CCFP
(match_operand:DF 1 "register_operand" "f") (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))] (match_operand:DF 2 "nonimmediate_operand" "fm"))]
UNSPEC_FNSTSW))]
"TARGET_80387" "TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);" "* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -805,7 +809,8 @@ ...@@ -805,7 +809,8 @@
(unspec:HI (unspec:HI
[(compare:CCFP [(compare:CCFP
(match_operand:XF 1 "register_operand" "f") (match_operand:XF 1 "register_operand" "f")
(match_operand:XF 2 "register_operand" "f"))] 9))] (match_operand:XF 2 "register_operand" "f"))]
UNSPEC_FNSTSW))]
"!TARGET_64BIT && TARGET_80387" "!TARGET_64BIT && TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);" "* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -816,7 +821,8 @@ ...@@ -816,7 +821,8 @@
(unspec:HI (unspec:HI
[(compare:CCFP [(compare:CCFP
(match_operand:TF 1 "register_operand" "f") (match_operand:TF 1 "register_operand" "f")
(match_operand:TF 2 "register_operand" "f"))] 9))] (match_operand:TF 2 "register_operand" "f"))]
UNSPEC_FNSTSW))]
"TARGET_80387" "TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);" "* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -839,7 +845,8 @@ ...@@ -839,7 +845,8 @@
(unspec:HI (unspec:HI
[(compare:CCFPU [(compare:CCFPU
(match_operand 1 "register_operand" "f") (match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f"))] 9))] (match_operand 2 "register_operand" "f"))]
UNSPEC_FNSTSW))]
"TARGET_80387 "TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1])) && FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])" && GET_MODE (operands[1]) == GET_MODE (operands[2])"
...@@ -887,7 +894,7 @@ ...@@ -887,7 +894,7 @@
(define_insn "x86_fnstsw_1" (define_insn "x86_fnstsw_1"
[(set (match_operand:HI 0 "register_operand" "=a") [(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI [(reg 18)] 9))] (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
"TARGET_80387" "TARGET_80387"
"fnstsw\t%0" "fnstsw\t%0"
[(set_attr "length" "2") [(set_attr "length" "2")
...@@ -900,7 +907,7 @@ ...@@ -900,7 +907,7 @@
(define_insn "x86_sahf_1" (define_insn "x86_sahf_1"
[(set (reg:CC 17) [(set (reg:CC 17)
(unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))] (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
"!TARGET_64BIT" "!TARGET_64BIT"
"sahf" "sahf"
[(set_attr "length" "1") [(set_attr "length" "1")
...@@ -4395,7 +4402,7 @@ ...@@ -4395,7 +4402,7 @@
;; %% Not used yet. ;; %% Not used yet.
(define_insn "x86_fnstcw_1" (define_insn "x86_fnstcw_1"
[(set (match_operand:HI 0 "memory_operand" "=m") [(set (match_operand:HI 0 "memory_operand" "=m")
(unspec:HI [(reg:HI 18)] 11))] (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
"TARGET_80387" "TARGET_80387"
"fnstcw\t%0" "fnstcw\t%0"
[(set_attr "length" "2") [(set_attr "length" "2")
...@@ -4405,7 +4412,7 @@ ...@@ -4405,7 +4412,7 @@
(define_insn "x86_fldcw_1" (define_insn "x86_fldcw_1"
[(set (reg:HI 18) [(set (reg:HI 18)
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))] (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387" "TARGET_80387"
"fldcw\t%0" "fldcw\t%0"
[(set_attr "length" "2") [(set_attr "length" "2")
...@@ -4681,7 +4688,8 @@ ...@@ -4681,7 +4688,8 @@
(match_operand:DI 2 "general_operand" ""))) (match_operand:DI 2 "general_operand" "")))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"!TARGET_64BIT && reload_completed" "!TARGET_64BIT && reload_completed"
[(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12)) [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
UNSPEC_ADD_CARRY))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
(plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
...@@ -4706,8 +4714,10 @@ ...@@ -4706,8 +4714,10 @@
(set_attr "ppro_uops" "few")]) (set_attr "ppro_uops" "few")])
(define_insn "*adddi3_cc_rex64" (define_insn "*adddi3_cc_rex64"
[(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0") [(set (reg:CC 17)
(match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12)) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rm")]
UNSPEC_ADD_CARRY))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(plus:DI (match_dup 1) (match_dup 2)))] (plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
...@@ -4743,8 +4753,10 @@ ...@@ -4743,8 +4753,10 @@
(set_attr "ppro_uops" "few")]) (set_attr "ppro_uops" "few")])
(define_insn "*addsi3_cc" (define_insn "*addsi3_cc"
[(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") [(set (reg:CC 17)
(match_operand:SI 2 "general_operand" "ri,rm")] 12)) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "ri,rm")]
UNSPEC_ADD_CARRY))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, SImode, operands)" "ix86_binary_operator_ok (PLUS, SImode, operands)"
...@@ -4753,8 +4765,10 @@ ...@@ -4753,8 +4765,10 @@
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "addqi3_cc" (define_insn "addqi3_cc"
[(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") [(set (reg:CC 17)
(match_operand:QI 2 "general_operand" "qi,qm")] 12)) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
(match_operand:QI 2 "general_operand" "qi,qm")]
UNSPEC_ADD_CARRY))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(plus:QI (match_dup 1) (match_dup 2)))] (plus:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, QImode, operands)" "ix86_binary_operator_ok (PLUS, QImode, operands)"
...@@ -13124,7 +13138,7 @@ ...@@ -13124,7 +13138,7 @@
;; all of memory. This blocks insns from being moved across this point. ;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage" (define_insn "blockage"
[(unspec_volatile [(const_int 0)] 0)] [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
"" ""
"" ""
[(set_attr "length" "0")]) [(set_attr "length" "0")])
...@@ -13189,7 +13203,8 @@ ...@@ -13189,7 +13203,8 @@
(unspec_volatile:SI (unspec_volatile:SI
[(plus:SI (match_dup 0) [(plus:SI (match_dup 0)
(plus:SI (match_operand:SI 1 "symbolic_operand" "") (plus:SI (match_operand:SI 1 "symbolic_operand" "")
(minus:SI (pc) (match_operand 2 "" ""))))] 1)) (minus:SI (pc) (match_operand 2 "" ""))))]
UNSPECV_PROLOGUE_SET_GOT))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"!TARGET_64BIT" "!TARGET_64BIT"
{ {
...@@ -13208,7 +13223,8 @@ ...@@ -13208,7 +13223,8 @@
(define_insn "prologue_get_pc" (define_insn "prologue_get_pc"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))] (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))]
UNSPECV_PROLOGUE_GET_PC))]
"!TARGET_64BIT" "!TARGET_64BIT"
{ {
if (GET_CODE (operands[1]) == LABEL_REF) if (GET_CODE (operands[1]) == LABEL_REF)
...@@ -13257,7 +13273,8 @@ ...@@ -13257,7 +13273,8 @@
}) })
(define_insn_and_split "eh_return_si" (define_insn_and_split "eh_return_si"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)] [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
UNSPECV_EH_RETURN)]
"!TARGET_64BIT" "!TARGET_64BIT"
"#" "#"
"reload_completed" "reload_completed"
...@@ -13265,7 +13282,8 @@ ...@@ -13265,7 +13282,8 @@
"ix86_expand_epilogue (2); DONE;") "ix86_expand_epilogue (2); DONE;")
(define_insn_and_split "eh_return_di" (define_insn_and_split "eh_return_di"
[(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)] [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
UNSPECV_EH_RETURN)]
"TARGET_64BIT" "TARGET_64BIT"
"#" "#"
"reload_completed" "reload_completed"
...@@ -13389,7 +13407,7 @@ ...@@ -13389,7 +13407,7 @@
(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r") (set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_dup 1)] 5))] (unspec:SI [(match_dup 1)] UNSPEC_BSF))]
"" ""
"bsf{l}\t{%1, %0|%0, %1}" "bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1") [(set_attr "prefix_0f" "1")
...@@ -14197,7 +14215,7 @@ ...@@ -14197,7 +14215,7 @@
(define_insn "sindf2" (define_insn "sindf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
...@@ -14206,7 +14224,7 @@ ...@@ -14206,7 +14224,7 @@
(define_insn "sinsf2" (define_insn "sinsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
...@@ -14216,7 +14234,8 @@ ...@@ -14216,7 +14234,8 @@
(define_insn "*sinextendsfdf2" (define_insn "*sinextendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(float_extend:DF (unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))] 1))] (match_operand:SF 1 "register_operand" "0"))]
UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
...@@ -14225,7 +14244,7 @@ ...@@ -14225,7 +14244,7 @@
(define_insn "sinxf2" (define_insn "sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
"!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
...@@ -14234,7 +14253,7 @@ ...@@ -14234,7 +14253,7 @@
(define_insn "sintf2" (define_insn "sintf2"
[(set (match_operand:TF 0 "register_operand" "=f") [(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))] (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
...@@ -14243,7 +14262,7 @@ ...@@ -14243,7 +14262,7 @@
(define_insn "cosdf2" (define_insn "cosdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
...@@ -14252,7 +14271,7 @@ ...@@ -14252,7 +14271,7 @@
(define_insn "cossf2" (define_insn "cossf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
...@@ -14262,7 +14281,8 @@ ...@@ -14262,7 +14281,8 @@
(define_insn "*cosextendsfdf2" (define_insn "*cosextendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(float_extend:DF (unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))] 2))] (match_operand:SF 1 "register_operand" "0"))]
UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
...@@ -14271,7 +14291,7 @@ ...@@ -14271,7 +14291,7 @@
(define_insn "cosxf2" (define_insn "cosxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))] (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
...@@ -14280,7 +14300,7 @@ ...@@ -14280,7 +14300,7 @@
(define_insn "costf2" (define_insn "costf2"
[(set (match_operand:TF 0 "register_operand" "=f") [(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))] (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
...@@ -15174,7 +15194,7 @@ ...@@ -15174,7 +15194,7 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(unspec:SI [(match_operand:BLK 1 "general_operand" "") (unspec:SI [(match_operand:BLK 1 "general_operand" "")
(match_operand:QI 2 "immediate_operand" "") (match_operand:QI 2 "immediate_operand" "")
(match_operand 3 "immediate_operand" "")] 0))] (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
"" ""
{ {
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
...@@ -15187,7 +15207,7 @@ ...@@ -15187,7 +15207,7 @@
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(unspec:DI [(match_operand:BLK 1 "general_operand" "") (unspec:DI [(match_operand:BLK 1 "general_operand" "")
(match_operand:QI 2 "immediate_operand" "") (match_operand:QI 2 "immediate_operand" "")
(match_operand 3 "immediate_operand" "")] 0))] (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
"" ""
{ {
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
...@@ -15201,7 +15221,7 @@ ...@@ -15201,7 +15221,7 @@
(unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1")) (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
(match_operand:QI 2 "register_operand" "a") (match_operand:QI 2 "register_operand" "a")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(match_operand:SI 4 "register_operand" "0")] 0)) (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
(use (reg:SI 19)) (use (reg:SI 19))
(clobber (match_operand:SI 1 "register_operand" "=D")) (clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
...@@ -15216,7 +15236,7 @@ ...@@ -15216,7 +15236,7 @@
(unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1")) (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
(match_operand:QI 2 "register_operand" "a") (match_operand:QI 2 "register_operand" "a")
(match_operand:DI 3 "immediate_operand" "i") (match_operand:DI 3 "immediate_operand" "i")
(match_operand:DI 4 "register_operand" "0")] 0)) (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
(use (reg:SI 19)) (use (reg:SI 19))
(clobber (match_operand:DI 1 "register_operand" "=D")) (clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
...@@ -16223,7 +16243,7 @@ ...@@ -16223,7 +16243,7 @@
}) })
(define_insn "allocate_stack_worker_1" (define_insn "allocate_stack_worker_1"
[(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3) [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
(set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
(clobber (match_dup 0)) (clobber (match_dup 0))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
...@@ -16233,7 +16253,7 @@ ...@@ -16233,7 +16253,7 @@
(set_attr "length" "5")]) (set_attr "length" "5")])
(define_insn "allocate_stack_worker_rex64" (define_insn "allocate_stack_worker_rex64"
[(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3) [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
(set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0))) (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
(clobber (match_dup 0)) (clobber (match_dup 0))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
...@@ -17605,8 +17625,8 @@ ...@@ -17605,8 +17625,8 @@
;; movaps or movups ;; movaps or movups
(define_insn "sse_movaps" (define_insn "sse_movaps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
(unspec:V4SF (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
[(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 38))] UNSPEC_MOVA))]
"TARGET_SSE" "TARGET_SSE"
"@ "@
movaps\t{%1, %0|%0, %1} movaps\t{%1, %0|%0, %1}
...@@ -17616,8 +17636,8 @@ ...@@ -17616,8 +17636,8 @@
(define_insn "sse_movups" (define_insn "sse_movups"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
(unspec:V4SF (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
[(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 39))] UNSPEC_MOVU))]
"TARGET_SSE" "TARGET_SSE"
"@ "@
movups\t{%1, %0|%0, %1} movups\t{%1, %0|%0, %1}
...@@ -17630,7 +17650,8 @@ ...@@ -17630,7 +17650,8 @@
(define_insn "sse_movmskps" (define_insn "sse_movmskps"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))] (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
UNSPEC_MOVMSK))]
"TARGET_SSE" "TARGET_SSE"
"movmskps\t{%1, %0|%0, %1}" "movmskps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -17638,7 +17659,8 @@ ...@@ -17638,7 +17659,8 @@
(define_insn "mmx_pmovmskb" (define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))] (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
UNSPEC_MOVMSK))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
"pmovmskb\t{%1, %0|%0, %1}" "pmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -17648,7 +17670,8 @@ ...@@ -17648,7 +17670,8 @@
(define_insn "mmx_maskmovq" (define_insn "mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
(match_operand:V8QI 2 "register_operand" "y")] 32))] (match_operand:V8QI 2 "register_operand" "y")]
UNSPEC_MASKMOV))]
"(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax ;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}" "maskmovq\t{%2, %1|%1, %2}"
...@@ -17658,7 +17681,8 @@ ...@@ -17658,7 +17681,8 @@
(define_insn "mmx_maskmovq_rex" (define_insn "mmx_maskmovq_rex"
[(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
(match_operand:V8QI 2 "register_operand" "y")] 32))] (match_operand:V8QI 2 "register_operand" "y")]
UNSPEC_MASKMOV))]
"(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax ;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}" "maskmovq\t{%2, %1|%1, %2}"
...@@ -17667,7 +17691,8 @@ ...@@ -17667,7 +17691,8 @@
(define_insn "sse_movntv4sf" (define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m") [(set (match_operand:V4SF 0 "memory_operand" "=m")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))] (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
UNSPEC_MOVNT))]
"TARGET_SSE" "TARGET_SSE"
"movntps\t{%1, %0|%0, %1}" "movntps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov") [(set_attr "type" "ssemov")
...@@ -17675,7 +17700,8 @@ ...@@ -17675,7 +17700,8 @@
(define_insn "sse_movntdi" (define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m") [(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))] (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
UNSPEC_MOVNT))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
"movntq\t{%1, %0|%0, %1}" "movntq\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxmov") [(set_attr "type" "mmxmov")
...@@ -17771,7 +17797,8 @@ ...@@ -17771,7 +17797,8 @@
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm") (match_operand:V4SF 2 "nonimmediate_operand" "xm")
(match_operand:SI 3 "immediate_operand" "i")] 41))] (match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_SHUFFLE))]
"TARGET_SSE" "TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax ;; @@@ check operand order for intel/nonintel syntax
"shufps\t{%3, %2, %0|%0, %2, %3}" "shufps\t{%3, %2, %0|%0, %2, %3}"
...@@ -17871,7 +17898,7 @@ ...@@ -17871,7 +17898,7 @@
(define_insn "rcpv4sf2" (define_insn "rcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF (unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))] [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
"TARGET_SSE" "TARGET_SSE"
"rcpps\t{%1, %0|%0, %1}" "rcpps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse") [(set_attr "type" "sse")
...@@ -17880,7 +17907,8 @@ ...@@ -17880,7 +17907,8 @@
(define_insn "vmrcpv4sf2" (define_insn "vmrcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF (vec_merge:V4SF
(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42) (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_RCP)
(match_operand:V4SF 2 "register_operand" "0") (match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE" "TARGET_SSE"
...@@ -17891,7 +17919,7 @@ ...@@ -17891,7 +17919,7 @@
(define_insn "rsqrtv4sf2" (define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF (unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))] [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
"TARGET_SSE" "TARGET_SSE"
"rsqrtps\t{%1, %0|%0, %1}" "rsqrtps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse") [(set_attr "type" "sse")
...@@ -17900,7 +17928,8 @@ ...@@ -17900,7 +17928,8 @@
(define_insn "vmrsqrtv4sf2" (define_insn "vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF (vec_merge:V4SF
(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43) (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_RSQRT)
(match_operand:V4SF 2 "register_operand" "0") (match_operand:V4SF 2 "register_operand" "0")
(const_int 1)))] (const_int 1)))]
"TARGET_SSE" "TARGET_SSE"
...@@ -18177,7 +18206,7 @@ ...@@ -18177,7 +18206,7 @@
;; this insn. ;; this insn.
(define_insn "sse_clrv4sf" (define_insn "sse_clrv4sf"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF [(const_int 0)] 45))] (unspec:V4SF [(const_int 0)] UNSPEC_NOP))]
"TARGET_SSE" "TARGET_SSE"
"xorps\t{%0, %0|%0, %0}" "xorps\t{%0, %0|%0, %0}"
[(set_attr "type" "sselog") [(set_attr "type" "sselog")
...@@ -18386,7 +18415,8 @@ ...@@ -18386,7 +18415,8 @@
(define_insn "cvttps2pi" (define_insn "cvttps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y") [(set (match_operand:V2SI 0 "register_operand" "=y")
(vec_select:V2SI (vec_select:V2SI
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30) (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX)
(parallel [(const_int 0) (const_int 1)])))] (parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE" "TARGET_SSE"
"cvttps2pi\t{%1, %0|%0, %1}" "cvttps2pi\t{%1, %0|%0, %1}"
...@@ -18418,7 +18448,8 @@ ...@@ -18418,7 +18448,8 @@
(define_insn "cvttss2si" (define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(vec_select:SI (vec_select:SI
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30) (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX)
(parallel [(const_int 0)])))] (parallel [(const_int 0)])))]
"TARGET_SSE" "TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}" "cvttss2si\t{%1, %0|%0, %1}"
...@@ -18624,7 +18655,8 @@ ...@@ -18624,7 +18655,8 @@
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI (unspec:DI
[(ior:DI (match_operand:DI 1 "register_operand" "0") [(ior:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] (match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"por\t{%2, %0|%0, %2}" "por\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
...@@ -18634,7 +18666,8 @@ ...@@ -18634,7 +18666,8 @@
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI (unspec:DI
[(xor:DI (match_operand:DI 1 "register_operand" "0") [(xor:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] (match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"pxor\t{%2, %0|%0, %2}" "pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
...@@ -18645,7 +18678,7 @@ ...@@ -18645,7 +18678,7 @@
;; they are live. ;; they are live.
(define_insn "mmx_clrdi" (define_insn "mmx_clrdi"
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI [(const_int 0)] 45))] (unspec:DI [(const_int 0)] UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"pxor\t{%0, %0|%0, %0}" "pxor\t{%0, %0|%0, %0}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
...@@ -18656,7 +18689,8 @@ ...@@ -18656,7 +18689,8 @@
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI (unspec:DI
[(and:DI (match_operand:DI 1 "register_operand" "0") [(and:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] (match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"pand\t{%2, %0|%0, %2}" "pand\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
...@@ -18666,7 +18700,8 @@ ...@@ -18666,7 +18700,8 @@
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI (unspec:DI
[(and:DI (not:DI (match_operand:DI 1 "register_operand" "0")) [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] (match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"pandn\t{%2, %0|%0, %2}" "pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
...@@ -18714,7 +18749,8 @@ ...@@ -18714,7 +18749,8 @@
(define_insn "mmx_psadbw" (define_insn "mmx_psadbw"
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI [(match_operand:V8QI 1 "register_operand" "0") (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")] 61))] (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
UNSPEC_PSADBW))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
"psadbw\t{%2, %0|%0, %2}" "psadbw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft") [(set_attr "type" "mmxshft")
...@@ -18747,7 +18783,8 @@ ...@@ -18747,7 +18783,8 @@
(define_insn "mmx_pshufw" (define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y") [(set (match_operand:V4HI 0 "register_operand" "=y")
(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0") (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")] 41))] (match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_SHUFFLE))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%2, %1, %0|%0, %1, %2}" "pshufw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "mmxcvt") [(set_attr "type" "mmxcvt")
...@@ -18893,7 +18930,8 @@ ...@@ -18893,7 +18930,8 @@
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI (unspec:DI
[(lshiftrt:DI (match_operand:DI 1 "register_operand" "0") [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))] (match_operand:DI 2 "nonmemory_operand" "yi"))]
UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"psrlq\t{%2, %0|%0, %2}" "psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft") [(set_attr "type" "mmxshft")
...@@ -18922,7 +18960,8 @@ ...@@ -18922,7 +18960,8 @@
[(set (match_operand:DI 0 "register_operand" "=y") [(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI (unspec:DI
[(ashift:DI (match_operand:DI 1 "register_operand" "0") [(ashift:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))] (match_operand:DI 2 "nonmemory_operand" "yi"))]
UNSPEC_NOP))]
"TARGET_MMX" "TARGET_MMX"
"psllq\t{%2, %0|%0, %2}" "psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft") [(set_attr "type" "mmxshft")
...@@ -19087,7 +19126,7 @@ ...@@ -19087,7 +19126,7 @@
;; Miscellaneous stuff ;; Miscellaneous stuff
(define_insn "emms" (define_insn "emms"
[(unspec_volatile [(const_int 0)] 31) [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
(clobber (reg:XF 8)) (clobber (reg:XF 8))
(clobber (reg:XF 9)) (clobber (reg:XF 9))
(clobber (reg:XF 10)) (clobber (reg:XF 10))
...@@ -19110,7 +19149,8 @@ ...@@ -19110,7 +19149,8 @@
(set_attr "memory" "unknown")]) (set_attr "memory" "unknown")])
(define_insn "ldmxcsr" (define_insn "ldmxcsr"
[(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)] [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
UNSPECV_LDMXCSR)]
"TARGET_MMX" "TARGET_MMX"
"ldmxcsr\t%0" "ldmxcsr\t%0"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19118,7 +19158,7 @@ ...@@ -19118,7 +19158,7 @@
(define_insn "stmxcsr" (define_insn "stmxcsr"
[(set (match_operand:SI 0 "memory_operand" "=m") [(set (match_operand:SI 0 "memory_operand" "=m")
(unspec_volatile:SI [(const_int 0)] 40))] (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
"TARGET_MMX" "TARGET_MMX"
"stmxcsr\t%0" "stmxcsr\t%0"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19126,7 +19166,7 @@ ...@@ -19126,7 +19166,7 @@
(define_expand "sfence" (define_expand "sfence"
[(set (match_dup 0) [(set (match_dup 0)
(unspec:BLK [(match_dup 0)] 44))] (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
{ {
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
...@@ -19135,7 +19175,7 @@ ...@@ -19135,7 +19175,7 @@
(define_insn "*sfence_insn" (define_insn "*sfence_insn"
[(set (match_operand:BLK 0 "" "") [(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0)] 44))] (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
"sfence" "sfence"
[(set_attr "type" "sse") [(set_attr "type" "sse")
...@@ -19150,7 +19190,7 @@ ...@@ -19150,7 +19190,7 @@
(reg:DI 25) (reg:DI 25)
(reg:DI 26) (reg:DI 26)
(reg:DI 27) (reg:DI 27)
(reg:DI 28)] 13)) (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" "")) (use (match_operand:DI 1 "register_operand" ""))
(use (match_operand:DI 2 "immediate_operand" "")) (use (match_operand:DI 2 "immediate_operand" ""))
(use (label_ref:DI (match_operand 3 "" "")))])] (use (label_ref:DI (match_operand 3 "" "")))])]
...@@ -19167,7 +19207,7 @@ ...@@ -19167,7 +19207,7 @@
(reg:DI 25) (reg:DI 25)
(reg:DI 26) (reg:DI 26)
(reg:DI 27) (reg:DI 27)
(reg:DI 28)] 13)) (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" "r")) (use (match_operand:DI 1 "register_operand" "r"))
(use (match_operand:DI 2 "const_int_operand" "i")) (use (match_operand:DI 2 "const_int_operand" "i"))
(use (label_ref:DI (match_operand 3 "" "X")))] (use (label_ref:DI (match_operand 3 "" "X")))]
...@@ -19286,7 +19326,7 @@ ...@@ -19286,7 +19326,7 @@
(set_attr "mode" "V2SF")]) (set_attr "mode" "V2SF")])
(define_insn "femms" (define_insn "femms"
[(unspec_volatile [(const_int 0)] 46) [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
(clobber (reg:XF 8)) (clobber (reg:XF 8))
(clobber (reg:XF 9)) (clobber (reg:XF 9))
(clobber (reg:XF 10)) (clobber (reg:XF 10))
...@@ -19411,7 +19451,8 @@ ...@@ -19411,7 +19451,8 @@
[(set (match_operand:V8QI 0 "register_operand" "=y") [(set (match_operand:V8QI 0 "register_operand" "=y")
(unspec:V8QI (unspec:V8QI
[(match_operand:V8QI 1 "register_operand" "0") [(match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))] (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
UNSPEC_PAVGUSB))]
"TARGET_3DNOW" "TARGET_3DNOW"
"pavgusb\\t{%2, %0|%0, %2}" "pavgusb\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft") [(set_attr "type" "mmxshft")
...@@ -19421,7 +19462,8 @@ ...@@ -19421,7 +19462,8 @@
(define_insn "pfrcpv2sf2" (define_insn "pfrcpv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y") [(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))] (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
UNSPEC_PFRCP))]
"TARGET_3DNOW" "TARGET_3DNOW"
"pfrcp\\t{%1, %0|%0, %1}" "pfrcp\\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19430,7 +19472,8 @@ ...@@ -19430,7 +19472,8 @@
(define_insn "pfrcpit1v2sf3" (define_insn "pfrcpit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y") [(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))] (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
UNSPEC_PFRCPIT1))]
"TARGET_3DNOW" "TARGET_3DNOW"
"pfrcpit1\\t{%2, %0|%0, %2}" "pfrcpit1\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19439,7 +19482,8 @@ ...@@ -19439,7 +19482,8 @@
(define_insn "pfrcpit2v2sf3" (define_insn "pfrcpit2v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y") [(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))] (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
UNSPEC_PFRCPIT2))]
"TARGET_3DNOW" "TARGET_3DNOW"
"pfrcpit2\\t{%2, %0|%0, %2}" "pfrcpit2\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19447,7 +19491,8 @@ ...@@ -19447,7 +19491,8 @@
(define_insn "pfrsqrtv2sf2" (define_insn "pfrsqrtv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y") [(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))] (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
UNSPEC_PFRSQRT))]
"TARGET_3DNOW" "TARGET_3DNOW"
"pfrsqrt\\t{%1, %0|%0, %1}" "pfrsqrt\\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19456,7 +19501,8 @@ ...@@ -19456,7 +19501,8 @@
(define_insn "pfrsqit1v2sf3" (define_insn "pfrsqit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y") [(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))] (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
UNSPEC_PFRSQIT1))]
"TARGET_3DNOW" "TARGET_3DNOW"
"pfrsqit1\\t{%2, %0|%0, %2}" "pfrsqit1\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx") [(set_attr "type" "mmx")
...@@ -19819,7 +19865,8 @@ ...@@ -19819,7 +19865,8 @@
(define_insn "sse2_movmskpd" (define_insn "sse2_movmskpd"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V2DF 1 "register_operand" "x")] 33))] (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
UNSPEC_MOVMSK))]
"TARGET_SSE2" "TARGET_SSE2"
"movmskpd\t{%1, %0|%0, %1}" "movmskpd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19827,7 +19874,8 @@ ...@@ -19827,7 +19874,8 @@
(define_insn "sse2_pmovmskb" (define_insn "sse2_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] 33))] (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
UNSPEC_MOVMSK))]
"TARGET_SSE2" "TARGET_SSE2"
"pmovmskb\t{%1, %0|%0, %1}" "pmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19836,7 +19884,8 @@ ...@@ -19836,7 +19884,8 @@
(define_insn "sse2_maskmovdqu" (define_insn "sse2_maskmovdqu"
[(set (mem:V16QI (match_operand:SI 0 "register_operand" "D")) [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
(match_operand:V16QI 2 "register_operand" "x")] 32))] (match_operand:V16QI 2 "register_operand" "x")]
UNSPEC_MASKMOV))]
"TARGET_SSE2" "TARGET_SSE2"
;; @@@ check ordering of operands in intel/nonintel syntax ;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovdqu\t{%2, %1|%1, %2}" "maskmovdqu\t{%2, %1|%1, %2}"
...@@ -19845,7 +19894,8 @@ ...@@ -19845,7 +19894,8 @@
(define_insn "sse2_movntv2df" (define_insn "sse2_movntv2df"
[(set (match_operand:V2DF 0 "memory_operand" "=m") [(set (match_operand:V2DF 0 "memory_operand" "=m")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] 34))] (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
UNSPEC_MOVNT))]
"TARGET_SSE2" "TARGET_SSE2"
"movntpd\t{%1, %0|%0, %1}" "movntpd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19853,7 +19903,8 @@ ...@@ -19853,7 +19903,8 @@
(define_insn "sse2_movntv2di" (define_insn "sse2_movntv2di"
[(set (match_operand:V2DI 0 "memory_operand" "=m") [(set (match_operand:V2DI 0 "memory_operand" "=m")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")] 34))] (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
UNSPEC_MOVNT))]
"TARGET_SSE2" "TARGET_SSE2"
"movntdq\t{%1, %0|%0, %1}" "movntdq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19861,7 +19912,8 @@ ...@@ -19861,7 +19912,8 @@
(define_insn "sse2_movntsi" (define_insn "sse2_movntsi"
[(set (match_operand:SI 0 "memory_operand" "=m") [(set (match_operand:SI 0 "memory_operand" "=m")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")] 34))] (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_MOVNT))]
"TARGET_SSE2" "TARGET_SSE2"
"movnti\t{%1, %0|%0, %1}" "movnti\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19889,7 +19941,8 @@ ...@@ -19889,7 +19941,8 @@
(define_insn "cvttps2dq" (define_insn "cvttps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30))] (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttps2dq\t{%1, %0|%0, %1}" "cvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19922,7 +19975,8 @@ ...@@ -19922,7 +19975,8 @@
(define_insn "cvttpd2dq" (define_insn "cvttpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(vec_concat:V4SI (vec_concat:V4SI
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 30) (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX)
(const_vector:V2SI [(const_int 0) (const_int 0)])))] (const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttpd2dq\t{%1, %0|%0, %1}" "cvttpd2dq\t{%1, %0|%0, %1}"
...@@ -19939,7 +19993,8 @@ ...@@ -19939,7 +19993,8 @@
(define_insn "cvttpd2pi" (define_insn "cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y") [(set (match_operand:V2SI 0 "register_operand" "=y")
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 30))] (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttpd2pi\t{%1, %0|%0, %1}" "cvttpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -19967,7 +20022,7 @@ ...@@ -19967,7 +20022,7 @@
(define_insn "cvttsd2si" (define_insn "cvttsd2si"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
(parallel [(const_int 0)]))] 30))] (parallel [(const_int 0)]))] UNSPEC_FIX))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}" "cvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -20327,7 +20382,8 @@ ...@@ -20327,7 +20382,8 @@
(define_insn "sse2_psadbw" (define_insn "sse2_psadbw"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0") (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
(match_operand:V16QI 2 "nonimmediate_operand" "ym")] 61))] (match_operand:V16QI 2 "nonimmediate_operand" "ym")]
UNSPEC_PSADBW))]
"TARGET_SSE2" "TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}" "psadbw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
...@@ -20361,7 +20417,8 @@ ...@@ -20361,7 +20417,8 @@
(define_insn "sse2_pshufd" (define_insn "sse2_pshufd"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")] 41))] (match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_SHUFFLE))]
"TARGET_SSE2" "TARGET_SSE2"
"pshufd\t{%2, %1, %0|%0, %1, %2}" "pshufd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -20370,7 +20427,8 @@ ...@@ -20370,7 +20427,8 @@
(define_insn "sse2_pshuflw" (define_insn "sse2_pshuflw"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")] 55))] (match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_PSHUFLW))]
"TARGET_SSE2" "TARGET_SSE2"
"pshuflw\t{%2, %1, %0|%0, %1, %2}" "pshuflw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -20379,7 +20437,8 @@ ...@@ -20379,7 +20437,8 @@
(define_insn "sse2_pshufhw" (define_insn "sse2_pshufhw"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")] 56))] (match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_PSHUFHW))]
"TARGET_SSE2" "TARGET_SSE2"
"pshufhw\t{%2, %1, %0|%0, %1, %2}" "pshufhw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
...@@ -20628,7 +20687,7 @@ ...@@ -20628,7 +20687,7 @@
(unspec:TI (unspec:TI
[(ashift:TI (match_operand:TI 1 "register_operand" "0") [(ashift:TI (match_operand:TI 1 "register_operand" "0")
(mult:SI (match_operand:SI 2 "immediate_operand" "i") (mult:SI (match_operand:SI 2 "immediate_operand" "i")
(const_int 8)))] 30))] (const_int 8)))] UNSPEC_NOP))]
"TARGET_SSE2" "TARGET_SSE2"
"pslldq\t{%2, %0|%0, %2}" "pslldq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -20639,7 +20698,7 @@ ...@@ -20639,7 +20698,7 @@
(unspec:TI (unspec:TI
[(lshiftrt:TI (match_operand:TI 1 "register_operand" "0") [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
(mult:SI (match_operand:SI 2 "immediate_operand" "i") (mult:SI (match_operand:SI 2 "immediate_operand" "i")
(const_int 8)))] 30))] (const_int 8)))] UNSPEC_NOP))]
"TARGET_SSE2" "TARGET_SSE2"
"pslrdq\t{%2, %0|%0, %2}" "pslrdq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -20829,7 +20888,8 @@ ...@@ -20829,7 +20888,8 @@
(define_insn "sse2_movapd" (define_insn "sse2_movapd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
(unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")] 38))] (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
UNSPEC_MOVA))]
"TARGET_SSE2" "TARGET_SSE2"
"@ "@
movapd\t{%1, %0|%0, %1} movapd\t{%1, %0|%0, %1}
...@@ -20839,7 +20899,8 @@ ...@@ -20839,7 +20899,8 @@
(define_insn "sse2_movupd" (define_insn "sse2_movupd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
(unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")] 39))] (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
UNSPEC_MOVU))]
"TARGET_SSE2" "TARGET_SSE2"
"@ "@
movupd\t{%1, %0|%0, %1} movupd\t{%1, %0|%0, %1}
...@@ -20849,7 +20910,8 @@ ...@@ -20849,7 +20910,8 @@
(define_insn "sse2_movdqa" (define_insn "sse2_movdqa"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m") [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
(unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")] 38))] (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
UNSPEC_MOVA))]
"TARGET_SSE2" "TARGET_SSE2"
"@ "@
movdqa\t{%1, %0|%0, %1} movdqa\t{%1, %0|%0, %1}
...@@ -20859,7 +20921,8 @@ ...@@ -20859,7 +20921,8 @@
(define_insn "sse2_movdqu" (define_insn "sse2_movdqu"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m") [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
(unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")] 39))] (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
UNSPEC_MOVU))]
"TARGET_SSE2" "TARGET_SSE2"
"@ "@
movdqu\t{%1, %0|%0, %1} movdqu\t{%1, %0|%0, %1}
...@@ -20943,7 +21006,8 @@ ...@@ -20943,7 +21006,8 @@
[(set (match_operand:V2DF 0 "register_operand" "=x") [(set (match_operand:V2DF 0 "register_operand" "=x")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
(match_operand:V2DF 2 "nonimmediate_operand" "xm") (match_operand:V2DF 2 "nonimmediate_operand" "xm")
(match_operand:SI 3 "immediate_operand" "i")] 41))] (match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_SHUFFLE))]
"TARGET_SSE2" "TARGET_SSE2"
;; @@@ check operand order for intel/nonintel syntax ;; @@@ check operand order for intel/nonintel syntax
"shufpd\t{%3, %2, %0|%0, %2, %3}" "shufpd\t{%3, %2, %0|%0, %2, %3}"
...@@ -20951,7 +21015,8 @@ ...@@ -20951,7 +21015,8 @@
(set_attr "mode" "V2DF")]) (set_attr "mode" "V2DF")])
(define_insn "sse2_clflush" (define_insn "sse2_clflush"
[(unspec_volatile [(match_operand:SI 0 "address_operand" "p")] 57)] [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")]
UNSPECV_CLFLUSH)]
"TARGET_SSE2" "TARGET_SSE2"
"clflush %0" "clflush %0"
[(set_attr "type" "sse") [(set_attr "type" "sse")
...@@ -20959,7 +21024,7 @@ ...@@ -20959,7 +21024,7 @@
(define_expand "sse2_mfence" (define_expand "sse2_mfence"
[(set (match_dup 0) [(set (match_dup 0)
(unspec:BLK [(match_dup 0)] 59))] (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"TARGET_SSE2" "TARGET_SSE2"
{ {
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
...@@ -20968,7 +21033,7 @@ ...@@ -20968,7 +21033,7 @@
(define_insn "*mfence_insn" (define_insn "*mfence_insn"
[(set (match_operand:BLK 0 "" "") [(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0)] 59))] (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"TARGET_SSE2" "TARGET_SSE2"
"mfence" "mfence"
[(set_attr "type" "sse") [(set_attr "type" "sse")
...@@ -20976,7 +21041,7 @@ ...@@ -20976,7 +21041,7 @@
(define_expand "sse2_lfence" (define_expand "sse2_lfence"
[(set (match_dup 0) [(set (match_dup 0)
(unspec:BLK [(match_dup 0)] 60))] (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
"TARGET_SSE2" "TARGET_SSE2"
{ {
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
...@@ -20985,7 +21050,7 @@ ...@@ -20985,7 +21050,7 @@
(define_insn "*lfence_insn" (define_insn "*lfence_insn"
[(set (match_operand:BLK 0 "" "") [(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0)] 60))] (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
"TARGET_SSE2" "TARGET_SSE2"
"lfence" "lfence"
[(set_attr "type" "sse") [(set_attr "type" "sse")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment