Commit 8cc9a087 by Eric Botcazou Committed by Eric Botcazou

sparc.c (sparc_do_work_around_errata): Use mem_ref instead of MEM_P in a couple more places.

	* config/sparc/sparc.c (sparc_do_work_around_errata): Use mem_ref
	instead of MEM_P in a couple more places.  Fix formatting issues.

From-SVN: r255393
parent 472a7639
2017-12-04 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.c (sparc_do_work_around_errata): Use mem_ref
instead of MEM_P in a couple more places. Fix formatting issues.
2017-12-04 Jim Wilson <jimw@sifive.com> 2017-12-04 Jim Wilson <jimw@sifive.com>
* config/riscv/riscv.c (riscv_for_each_saved_reg): Use GP_REG_LAST * config/riscv/riscv.c (riscv_for_each_saved_reg): Use GP_REG_LAST
...@@ -1050,43 +1050,42 @@ sparc_do_work_around_errata (void) ...@@ -1050,43 +1050,42 @@ sparc_do_work_around_errata (void)
/* Look into the instruction in a delay slot. */ /* Look into the instruction in a delay slot. */
if (NONJUMP_INSN_P (insn) if (NONJUMP_INSN_P (insn)
&& (seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))) && (seq = dyn_cast <rtx_sequence *> (PATTERN (insn))))
{ {
jump = seq->insn (0); jump = seq->insn (0);
insn = seq->insn (1); insn = seq->insn (1);
} }
else if (JUMP_P (insn)) else if (JUMP_P (insn))
jump = insn; jump = insn;
else else
jump = NULL; jump = NULL;
/* Place a NOP at the branch target of an integer branch if it is /* Place a NOP at the branch target of an integer branch if it is a
a floating-point operation or a floating-point branch. */ floating-point operation or a floating-point branch. */
if (sparc_fix_gr712rc if (sparc_fix_gr712rc
&& jump != NULL_RTX && jump
&& get_attr_branch_type (jump) == BRANCH_TYPE_ICC) && get_attr_branch_type (jump) == BRANCH_TYPE_ICC)
{ {
rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump)); rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump));
if (target if (target
&& (fpop_insn_p (target) && (fpop_insn_p (target)
|| ((JUMP_P (target) || (JUMP_P (target)
&& get_attr_branch_type (target) == BRANCH_TYPE_FCC)))) && get_attr_branch_type (target) == BRANCH_TYPE_FCC)))
emit_insn_before (gen_nop (), target); emit_insn_before (gen_nop (), target);
} }
/* Insert a NOP between load instruction and atomic /* Insert a NOP between load instruction and atomic instruction. Insert
instruction. Insert a NOP at branch target if load a NOP at branch target if there is a load in delay slot and an atomic
in delay slot and atomic instruction at branch target. */ instruction at branch target. */
if (sparc_fix_ut700 if (sparc_fix_ut700
&& NONJUMP_INSN_P (insn) && NONJUMP_INSN_P (insn)
&& (set = single_set (insn)) != NULL_RTX && (set = single_set (insn)) != NULL_RTX
&& MEM_P (SET_SRC (set)) && mem_ref (SET_SRC (set))
&& REG_P (SET_DEST (set))) && REG_P (SET_DEST (set)))
{ {
if (jump) if (jump)
{ {
rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump)); rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump));
if (target if (target && atomic_insn_for_leon3_p (target))
&& atomic_insn_for_leon3_p (target))
emit_insn_before (gen_nop (), target); emit_insn_before (gen_nop (), target);
} }
...@@ -1098,7 +1097,9 @@ sparc_do_work_around_errata (void) ...@@ -1098,7 +1097,9 @@ sparc_do_work_around_errata (void)
insert_nop = true; insert_nop = true;
} }
/* Look for sequences that could trigger the GRLIB-TN-0013 errata. */ /* Look for a sequence that starts with a fdiv or fsqrt instruction and
ends with another fdiv or fsqrt instruction with no dependencies on
the former, along with an appropriate pattern in between. */
if (sparc_fix_lost_divsqrt if (sparc_fix_lost_divsqrt
&& NONJUMP_INSN_P (insn) && NONJUMP_INSN_P (insn)
&& div_sqrt_insn_p (insn)) && div_sqrt_insn_p (insn))
...@@ -1229,8 +1230,8 @@ sparc_do_work_around_errata (void) ...@@ -1229,8 +1230,8 @@ sparc_do_work_around_errata (void)
then the sequence cannot be problematic. */ then the sequence cannot be problematic. */
if (i == 0) if (i == 0)
{ {
if (((set = single_set (after)) != NULL_RTX) if ((set = single_set (after)) != NULL_RTX
&& (MEM_P (SET_DEST (set)) || MEM_P (SET_SRC (set)))) && (MEM_P (SET_DEST (set)) || mem_ref (SET_SRC (set))))
break; break;
after = next_active_insn (after); after = next_active_insn (after);
...@@ -1240,21 +1241,21 @@ sparc_do_work_around_errata (void) ...@@ -1240,21 +1241,21 @@ sparc_do_work_around_errata (void)
/* Add NOP if third instruction is a store. */ /* Add NOP if third instruction is a store. */
if (i == 1 if (i == 1
&& ((set = single_set (after)) != NULL_RTX) && (set = single_set (after)) != NULL_RTX
&& MEM_P (SET_DEST (set))) && MEM_P (SET_DEST (set)))
insert_nop = true; insert_nop = true;
} }
} }
else
/* Look for a single-word load into an odd-numbered FP register. */ /* Look for a single-word load into an odd-numbered FP register. */
if (sparc_fix_at697f else if (sparc_fix_at697f
&& NONJUMP_INSN_P (insn) && NONJUMP_INSN_P (insn)
&& (set = single_set (insn)) != NULL_RTX && (set = single_set (insn)) != NULL_RTX
&& GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
&& MEM_P (SET_SRC (set)) && mem_ref (SET_SRC (set))
&& REG_P (SET_DEST (set)) && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) > 31 && REGNO (SET_DEST (set)) > 31
&& REGNO (SET_DEST (set)) % 2 != 0) && REGNO (SET_DEST (set)) % 2 != 0)
{ {
/* The wrong dependency is on the enclosing double register. */ /* The wrong dependency is on the enclosing double register. */
const unsigned int x = REGNO (SET_DEST (set)) - 1; const unsigned int x = REGNO (SET_DEST (set)) - 1;
......
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