Commit 89774469 by Steve Ellcey Committed by Steve Ellcey

re PR target/36898 (Insufficient qp-mutex declarations)

2010-10-18  Steve Ellcey  <sje@cup.hp.com>

	PR target/36898
	PR middle-end/43760
	* config/ia64/ia64.c (rws_access_regno): Remove predicate check.

From-SVN: r165664
parent b69da3d8
2010-10-18 Steve Ellcey <sje@cup.hp.com>
PR target/36898
PR middle-end/43760
* config/ia64/ia64.c (rws_access_regno): Remove predicate check.
2010-10-18 Joseph Myers <joseph@codesourcery.com> 2010-10-18 Joseph Myers <joseph@codesourcery.com>
* config/i386/i386.c (ix86_option_override_internal): Define and * config/i386/i386.c (ix86_option_override_internal): Define and
...@@ -5875,15 +5875,14 @@ rws_access_regno (int regno, struct reg_flags flags, int pred) ...@@ -5875,15 +5875,14 @@ rws_access_regno (int regno, struct reg_flags flags, int pred)
break; break;
case 1: case 1:
/* The register has been written via a predicate. If this is /* The register has been written via a predicate. Treat
not a complementary predicate, then we need a barrier. */ it like a unconditional write and do not try to check
/* ??? This assumes that P and P+1 are always complementary for complementary pred reg in earlier write. */
predicates for P even. */
if (flags.is_and && rws_sum[regno].written_by_and) if (flags.is_and && rws_sum[regno].written_by_and)
; ;
else if (flags.is_or && rws_sum[regno].written_by_or) else if (flags.is_or && rws_sum[regno].written_by_or)
; ;
else if ((rws_sum[regno].first_pred ^ 1) != pred) else
need_barrier = 1; need_barrier = 1;
if (!in_safe_group_barrier) if (!in_safe_group_barrier)
rws_update (regno, flags, pred); rws_update (regno, flags, pred);
...@@ -5944,11 +5943,8 @@ rws_access_regno (int regno, struct reg_flags flags, int pred) ...@@ -5944,11 +5943,8 @@ rws_access_regno (int regno, struct reg_flags flags, int pred)
break; break;
case 1: case 1:
/* The register has been written via a predicate. If this is /* The register has been written via a predicate, assume we
not a complementary predicate, then we need a barrier. */ need a barrier (don't check for complementary regs). */
/* ??? This assumes that P and P+1 are always complementary
predicates for P even. */
if ((rws_sum[regno].first_pred ^ 1) != pred)
need_barrier = 1; need_barrier = 1;
break; break;
......
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