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Commit 89520fd7 by Jason Eckhardt Committed by Jason Eckhardt
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i860-protos.h (output_delay_insn): Remove prototype. 

2003-08-22  Jason Eckhardt  <jle@rice.edu>

	* config/i860/i860-protos.h (output_delay_insn): Remove prototype.
	(output_delayed_branch): Remove prototype.
	(single_insn_src_p): Remove prototype.
	* config/i860/i860.c (single_insn_src_p): Remove function.
	(output_delayed_branch): Remove function.
	(output_delay_insn): Remove function.
	(va_start): Remove unconditional test and dead code, re-format.
	Fix coding style and spelling problems in various comments.
	* config/i860/i860.md (UNSPECV_BLOCKAGE): Define constant...
	(blockage pattern): ...and use it here.
	(all define_peephole patterns related to delayed branches): Remove.
	Fix coding style and spelling problems in various comments.

From-SVN: r70724
parent 8274e603
Showing with 37 additions and 123 deletions
gcc/ChangeLog
2003-08-22 Jason Eckhardt <jle@rice.edu>
* config/i860/i860-protos.h (output_delay_insn): Remove prototype.
(output_delayed_branch): Remove prototype.
(single_insn_src_p): Remove prototype.
* config/i860/i860.c (single_insn_src_p): Remove function.
(output_delayed_branch): Remove function.
(output_delay_insn): Remove function.
(va_start): Remove unconditional test and dead code, re-format.
Fix coding style and spelling problems in various comments.
* config/i860/i860.md (UNSPECV_BLOCKAGE): Define constant...
(blockage pattern): ...and use it here.
(all define_peephole patterns related to delayed branches): Remove.
Fix coding style and spelling problems in various comments.
2003-08-22 Jason Eckhardt <jle@rice.edu>
* config/i860/i860.c: Replace all occurrences of 'GNU CC' with 'GCC'.
Remove all uses of the PARAMS macro. Remove superflous prototypes.
Convert all function definitions from traditional to ISO C90 syntax.
......
gcc/config/i860/i860-protos.h
......@@ -30,14 +30,9 @@ extern const char *output_store (rtx *);
extern const char *output_move_double (rtx *);
extern const char *output_fp_move_double (rtx *);
extern const char *output_block_move (rtx *);
extern const char *output_delay_insn (rtx);
#if 0
extern const char *output_delayed_branch (const char *, rtx *, rtx);
#endif
extern void output_load_address (rtx *);
extern int safe_insn_src_p (rtx, enum machine_mode);
extern int operand_clobbered_before_used_after (rtx, rtx);
extern int single_insn_src_p (rtx, enum machine_mode);
extern int reg_or_0_operand (rtx, enum machine_mode);
extern int arith_operand (rtx, enum machine_mode);
extern int logic_operand (rtx, enum machine_mode);
......
gcc/config/i860/i860.md
;;- Machine description for Intel 860 chip for GNU C compiler
;; GCC Machine description for the Intel i860 microprocessor
;; Copyright (C) 1989, 1990, 1997, 1998, 1999, 2000, 2003
;; Free Software Foundation, Inc.
......@@ -25,6 +25,15 @@
;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
;;- updates for most instructions.
;;
;; UNSPEC_VOLATILE usage
;;
(define_constants
[; Blockage
(UNSPECV_BLOCKAGE 0)
])
;;- Operand classes for the register allocator:
/* Bit-test instructions. */
......@@ -307,8 +316,7 @@
return \"pfgt.ss %r0,%r1,%?f0\";
}")
;; NOTE: The pfle opcode doesn't do what you think it does. It is
;; bass-ackwards. It *clears* the CC flag if the first operand is
;; NOTE: The pfle opcode *clears* the CC flag if the first operand is
;; less than or equal to the second. Thus, we have to set CC_NEGATED
;; for the following two patterns.
......@@ -385,8 +393,7 @@
return \"pfgt.dd %r0,%r1,%?f0\";
}")
;; NOTE: The pfle opcode doesn't do what you think it does. It is
;; bass-ackwards. It *clears* the CC flag if the first operand is
;; NOTE: The pfle opcode *clears* the CC flag if the first operand is
;; less than or equal to the second. Thus, we have to set CC_NEGATED
;; for the following two patterns.
......@@ -878,7 +885,7 @@
;; Move instructions
;; Note that source operands for `mov' pseudo-instructions are no longer
;; allowed (by the svr4 assembler) to be "big" things, i.e. constants that
;; allowed (by the SVR4 assembler) to be "big" things, i.e. constants that
;; won't fit in 16-bits. (This includes any sort of a relocatable address
;; also.) Thus, we must use an explicit orh/or pair of instructions if
;; the source operand is something "big".
......@@ -1520,9 +1527,9 @@
return \"and 128,%0,%?r0\";
}")
;; next two patterns are good for bitfields coming from memory
;; The next two patterns are good for bitfields coming from memory
;; (via pseudo-register) or from a register, though this optimization
;; is only good for values contained wholly within the bottom 13 bits
;; is only good for values contained wholly within the bottom 13 bits.
(define_insn ""
[(set (cc0)
(eq
......@@ -1573,7 +1580,7 @@
;; Note that among the fix-to-float insns
;; the ones that start with SImode come first.
;; That is so that an operand that is a CONST_INT
;; (and therefore lacks a specific machine mode).
;; (and therefore lacks a specific machine mode)
;; will be recognized as SImode (which is always valid)
;; rather than as QImode or HImode.
......@@ -1999,8 +2006,7 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
;; Shift instructions
;; Optimized special case of shifting.
;; Must precede the general case.
;; Optimized special case of shifting, which must precede the general case.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
......@@ -2020,7 +2026,7 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
}")
;;- arithmetic shift instructions
;;- Arithmetic shift instructions.
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI (match_operand:SI 1 "register_operand" "r")
......@@ -2071,7 +2077,7 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
return \"shr %2,%1,%0\";
}")
;; Unconditional and other jump instructions
;; Unconditional and other jump instructions.
(define_insn "jump"
[(set (pc) (label_ref (match_operand 0 "" "")))]
......@@ -2081,41 +2087,12 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
return \"br %l0\;nop\";
}")
;; Here are two simple peepholes which fill the delay slot of
;; an unconditional branch.
;
;; ??? All disabled, because output_delayed_branch is a crock
;; that will reliably segfault. This should be using the dbr
;; pass in any case. Anyone who cares is welcome to fix it.
;
;(define_peephole
; [(set (match_operand:SI 0 "register_operand" "=rf")
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
; (set (pc) (label_ref (match_operand 2 "" "")))]
; ""
; "* return output_delayed_branch (\"br %l2\", operands, insn);")
;
;(define_peephole
; [(set (match_operand:SI 0 "memory_operand" "=m")
; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
; (set (pc) (label_ref (match_operand 2 "" "")))]
; ""
; "* return output_delayed_branch (\"br %l2\", operands, insn);")
(define_insn "tablejump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))]
""
"bri %0\;nop")
;(define_peephole
; [(set (match_operand:SI 0 "memory_operand" "=m")
; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
; (set (pc) (match_operand:SI 2 "register_operand" "r"))
; (use (label_ref (match_operand 3 "" "")))]
; ""
; "* return output_delayed_branch (\"bri %2\", operands, insn);")
;;- jump to subroutine
(define_expand "call"
[(call (match_operand:SI 0 "memory_operand" "m")
......@@ -2137,7 +2114,7 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
}
}")
;;- jump to subroutine
;;- Jump to subroutine.
(define_insn ""
[(call (match_operand:SI 0 "call_insn_operand" "m")
(match_operand 1 "" "i"))]
......@@ -2153,38 +2130,6 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
return \"call %0\;nop\";
}")
;(define_peephole
; [(set (match_operand:SI 0 "register_operand" "=rf")
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
; (call (match_operand:SI 2 "memory_operand" "m")
; (match_operand 3 "" "i"))]
; ;;- Don't use operand 1 for most machines.
; "! reg_mentioned_p (operands[0], operands[2])"
; "*
;{
; /* strip the MEM. */
; operands[2] = XEXP (operands[2], 0);
; if (GET_CODE (operands[2]) == REG)
; return output_delayed_branch (\"calli %2\", operands, insn);
; return output_delayed_branch (\"call %2\", operands, insn);
;}")
;(define_peephole
; [(set (match_operand:SI 0 "memory_operand" "=m")
; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
; (call (match_operand:SI 2 "call_insn_operand" "m")
; (match_operand 3 "" "i"))]
; ;;- Don't use operand 1 for most machines.
; ""
; "*
;{
; /* strip the MEM. */
; operands[2] = XEXP (operands[2], 0);
; if (GET_CODE (operands[2]) == REG)
; return output_delayed_branch (\"calli %2\", operands, insn);
; return output_delayed_branch (\"call %2\", operands, insn);
;}")
(define_expand "call_value"
[(set (match_operand 0 "register_operand" "=rf")
(call (match_operand:SI 1 "memory_operand" "m")
......@@ -2214,7 +2159,7 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
""
"*
{
/* strip the MEM. */
/* Strip the MEM. */
operands[1] = XEXP (operands[1], 0);
CC_STATUS_INIT;
if (GET_CODE (operands[1]) == REG)
......@@ -2222,40 +2167,6 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
return \"call %1\;nop\";
}")
;(define_peephole
; [(set (match_operand:SI 0 "register_operand" "=rf")
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
; (set (match_operand 2 "" "=rf")
; (call (match_operand:SI 3 "call_insn_operand" "m")
; (match_operand 4 "" "i")))]
; ;;- Don't use operand 4 for most machines.
; "! reg_mentioned_p (operands[0], operands[3])"
; "*
;{
; /* strip the MEM. */
; operands[3] = XEXP (operands[3], 0);
; if (GET_CODE (operands[3]) == REG)
; return output_delayed_branch (\"calli %3\", operands, insn);
; return output_delayed_branch (\"call %3\", operands, insn);
;}")
;(define_peephole
; [(set (match_operand:SI 0 "memory_operand" "=m")
; (match_operand:SI 1 "reg_or_0_operand" "rJf"))
; (set (match_operand 2 "" "=rf")
; (call (match_operand:SI 3 "call_insn_operand" "m")
; (match_operand 4 "" "i")))]
; ;;- Don't use operand 4 for most machines.
; ""
; "*
;{
; /* strip the MEM. */
; operands[3] = XEXP (operands[3], 0);
; if (GET_CODE (operands[3]) == REG)
; return output_delayed_branch (\"calli %3\", operands, insn);
; return output_delayed_branch (\"call %3\", operands, insn);
;}")
;; Call subroutine returning any type.
(define_expand "untyped_call"
......@@ -2289,7 +2200,7 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] 0)]
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
"")
......@@ -2318,10 +2229,3 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
return \"orh %H2,%?r0,%?r31\;or %L2,%?r31,%?r31\;ld.l %?r31(%1),%0\";
}")
;(define_peephole
; [(set (match_operand:SI 0 "register_operand" "=rf")
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
; (set (pc) (match_operand:SI 2 "register_operand" "r"))
; (use (label_ref (match_operand 3 "" "")))]
; "REGNO (operands[0]) != REGNO (operands[2])"
; "* return output_delayed_branch (\"bri %2\", operands, insn);")
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