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riscv-gcc-1
Commit 8861ba4d by Uros Bizjak
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sse.md (ssse3_plusminus): New code iterator. 

2012-04-14  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/sse.md (ssse3_plusminus): New code iterator.
	(avx2_ph<plusminus_mnemonic>wv16hi3): Macroize insn from
	avx2_ph{add,adds,sub,subs}wv16hi3 using ssse3_plusminus code iterator.
	(ssse3_ph<plusminus_mnemonic>wv8hi3): Macroize insn from
	ssse3_ph{add,adds,sub,subs}wv8hi3 using ssse3_plusminus code iterator.
	(ssse3_ph<plusminus_mnemonic>wv4hi3): Macroize insn from
	ssse3_ph{add,adds,sub,subs}wv4hi3 using ssse3_plusminus code iterator.

	(avx2_ph<plusminus_mnemonic>dv8si3): Macroize insn from
	avx2_ph{add,adds,sub,subs}dv8si3 using plusminus code iterator.
	(ssse3_ph<plusminus_mnemonic>dv4si3): Macroize insn from
	ssse3_ph{add,adds,sub,subs}dv4si3 using plusminus code iterator.
	(ssse3_ph<plusminus_mnemonic>dv2si3): Macroize insn from
	ssse3_ph{add,adds,sub,subs}dv2si3 using plusminus code iterator.

	(xop_plus): New code iterator.
	(macs): New code attribute.
	(macds): Ditto.
	(xop_p<macs><ssemodesuffix><ssemodesuffix>): Macroize insn from
	xop_pmacs{,s}{ww,dd} using xop_plus code iterator and VI24_128 mode
	iterator.
	(xop_p<macs>dql): Macroize insn from xop_pmacs{,s}dql using
	xop_plus code iterator.
	(xop_p<macs>dqh): Macroize insn from xop_pmacs{,s}dqh using
	xop_plus code iterator.
	(xop_p<macs>wd): Macroize insn from xop_pmacs{,s}wd using
	xop_plus code iterator.
	(xop_p<madcs>wd): Macroize insn from xop_pmadcs{,s}wd using
	xop_plus code iterator.

	(xop_phadd<u>bw): Macroize insn from xop_phadd{,u}bw usign
	any_extend code iterator.
	(xop_phadd<u>bd): Macroize insn from xop_phadd{,u}bd usign
	any_extend code iterator.
	(xop_phadd<u>bq): Macroize insn from xop_phadd{,u}bq usign
	any_extend code iterator.
	(xop_phadd<u>wd): Macroize insn from xop_phadd{,u}wd usign
	any_extend code iterator.
	(xop_phadd<u>wq): Macroize insn from xop_phadd{,u}wq usign
	any_extend code iterator.
	(xop_phadd<u>dq): Macroize insn from xop_phadd{,u}dq usign
	any_extend code iterator.

From-SVN: r186454
parent 531b2c7b
Showing with 338 additions and 1166 deletions
gcc/ChangeLog
2012-04-14 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (ssse3_plusminus): New code iterator.
(avx2_ph<plusminus_mnemonic>wv16hi3): Macroize insn from
avx2_ph{add,adds,sub,subs}wv16hi3 using ssse3_plusminus code iterator.
(ssse3_ph<plusminus_mnemonic>wv8hi3): Macroize insn from
ssse3_ph{add,adds,sub,subs}wv8hi3 using ssse3_plusminus code iterator.
(ssse3_ph<plusminus_mnemonic>wv4hi3): Macroize insn from
ssse3_ph{add,adds,sub,subs}wv4hi3 using ssse3_plusminus code iterator.
(avx2_ph<plusminus_mnemonic>dv8si3): Macroize insn from
avx2_ph{add,adds,sub,subs}dv8si3 using plusminus code iterator.
(ssse3_ph<plusminus_mnemonic>dv4si3): Macroize insn from
ssse3_ph{add,adds,sub,subs}dv4si3 using plusminus code iterator.
(ssse3_ph<plusminus_mnemonic>dv2si3): Macroize insn from
ssse3_ph{add,adds,sub,subs}dv2si3 using plusminus code iterator.
(xop_plus): New code iterator.
(macs): New code attribute.
(macds): Ditto.
(xop_p<macs><ssemodesuffix><ssemodesuffix>): Macroize insn from
xop_pmacs{,s}{ww,dd} using xop_plus code iterator and VI24_128 mode
iterator.
(xop_p<macs>dql): Macroize insn from xop_pmacs{,s}dql using
xop_plus code iterator.
(xop_p<macs>dqh): Macroize insn from xop_pmacs{,s}dqh using
xop_plus code iterator.
(xop_p<macs>wd): Macroize insn from xop_pmacs{,s}wd using
xop_plus code iterator.
(xop_p<madcs>wd): Macroize insn from xop_pmadcs{,s}wd using
xop_plus code iterator.
(xop_phadd<u>bw): Macroize insn from xop_phadd{,u}bw usign
any_extend code iterator.
(xop_phadd<u>bd): Macroize insn from xop_phadd{,u}bd usign
any_extend code iterator.
(xop_phadd<u>bq): Macroize insn from xop_phadd{,u}bq usign
any_extend code iterator.
(xop_phadd<u>wd): Macroize insn from xop_phadd{,u}wd usign
any_extend code iterator.
(xop_phadd<u>wq): Macroize insn from xop_phadd{,u}wq usign
any_extend code iterator.
(xop_phadd<u>dq): Macroize insn from xop_phadd{,u}dq usign
any_extend code iterator.
2012-04-14 Tom de Vries <tom@codesourcery.com> 2012-04-14 Tom de Vries <tom@codesourcery.com>
* cfgcleanup.c (try_optimize_cfg): Replace call to delete_insn_chain by * cfgcleanup.c (try_optimize_cfg): Replace call to delete_insn_chain by
...@@ -204,8 +249,7 @@ ...@@ -204,8 +249,7 @@
2012-04-13 Richard Guenther <rguenther@suse.de> 2012-04-13 Richard Guenther <rguenther@suse.de>
PR c/52862 PR c/52862
* convert.c (convert_to_pointer): Remove special-casing of * convert.c (convert_to_pointer): Remove special-casing of zero.
zero.
2012-04-13 Joey Ye <joey.ye@arm.com> 2012-04-13 Joey Ye <joey.ye@arm.com>
......
gcc/config/i386/sse.md
...@@ -8037,7 +8037,8 @@ ...@@ -8037,7 +8037,8 @@
;; surely not generally useful. ;; surely not generally useful.
(define_insn "<sse2_avx2>_psadbw" (define_insn "<sse2_avx2>_psadbw"
[(set (match_operand:VI8_AVX2 0 "register_operand" "=x,x") [(set (match_operand:VI8_AVX2 0 "register_operand" "=x,x")
(unspec:VI8_AVX2 [(match_operand:<ssebytemode> 1 "register_operand" "0,x") (unspec:VI8_AVX2
[(match_operand:<ssebytemode> 1 "register_operand" "0,x")
(match_operand:<ssebytemode> 2 "nonimmediate_operand" "xm,xm")] (match_operand:<ssebytemode> 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_PSADBW))] UNSPEC_PSADBW))]
"TARGET_SSE2" "TARGET_SSE2"
...@@ -8175,123 +8176,125 @@ ...@@ -8175,123 +8176,125 @@
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn "avx2_phaddwv16hi3" (define_code_iterator ssse3_plusminus [plus ss_plus minus ss_minus])
(define_insn "avx2_ph<plusminus_mnemonic>wv16hi3"
[(set (match_operand:V16HI 0 "register_operand" "=x") [(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_concat:V16HI (vec_concat:V16HI
(vec_concat:V8HI (vec_concat:V8HI
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (vec_select:HI
(match_operand:V16HI 1 "register_operand" "x") (match_operand:V16HI 1 "register_operand" "x")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)])) (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)])))) (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)])) (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)])) (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)]))))) (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 8)])) (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 9)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 10)])) (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 11)])))) (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 12)])) (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 13)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 14)])) (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 15)])))))) (vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
(vec_concat:V8HI (vec_concat:V8HI
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (vec_select:HI
(match_operand:V16HI 2 "nonimmediate_operand" "xm") (match_operand:V16HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)])))) (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)])) (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)])) (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)]))))) (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 8)])) (vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 9)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 10)])) (vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 11)])))) (vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 12)])) (vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 13)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 14)])) (vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))] (vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
"TARGET_AVX2" "TARGET_AVX2"
"vphaddw\t{%2, %1, %0|%0, %1, %2}" "vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex") (set_attr "prefix" "vex")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "ssse3_phaddwv8hi3" (define_insn "ssse3_ph<plusminus_mnemonic>wv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x,x") [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI (vec_concat:V8HI
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (vec_select:HI
(match_operand:V8HI 1 "register_operand" "0,x") (match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)])) (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)])))) (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)])) (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)])) (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)]))))) (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (vec_select:HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)])))) (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)])) (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)])) (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))] (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3" "TARGET_SSSE3"
"@ "@
phaddw\t{%2, %0|%0, %2} ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
vphaddw\t{%2, %1, %0|%0, %1, %2}" vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx") [(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd") (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex") (set_attr "atom_unit" "complex")
...@@ -8300,104 +8303,104 @@ ...@@ -8300,104 +8303,104 @@
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "ssse3_phaddwv4hi3" (define_insn "ssse3_ph<plusminus_mnemonic>wv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y") [(set (match_operand:V4HI 0 "register_operand" "=y")
(vec_concat:V4HI (vec_concat:V4HI
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (vec_select:HI
(match_operand:V4HI 1 "register_operand" "0") (match_operand:V4HI 1 "register_operand" "0")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)])) (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)])))) (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI (vec_concat:V2HI
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (vec_select:HI
(match_operand:V4HI 2 "nonimmediate_operand" "ym") (match_operand:V4HI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(plus:HI (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))] (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3" "TARGET_SSSE3"
"phaddw\t{%2, %0|%0, %2}" "ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex") (set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "avx2_phadddv8si3" (define_insn "avx2_ph<plusminus_mnemonic>dv8si3"
[(set (match_operand:V8SI 0 "register_operand" "=x") [(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_concat:V8SI (vec_concat:V8SI
(vec_concat:V4SI (vec_concat:V4SI
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (vec_select:SI
(match_operand:V8SI 1 "register_operand" "x") (match_operand:V8SI 1 "register_operand" "x")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)]))) (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 2)])) (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 3)])))) (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 4)])) (vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 5)]))) (vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 6)])) (vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 7)]))))) (vec_select:SI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4SI (vec_concat:V4SI
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (vec_select:SI
(match_operand:V8SI 2 "nonimmediate_operand" "xm") (match_operand:V8SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)]))) (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)])) (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)])))) (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 4)])) (vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 5)]))) (vec_select:SI (match_dup 2) (parallel [(const_int 5)])))
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 6)])) (vec_select:SI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))] (vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_AVX2" "TARGET_AVX2"
"vphaddd\t{%2, %1, %0|%0, %1, %2}" "vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex") (set_attr "prefix" "vex")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "ssse3_phadddv4si3" (define_insn "ssse3_ph<plusminus_mnemonic>dv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x,x") [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_concat:V4SI (vec_concat:V4SI
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (vec_select:SI
(match_operand:V4SI 1 "register_operand" "0,x") (match_operand:V4SI 1 "register_operand" "0,x")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)]))) (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 2)])) (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 3)])))) (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (vec_select:SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm,xm") (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)]))) (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(plus:SI (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)])) (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))] (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3" "TARGET_SSSE3"
"@ "@
phaddd\t{%2, %0|%0, %2} ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
vphaddd\t{%2, %1, %0|%0, %1, %2}" vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx") [(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd") (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex") (set_attr "atom_unit" "complex")
...@@ -8406,768 +8409,207 @@ ...@@ -8406,768 +8409,207 @@
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "ssse3_phadddv2si3" (define_insn "ssse3_ph<plusminus_mnemonic>dv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y") [(set (match_operand:V2SI 0 "register_operand" "=y")
(vec_concat:V2SI (vec_concat:V2SI
(plus:SI (plusminus:SI
(vec_select:SI (vec_select:SI
(match_operand:V2SI 1 "register_operand" "0") (match_operand:V2SI 1 "register_operand" "0")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)]))) (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(plus:SI (plusminus:SI
(vec_select:SI (vec_select:SI
(match_operand:V2SI 2 "nonimmediate_operand" "ym") (match_operand:V2SI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))] (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSSE3" "TARGET_SSSE3"
"phaddd\t{%2, %0|%0, %2}" "ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex") (set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "avx2_phaddswv16hi3" (define_insn "avx2_pmaddubsw256"
[(set (match_operand:V16HI 0 "register_operand" "=x") [(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_concat:V16HI (ss_plus:V16HI
(vec_concat:V8HI (mult:V16HI
(vec_concat:V4HI (zero_extend:V16HI
(vec_concat:V2HI (vec_select:V16QI
(ss_plus:HI (match_operand:V32QI 1 "register_operand" "x")
(vec_select:HI (parallel [(const_int 0)
(match_operand:V16HI 1 "register_operand" "x") (const_int 2)
(parallel [(const_int 0)])) (const_int 4)
(vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (const_int 6)
(ss_plus:HI (const_int 8)
(vec_select:HI (match_dup 1) (parallel [(const_int 2)])) (const_int 10)
(vec_select:HI (match_dup 1) (parallel [(const_int 3)])))) (const_int 12)
(vec_concat:V2HI (const_int 14)
(ss_plus:HI (const_int 16)
(vec_select:HI (match_dup 1) (parallel [(const_int 4)])) (const_int 18)
(vec_select:HI (match_dup 1) (parallel [(const_int 5)]))) (const_int 20)
(ss_plus:HI (const_int 22)
(vec_select:HI (match_dup 1) (parallel [(const_int 6)])) (const_int 24)
(vec_select:HI (match_dup 1) (parallel [(const_int 7)]))))) (const_int 26)
(vec_concat:V4HI (const_int 28)
(vec_concat:V2HI (const_int 30)])))
(ss_plus:HI (sign_extend:V16HI
(vec_select:HI (match_dup 1) (parallel [(const_int 8)])) (vec_select:V16QI
(vec_select:HI (match_dup 1) (parallel [(const_int 9)]))) (match_operand:V32QI 2 "nonimmediate_operand" "xm")
(ss_plus:HI (parallel [(const_int 0)
(vec_select:HI (match_dup 1) (parallel [(const_int 10)])) (const_int 2)
(vec_select:HI (match_dup 1) (parallel [(const_int 11)])))) (const_int 4)
(vec_concat:V2HI (const_int 6)
(ss_plus:HI (const_int 8)
(vec_select:HI (match_dup 1) (parallel [(const_int 12)])) (const_int 10)
(vec_select:HI (match_dup 1) (parallel [(const_int 13)]))) (const_int 12)
(ss_plus:HI (const_int 14)
(vec_select:HI (match_dup 1) (parallel [(const_int 14)])) (const_int 16)
(vec_select:HI (match_dup 1) (parallel [(const_int 15)])))))) (const_int 18)
(vec_concat:V8HI (const_int 20)
(vec_concat:V4HI (const_int 22)
(vec_concat:V2HI (const_int 24)
(ss_plus:HI (const_int 26)
(vec_select:HI (const_int 28)
(match_operand:V16HI 2 "nonimmediate_operand" "xm") (const_int 30)]))))
(parallel [(const_int 0)])) (mult:V16HI
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (zero_extend:V16HI
(ss_plus:HI (vec_select:V16QI (match_dup 1)
(vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (parallel [(const_int 1)
(vec_select:HI (match_dup 2) (parallel [(const_int 3)])))) (const_int 3)
(vec_concat:V2HI (const_int 5)
(ss_plus:HI (const_int 7)
(vec_select:HI (match_dup 2) (parallel [(const_int 4)])) (const_int 9)
(vec_select:HI (match_dup 2) (parallel [(const_int 5)]))) (const_int 11)
(ss_plus:HI (const_int 13)
(vec_select:HI (match_dup 2) (parallel [(const_int 6)])) (const_int 15)
(vec_select:HI (match_dup 2) (parallel [(const_int 7)]))))) (const_int 17)
(vec_concat:V4HI (const_int 19)
(vec_concat:V2HI (const_int 21)
(ss_plus:HI (const_int 23)
(vec_select:HI (match_dup 2) (parallel [(const_int 8)])) (const_int 25)
(vec_select:HI (match_dup 2) (parallel [(const_int 9)]))) (const_int 27)
(ss_plus:HI (const_int 29)
(vec_select:HI (match_dup 2) (parallel [(const_int 10)])) (const_int 31)])))
(vec_select:HI (match_dup 2) (parallel [(const_int 11)])))) (sign_extend:V16HI
(vec_concat:V2HI (vec_select:V16QI (match_dup 2)
(ss_plus:HI (parallel [(const_int 1)
(vec_select:HI (match_dup 2) (parallel [(const_int 12)])) (const_int 3)
(vec_select:HI (match_dup 2) (parallel [(const_int 13)]))) (const_int 5)
(ss_plus:HI (const_int 7)
(vec_select:HI (match_dup 2) (parallel [(const_int 14)])) (const_int 9)
(vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))] (const_int 11)
(const_int 13)
(const_int 15)
(const_int 17)
(const_int 19)
(const_int 21)
(const_int 23)
(const_int 25)
(const_int 27)
(const_int 29)
(const_int 31)]))))))]
"TARGET_AVX2" "TARGET_AVX2"
"vphaddsw\t{%2, %1, %0|%0, %1, %2}" "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex") (set_attr "prefix" "vex")
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_insn "ssse3_phaddswv8hi3" (define_insn "ssse3_pmaddubsw128"
[(set (match_operand:V8HI 0 "register_operand" "=x,x") [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI (ss_plus:V8HI
(vec_concat:V4HI (mult:V8HI
(vec_concat:V2HI (zero_extend:V8HI
(ss_plus:HI (vec_select:V8QI
(vec_select:HI (match_operand:V16QI 1 "register_operand" "0,x")
(match_operand:V8HI 1 "register_operand" "0,x") (parallel [(const_int 0)
(parallel [(const_int 0)])) (const_int 2)
(vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (const_int 4)
(ss_plus:HI (const_int 6)
(vec_select:HI (match_dup 1) (parallel [(const_int 2)])) (const_int 8)
(vec_select:HI (match_dup 1) (parallel [(const_int 3)])))) (const_int 10)
(vec_concat:V2HI (const_int 12)
(ss_plus:HI (const_int 14)])))
(vec_select:HI (match_dup 1) (parallel [(const_int 4)])) (sign_extend:V8HI
(vec_select:HI (match_dup 1) (parallel [(const_int 5)]))) (vec_select:V8QI
(ss_plus:HI (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")
(vec_select:HI (match_dup 1) (parallel [(const_int 6)])) (parallel [(const_int 0)
(vec_select:HI (match_dup 1) (parallel [(const_int 7)]))))) (const_int 2)
(vec_concat:V4HI (const_int 4)
(vec_concat:V2HI (const_int 6)
(ss_plus:HI (const_int 8)
(vec_select:HI (const_int 10)
(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") (const_int 12)
(parallel [(const_int 0)])) (const_int 14)]))))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (mult:V8HI
(ss_plus:HI (zero_extend:V8HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (vec_select:V8QI (match_dup 1)
(vec_select:HI (match_dup 2) (parallel [(const_int 3)])))) (parallel [(const_int 1)
(vec_concat:V2HI (const_int 3)
(ss_plus:HI (const_int 5)
(vec_select:HI (match_dup 2) (parallel [(const_int 4)])) (const_int 7)
(vec_select:HI (match_dup 2) (parallel [(const_int 5)]))) (const_int 9)
(ss_plus:HI (const_int 11)
(vec_select:HI (match_dup 2) (parallel [(const_int 6)])) (const_int 13)
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))] (const_int 15)])))
(sign_extend:V8HI
(vec_select:V8QI (match_dup 2)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)
(const_int 9)
(const_int 11)
(const_int 13)
(const_int 15)]))))))]
"TARGET_SSSE3" "TARGET_SSSE3"
"@ "@
phaddsw\t{%2, %0|%0, %2} pmaddubsw\t{%2, %0|%0, %2}
vphaddsw\t{%2, %1, %0|%0, %1, %2}" vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx") [(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd") (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex") (set_attr "atom_unit" "simul")
(set_attr "prefix_data16" "1,*") (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "ssse3_phaddswv4hi3" (define_insn "ssse3_pmaddubsw"
[(set (match_operand:V4HI 0 "register_operand" "=y") [(set (match_operand:V4HI 0 "register_operand" "=y")
(vec_concat:V4HI (ss_plus:V4HI
(vec_concat:V2HI (mult:V4HI
(ss_plus:HI (zero_extend:V4HI
(vec_select:HI (vec_select:V4QI
(match_operand:V4HI 1 "register_operand" "0") (match_operand:V8QI 1 "register_operand" "0")
(parallel [(const_int 0)])) (parallel [(const_int 0)
(vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (const_int 2)
(ss_plus:HI (const_int 4)
(vec_select:HI (match_dup 1) (parallel [(const_int 2)])) (const_int 6)])))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)])))) (sign_extend:V4HI
(vec_concat:V2HI (vec_select:V4QI
(ss_plus:HI (match_operand:V8QI 2 "nonimmediate_operand" "ym")
(vec_select:HI (parallel [(const_int 0)
(match_operand:V4HI 2 "nonimmediate_operand" "ym") (const_int 2)
(parallel [(const_int 0)])) (const_int 4)
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (const_int 6)]))))
(ss_plus:HI (mult:V4HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (zero_extend:V4HI
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))] (vec_select:V4QI (match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)])))
(sign_extend:V4HI
(vec_select:V4QI (match_dup 2)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)]))))))]
"TARGET_SSSE3" "TARGET_SSSE3"
"phaddsw\t{%2, %0|%0, %2}" "pmaddubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex") (set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "avx2_phsubwv16hi3"
[(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_concat:V16HI
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
(match_operand:V16HI 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
(match_operand:V16HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
"TARGET_AVX2"
"vphsubw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(define_insn "ssse3_phsubwv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
(match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
"@
phsubw\t{%2, %0|%0, %2}
vphsubw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubwv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
(match_operand:V4HI 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(minus:HI
(vec_select:HI
(match_operand:V4HI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3"
"phsubw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "avx2_phsubdv8si3"
[(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_concat:V8SI
(vec_concat:V4SI
(vec_concat:V2SI
(minus:SI
(vec_select:SI
(match_operand:V8SI 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(minus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI
(minus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
(minus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4SI
(vec_concat:V2SI
(minus:SI
(vec_select:SI
(match_operand:V8SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(minus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2SI
(minus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 5)])))
(minus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_AVX2"
"vphsubd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(define_insn "ssse3_phsubdv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_concat:V4SI
(vec_concat:V2SI
(minus:SI
(vec_select:SI
(match_operand:V4SI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(minus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI
(minus:SI
(vec_select:SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(minus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3"
"@
phsubd\t{%2, %0|%0, %2}
vphsubd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubdv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(vec_concat:V2SI
(minus:SI
(vec_select:SI
(match_operand:V2SI 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(minus:SI
(vec_select:SI
(match_operand:V2SI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSSE3"
"phsubd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "avx2_phsubswv16hi3"
[(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_concat:V16HI
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
(match_operand:V16HI 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
(match_operand:V16HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
"TARGET_AVX2"
"vphsubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(define_insn "ssse3_phsubswv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
(match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
"@
phsubsw\t{%2, %0|%0, %2}
vphsubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubswv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
(match_operand:V4HI 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
(match_operand:V4HI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3"
"phsubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "avx2_pmaddubsw256"
[(set (match_operand:V16HI 0 "register_operand" "=x")
(ss_plus:V16HI
(mult:V16HI
(zero_extend:V16HI
(vec_select:V16QI
(match_operand:V32QI 1 "register_operand" "x")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)
(const_int 8)
(const_int 10)
(const_int 12)
(const_int 14)
(const_int 16)
(const_int 18)
(const_int 20)
(const_int 22)
(const_int 24)
(const_int 26)
(const_int 28)
(const_int 30)])))
(sign_extend:V16HI
(vec_select:V16QI
(match_operand:V32QI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)
(const_int 8)
(const_int 10)
(const_int 12)
(const_int 14)
(const_int 16)
(const_int 18)
(const_int 20)
(const_int 22)
(const_int 24)
(const_int 26)
(const_int 28)
(const_int 30)]))))
(mult:V16HI
(zero_extend:V16HI
(vec_select:V16QI (match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)
(const_int 9)
(const_int 11)
(const_int 13)
(const_int 15)
(const_int 17)
(const_int 19)
(const_int 21)
(const_int 23)
(const_int 25)
(const_int 27)
(const_int 29)
(const_int 31)])))
(sign_extend:V16HI
(vec_select:V16QI (match_dup 2)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)
(const_int 9)
(const_int 11)
(const_int 13)
(const_int 15)
(const_int 17)
(const_int 19)
(const_int 21)
(const_int 23)
(const_int 25)
(const_int 27)
(const_int 29)
(const_int 31)]))))))]
"TARGET_AVX2"
"vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(define_insn "ssse3_pmaddubsw128"
[(set (match_operand:V8HI 0 "register_operand" "=x,x")
(ss_plus:V8HI
(mult:V8HI
(zero_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "register_operand" "0,x")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)
(const_int 8)
(const_int 10)
(const_int 12)
(const_int 14)])))
(sign_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)
(const_int 8)
(const_int 10)
(const_int 12)
(const_int 14)]))))
(mult:V8HI
(zero_extend:V8HI
(vec_select:V8QI (match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)
(const_int 9)
(const_int 11)
(const_int 13)
(const_int 15)])))
(sign_extend:V8HI
(vec_select:V8QI (match_dup 2)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)
(const_int 9)
(const_int 11)
(const_int 13)
(const_int 15)]))))))]
"TARGET_SSSE3"
"@
pmaddubsw\t{%2, %0|%0, %2}
vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_pmaddubsw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(ss_plus:V4HI
(mult:V4HI
(zero_extend:V4HI
(vec_select:V4QI
(match_operand:V8QI 1 "register_operand" "0")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)])))
(sign_extend:V4HI
(vec_select:V4QI
(match_operand:V8QI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)]))))
(mult:V4HI
(zero_extend:V4HI
(vec_select:V4QI (match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)])))
(sign_extend:V4HI
(vec_select:V4QI (match_dup 2)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)]))))))]
"TARGET_SSSE3"
"pmaddubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
...@@ -9314,7 +8756,8 @@ ...@@ -9314,7 +8756,8 @@
(define_insn "<ssse3_avx2>_pshufb<mode>3" (define_insn "<ssse3_avx2>_pshufb<mode>3"
[(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x") [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
(unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,x") (unspec:VI1_AVX2
[(match_operand:VI1_AVX2 1 "register_operand" "0,x")
(match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")] (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_PSHUFB))] UNSPEC_PSHUFB))]
"TARGET_SSSE3" "TARGET_SSSE3"
...@@ -9372,7 +8815,8 @@ ...@@ -9372,7 +8815,8 @@
(define_insn "<ssse3_avx2>_palignr<mode>" (define_insn "<ssse3_avx2>_palignr<mode>"
[(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x") [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x")
(unspec:SSESCALARMODE [(match_operand:SSESCALARMODE 1 "register_operand" "0,x") (unspec:SSESCALARMODE
[(match_operand:SSESCALARMODE 1 "register_operand" "0,x")
(match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm") (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm")
(match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
UNSPEC_PALIGNR))] UNSPEC_PALIGNR))]
...@@ -9595,7 +9039,8 @@ ...@@ -9595,7 +9039,8 @@
(define_insn "<sse4_1_avx2>_mpsadbw" (define_insn "<sse4_1_avx2>_mpsadbw"
[(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x") [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
(unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,x") (unspec:VI1_AVX2
[(match_operand:VI1_AVX2 1 "register_operand" "0,x")
(match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm") (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")
(match_operand:SI 3 "const_0_to_255_operand" "n,n")] (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
UNSPEC_MPSADBW))] UNSPEC_MPSADBW))]
...@@ -10396,78 +9841,51 @@ ...@@ -10396,78 +9841,51 @@
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_code_iterator xop_plus [plus ss_plus])
(define_code_attr macs [(plus "macs") (ss_plus "macss")])
(define_code_attr madcs [(plus "madcs") (ss_plus "madcss")])
;; XOP parallel integer multiply/add instructions. ;; XOP parallel integer multiply/add instructions.
;; Note the XOP multiply/add instructions ;; Note the XOP multiply/add instructions
;; a[i] = b[i] * c[i] + d[i]; ;; a[i] = b[i] * c[i] + d[i];
;; do not allow the value being added to be a memory operation. ;; do not allow the value being added to be a memory operation.
(define_insn "xop_pmacsww"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(plus:V8HI
(mult:V8HI
(match_operand:V8HI 1 "nonimmediate_operand" "%x")
(match_operand:V8HI 2 "nonimmediate_operand" "xm"))
(match_operand:V8HI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmacsww\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
(define_insn "xop_pmacssww"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ss_plus:V8HI
(mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
(match_operand:V8HI 2 "nonimmediate_operand" "xm"))
(match_operand:V8HI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmacssww\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
(define_insn "xop_pmacsdd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI
(mult:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "%x")
(match_operand:V4SI 2 "nonimmediate_operand" "xm"))
(match_operand:V4SI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmacsdd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
(define_insn "xop_pmacssdd" (define_insn "xop_p<macs><ssemodesuffix><ssemodesuffix>"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:VI24_128 0 "register_operand" "=x")
(ss_plus:V4SI (xop_plus:VI24_128
(mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x") (mult:VI24_128
(match_operand:V4SI 2 "nonimmediate_operand" "xm")) (match_operand:VI24_128 1 "nonimmediate_operand" "%x")
(match_operand:V4SI 3 "nonimmediate_operand" "x")))] (match_operand:VI24_128 2 "nonimmediate_operand" "xm"))
(match_operand:VI24_128 3 "nonimmediate_operand" "x")))]
"TARGET_XOP" "TARGET_XOP"
"vpmacssdd\t{%3, %2, %1, %0|%0, %1, %2, %3}" "vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd") [(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "xop_pmacssdql" (define_insn "xop_p<macs>dql"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(ss_plus:V2DI (xop_plus:V2DI
(mult:V2DI (mult:V2DI
(sign_extend:V2DI (sign_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "%x") (match_operand:V4SI 1 "nonimmediate_operand" "%x")
(parallel [(const_int 1) (parallel [(const_int 1)
(const_int 3)]))) (const_int 3)])))
(sign_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm") (match_operand:V4SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 1) (parallel [(const_int 1)
(const_int 3)]))) (const_int 3)]))))
(match_operand:V2DI 3 "nonimmediate_operand" "x")))] (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP" "TARGET_XOP"
"vpmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}" "vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd") [(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "xop_pmacssdqh" (define_insn "xop_p<macs>dqh"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(ss_plus:V2DI (xop_plus:V2DI
(mult:V2DI (mult:V2DI
(sign_extend:V2DI (sign_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
...@@ -10481,27 +9899,7 @@ ...@@ -10481,27 +9899,7 @@
(const_int 2)])))) (const_int 2)]))))
(match_operand:V2DI 3 "nonimmediate_operand" "x")))] (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP" "TARGET_XOP"
"vpmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}" "vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
(define_insn "xop_pmacsdql"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "%x")
(parallel [(const_int 1)
(const_int 3)])))
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 1)
(const_int 3)]))))
(match_operand:V2DI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd") [(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
...@@ -10547,26 +9945,6 @@ ...@@ -10547,26 +9945,6 @@
[(set_attr "type" "ssemul") [(set_attr "type" "ssemul")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "xop_pmacsdqh"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "%x")
(parallel [(const_int 0)
(const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 2)]))))
(match_operand:V2DI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
;; We don't have a straight 32-bit parallel multiply and extend on XOP, so ;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
;; fake it with a multiply/add. In general, we expect the define_split to ;; fake it with a multiply/add. In general, we expect the define_split to
;; occur before register allocation, so we have to handle the corner case where ;; occur before register allocation, so we have to handle the corner case where
...@@ -10603,40 +9981,16 @@ ...@@ -10603,40 +9981,16 @@
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 2)])))) (const_int 2)]))))
(match_dup 0)))] (match_dup 0)))]
{ {
operands[3] = CONST0_RTX (V2DImode); operands[3] = CONST0_RTX (V2DImode);
} }
[(set_attr "type" "ssemul") [(set_attr "type" "ssemul")
(set_attr "mode" "TI")])
;; XOP parallel integer multiply/add instructions for the intrinisics
(define_insn "xop_pmacsswd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ss_plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "%x")
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)]))))
(match_operand:V4SI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmacsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "xop_pmacswd" ;; XOP parallel integer multiply/add instructions for the intrinisics
(define_insn "xop_p<macs>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI (xop_plus:V4SI
(mult:V4SI (mult:V4SI
(sign_extend:V4SI (sign_extend:V4SI
(vec_select:V4HI (vec_select:V4HI
...@@ -10654,53 +10008,13 @@ ...@@ -10654,53 +10008,13 @@
(const_int 7)])))) (const_int 7)]))))
(match_operand:V4SI 3 "nonimmediate_operand" "x")))] (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP" "TARGET_XOP"
"vpmacswd\t{%3, %2, %1, %0|%0, %1, %2, %3}" "vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
(define_insn "xop_pmadcsswd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ss_plus:V4SI
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "%x")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)]))))
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_dup 2)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)])))))
(match_operand:V4SI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP"
"vpmadcsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd") [(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "xop_pmadcswd" (define_insn "xop_p<madcs>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI (xop_plus:V4SI
(plus:V4SI (plus:V4SI
(mult:V4SI (mult:V4SI
(sign_extend:V4SI (sign_extend:V4SI
...@@ -10734,7 +10048,7 @@ ...@@ -10734,7 +10048,7 @@
(const_int 7)]))))) (const_int 7)])))))
(match_operand:V4SI 3 "nonimmediate_operand" "x")))] (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
"TARGET_XOP" "TARGET_XOP"
"vpmadcswd\t{%3, %2, %1, %0|%0, %1, %2, %3}" "vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd") [(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
...@@ -10750,196 +10064,10 @@ ...@@ -10750,196 +10064,10 @@
[(set_attr "type" "sse4arg")]) [(set_attr "type" "sse4arg")])
;; XOP horizontal add/subtract instructions ;; XOP horizontal add/subtract instructions
(define_insn "xop_phaddbw" (define_insn "xop_phadd<u>bw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(plus:V8HI
(sign_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)
(const_int 8)
(const_int 10)
(const_int 12)
(const_int 14)])))
(sign_extend:V8HI
(vec_select:V8QI
(match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)
(const_int 9)
(const_int 11)
(const_int 13)
(const_int 15)])))))]
"TARGET_XOP"
"vphaddbw\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddbd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI
(plus:V4SI
(sign_extend:V4SI
(vec_select:V4QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 4)
(const_int 8)
(const_int 12)])))
(sign_extend:V4SI
(vec_select:V4QI
(match_dup 1)
(parallel [(const_int 1)
(const_int 5)
(const_int 9)
(const_int 13)]))))
(plus:V4SI
(sign_extend:V4SI
(vec_select:V4QI
(match_dup 1)
(parallel [(const_int 2)
(const_int 6)
(const_int 10)
(const_int 14)])))
(sign_extend:V4SI
(vec_select:V4QI
(match_dup 1)
(parallel [(const_int 3)
(const_int 7)
(const_int 11)
(const_int 15)]))))))]
"TARGET_XOP"
"vphaddbd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddbq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(plus:V2DI
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 4)])))
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 1)
(const_int 5)]))))
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 2)
(const_int 6)])))
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 3)
(const_int 7)])))))
(plus:V2DI
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 8)
(const_int 12)])))
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 9)
(const_int 13)]))))
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 10)
(const_int 14)])))
(sign_extend:V2DI
(vec_select:V2QI
(match_dup 1)
(parallel [(const_int 11)
(const_int 15)])))))))]
"TARGET_XOP"
"vphaddbq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddwd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_dup 1)
(parallel [(const_int 1)
(const_int 3)
(const_int 5)
(const_int 7)])))))]
"TARGET_XOP"
"vphaddwd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddwq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 4)])))
(sign_extend:V2DI
(vec_select:V2HI
(match_dup 1)
(parallel [(const_int 1)
(const_int 5)]))))
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2HI
(match_dup 1)
(parallel [(const_int 2)
(const_int 6)])))
(sign_extend:V2DI
(vec_select:V2HI
(match_dup 1)
(parallel [(const_int 3)
(const_int 7)]))))))]
"TARGET_XOP"
"vphaddwq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phadddq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
(match_dup 1)
(parallel [(const_int 1)
(const_int 3)])))))]
"TARGET_XOP"
"vphadddq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddubw"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(plus:V8HI (plus:V8HI
(zero_extend:V8HI (any_extend:V8HI
(vec_select:V8QI (vec_select:V8QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (parallel [(const_int 0)
...@@ -10950,7 +10078,7 @@ ...@@ -10950,7 +10078,7 @@
(const_int 10) (const_int 10)
(const_int 12) (const_int 12)
(const_int 14)]))) (const_int 14)])))
(zero_extend:V8HI (any_extend:V8HI
(vec_select:V8QI (vec_select:V8QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (parallel [(const_int 1)
...@@ -10962,21 +10090,21 @@ ...@@ -10962,21 +10090,21 @@
(const_int 13) (const_int 13)
(const_int 15)])))))] (const_int 15)])))))]
"TARGET_XOP" "TARGET_XOP"
"vphaddubw\t{%1, %0|%0, %1}" "vphadd<u>bw\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")]) [(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddubd" (define_insn "xop_phadd<u>bd"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI (plus:V4SI
(plus:V4SI (plus:V4SI
(zero_extend:V4SI (any_extend:V4SI
(vec_select:V4QI (vec_select:V4QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 4) (const_int 4)
(const_int 8) (const_int 8)
(const_int 12)]))) (const_int 12)])))
(zero_extend:V4SI (any_extend:V4SI
(vec_select:V4QI (vec_select:V4QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (parallel [(const_int 1)
...@@ -10984,14 +10112,14 @@ ...@@ -10984,14 +10112,14 @@
(const_int 9) (const_int 9)
(const_int 13)])))) (const_int 13)]))))
(plus:V4SI (plus:V4SI
(zero_extend:V4SI (any_extend:V4SI
(vec_select:V4QI (vec_select:V4QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 2) (parallel [(const_int 2)
(const_int 6) (const_int 6)
(const_int 10) (const_int 10)
(const_int 14)]))) (const_int 14)])))
(zero_extend:V4SI (any_extend:V4SI
(vec_select:V4QI (vec_select:V4QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 3) (parallel [(const_int 3)
...@@ -10999,73 +10127,73 @@ ...@@ -10999,73 +10127,73 @@
(const_int 11) (const_int 11)
(const_int 15)]))))))] (const_int 15)]))))))]
"TARGET_XOP" "TARGET_XOP"
"vphaddubd\t{%1, %0|%0, %1}" "vphadd<u>bd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")]) [(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddubq" (define_insn "xop_phadd<u>bq"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI (plus:V2DI
(plus:V2DI (plus:V2DI
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 4)]))) (const_int 4)])))
(sign_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (parallel [(const_int 1)
(const_int 5)])))) (const_int 5)]))))
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 2) (parallel [(const_int 2)
(const_int 6)]))) (const_int 6)])))
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 3) (parallel [(const_int 3)
(const_int 7)]))))) (const_int 7)])))))
(plus:V2DI (plus:V2DI
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 8) (parallel [(const_int 8)
(const_int 12)]))) (const_int 12)])))
(sign_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 9) (parallel [(const_int 9)
(const_int 13)])))) (const_int 13)]))))
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 10) (parallel [(const_int 10)
(const_int 14)]))) (const_int 14)])))
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_dup 1) (match_dup 1)
(parallel [(const_int 11) (parallel [(const_int 11)
(const_int 15)])))))))] (const_int 15)])))))))]
"TARGET_XOP" "TARGET_XOP"
"vphaddubq\t{%1, %0|%0, %1}" "vphadd<u>bq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")]) [(set_attr "type" "sseiadd1")])
(define_insn "xop_phadduwd" (define_insn "xop_phadd<u>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI (plus:V4SI
(zero_extend:V4SI (any_extend:V4SI
(vec_select:V4HI (vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm") (match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 2) (const_int 2)
(const_int 4) (const_int 4)
(const_int 6)]))) (const_int 6)])))
(zero_extend:V4SI (any_extend:V4SI
(vec_select:V4HI (vec_select:V4HI
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (parallel [(const_int 1)
...@@ -11073,53 +10201,53 @@ ...@@ -11073,53 +10201,53 @@
(const_int 5) (const_int 5)
(const_int 7)])))))] (const_int 7)])))))]
"TARGET_XOP" "TARGET_XOP"
"vphadduwd\t{%1, %0|%0, %1}" "vphadd<u>wd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")]) [(set_attr "type" "sseiadd1")])
(define_insn "xop_phadduwq" (define_insn "xop_phadd<u>wq"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI (plus:V2DI
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2HI (vec_select:V2HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm") (match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 4)]))) (const_int 4)])))
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2HI (vec_select:V2HI
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (parallel [(const_int 1)
(const_int 5)])))) (const_int 5)]))))
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2HI (vec_select:V2HI
(match_dup 1) (match_dup 1)
(parallel [(const_int 2) (parallel [(const_int 2)
(const_int 6)]))) (const_int 6)])))
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2HI (vec_select:V2HI
(match_dup 1) (match_dup 1)
(parallel [(const_int 3) (parallel [(const_int 3)
(const_int 7)]))))))] (const_int 7)]))))))]
"TARGET_XOP" "TARGET_XOP"
"vphadduwq\t{%1, %0|%0, %1}" "vphadd<u>wq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")]) [(set_attr "type" "sseiadd1")])
(define_insn "xop_phaddudq" (define_insn "xop_phadd<u>dq"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI (plus:V2DI
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm") (match_operand:V4SI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 2)]))) (const_int 2)])))
(zero_extend:V2DI (any_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_dup 1) (match_dup 1)
(parallel [(const_int 1) (parallel [(const_int 1)
(const_int 3)])))))] (const_int 3)])))))]
"TARGET_XOP" "TARGET_XOP"
"vphaddudq\t{%1, %0|%0, %1}" "vphadd<u>dq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")]) [(set_attr "type" "sseiadd1")])
(define_insn "xop_phsubbw" (define_insn "xop_phsubbw"
......
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