[AArch64] PR target/79913: VEC_SELECT bugs in aarch64 patterns

	PR target/79913
	* config/aarch64/iterators.md (VALL_F16_NO_V2Q): New mode iterator.
	(VALL_NO_V2Q): Likewise.
	(VDQF_DF): Delete.
	* config/aarch64/aarch64-simd.md
	(aarch64_dup_lane_<vswap_width_name><mode>): Use VALL_F16_NO_V2Q
	iterator.
	(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Use
	VALL_NO_V2Q mode iterator.
	(*aarch64_vgetfmulx<mode>): Use VDQF iterator.

From-SVN: r245999

gcc/ChangeLog

+2017-03-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/79913
+	* config/aarch64/iterators.md (VALL_F16_NO_V2Q): New mode iterator.
+	(VALL_NO_V2Q): Likewise.
+	(VDQF_DF): Delete.
+	* config/aarch64/aarch64-simd.md
+	(aarch64_dup_lane_<vswap_width_name><mode>): Use VALL_F16_NO_V2Q
+	iterator.
+	(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Use
+	VALL_NO_V2Q mode iterator.
+	(*aarch64_vgetfmulx<mode>): Use VDQF iterator.
+
 2017-03-09  Martin Liska  <mliska@suse.cz>
 
 	PR tree-optimization/79631

gcc/config/aarch64/aarch64-simd.md

@@ -77,8 +77,8 @@
 )
 
 (define_insn "aarch64_dup_lane_<vswap_width_name><mode>"
-  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
-	(vec_duplicate:VALL_F16
+  [(set (match_operand:VALL_F16_NO_V2Q 0 "register_operand" "=w")
+	(vec_duplicate:VALL_F16_NO_V2Q
 	  (vec_select:<VEL>
 	    (match_operand:<VSWAP_WIDTH> 1 "register_operand" "w")
 	    (parallel [(match_operand:SI 2 "immediate_operand" "i")])
@@ -586,14 +586,14 @@
 )
 
 (define_insn "*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>"
-  [(set (match_operand:VALL 0 "register_operand" "=w")
-	(vec_merge:VALL
-	    (vec_duplicate:VALL
+  [(set (match_operand:VALL_F16_NO_V2Q 0 "register_operand" "=w")
+	(vec_merge:VALL_F16_NO_V2Q
+	    (vec_duplicate:VALL_F16_NO_V2Q
 	      (vec_select:<VEL>
 		(match_operand:<VSWAP_WIDTH> 3 "register_operand" "w")
 		(parallel
 		  [(match_operand:SI 4 "immediate_operand" "i")])))
-	    (match_operand:VALL 1 "register_operand" "0")
+	    (match_operand:VALL_F16_NO_V2Q 1 "register_operand" "0")
 	    (match_operand:SI 2 "immediate_operand" "i")))]
   "TARGET_SIMD"
   {
@@ -3194,7 +3194,7 @@
 	(unspec:<VEL>
 	 [(match_operand:<VEL> 1 "register_operand" "w")
 	  (vec_select:<VEL>
-	   (match_operand:VDQF_DF 2 "register_operand" "w")
+	   (match_operand:VDQF 2 "register_operand" "w")
 	    (parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
 	 UNSPEC_FMULX))]
   "TARGET_SIMD"

gcc/config/aarch64/iterators.md

@@ -101,7 +101,6 @@
 			     V2SF V4SF V2DF])
 
 ;; Vector Float modes, and DF.
-(define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
 				(V8HF "TARGET_SIMD_F16INST")
 				V2SF V4SF V2DF DF])
@@ -133,6 +132,10 @@
 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 				V4HF V8HF V2SF V4SF V2DF])
 
+;; The VALL_F16 modes except the 128-bit 2-element ones.
+(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
+				V4HF V8HF V2SF V4SF])
+
 ;; All vector modes barring HF modes, plus DI.
 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])