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riscv-gcc-1
Commit 8690fedf by Richard Kenner
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(cmphf): Addd Base Reg with Offset address mode (LB,STB,..) 

(cmphf): Addd Base Reg with Offset address mode (LB,STB,..)
(movqi,movhi,movhf,addqi3,addhf3,subqi3,subhf3,mulqihi3): Likewise.
(mulhf3,divhf3,andqi3,iorqi3): Likewise.
(define_peephole): Remove the Base mode peepholes. Replace the
special addqi define_insn for "LIM Ra,sym,Rb" by a define_peephole.
(ashlqi3): Took out futile 0th alternative.
(lshrqi3, lshrhi3, ashrqi3, ahsrhi3): Correct case of non-constant
shift count.

From-SVN: r10575
parent 67ca0b22
Showing with 174 additions and 146 deletions
gcc/config/1750a/1750a.md
......@@ -234,11 +234,12 @@
(define_insn "cmphf"
[(set (cc0)
(compare (match_operand:HF 0 "general_operand" "r,r")
(match_operand:HF 1 "general_operand" "r,m")))]
(compare (match_operand:HF 0 "general_operand" "r,z,r")
(match_operand:HF 1 "general_operand" "r,Q,m")))]
""
"@
fcr r%0,r%1
fcb %Q1
fc r%0,%1 ")
(define_insn "cmptqf"
......@@ -367,8 +368,8 @@
;; 16-bit moves
(define_insn "movqi"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m")
(match_operand:QI 1 "general_operand" "O,I,J,M,i,r,m,r,K"))]
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,t,r,Q,m,m")
(match_operand:QI 1 "general_operand" "O,I,J,M,i,r,Q,m,t,r,K"))]
""
"@
xorr r%0,r%0
......@@ -377,7 +378,9 @@
lim r%0,%1 ; 'M' constraint
lim r%0,%1 ; 'i' constraint
lr r%0,r%1
lb %Q1
l r%0,%1
stb %Q0
st r%1,%0
stc %1,%0 ")
......@@ -418,12 +421,14 @@
")
(define_insn "movhi"
[(set (match_operand:HI 0 "general_operand" "=r,r,m")
(match_operand:HI 1 "general_operand" "r,m,r"))]
[(set (match_operand:HI 0 "general_operand" "=r,z,r,Q,m")
(match_operand:HI 1 "general_operand" "r,Q,m,z,r"))]
""
"@
dlr r%0,r%1
dlb %Q1
dl r%0,%1
dstb %Q0
dst r%1,%0 ")
......@@ -440,12 +445,14 @@
; dst r%1,%0 ")
(define_insn "movhf"
[(set (match_operand:HF 0 "general_operand" "=r,r,m")
(match_operand:HF 1 "general_operand" "r,m,r"))]
[(set (match_operand:HF 0 "general_operand" "=r,z,r,Q,m")
(match_operand:HF 1 "general_operand" "r,Q,m,z,r"))]
""
"@
dlr r%0,r%1
dlb %Q1
dl r%0,%1
dstb %Q0
dst r%1,%0 ")
......@@ -475,19 +482,10 @@
;; single integer
;; Use "LIM Ra,sym,Rb" for adding a symbol value to a register and
;; transferring the result to a different register.
;(define_insn ""
; [(set (match_operand:QI 0 "register_operand" "=r")
; (plus:QI (match_operand:QI 1 "register_operand" "b")
; (match_operand:QI 2 "immediate_operand" "i")))]
; "REGNO(operands[0]) != REGNO(operands[1])"
; "lim r%0,%2,r%1 ;md special addqi")
(define_insn "addqi3"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
(match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))]
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,t,r,m,m")
(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0,0")
(match_operand:QI 2 "general_operand" "I,J,i,r,Q,m,I,J")))]
""
"*
switch (which_alternative)
......@@ -504,10 +502,12 @@
case 3:
return \"ar r%0,r%2\";
case 4:
return \"a r%0,%2\";
return \"ab %Q2\";
case 5:
return \"incm %2,%0\";
return \"a r%0,%2\";
case 6:
return \"incm %2,%0\";
case 7:
return \"decm %J2,%0\";
} ")
......@@ -522,36 +522,38 @@
da r%0,%2 ")
(define_insn "addhf3"
[(set (match_operand:HF 0 "register_operand" "=r,r")
(plus:HF (match_operand:HF 1 "register_operand" "%0,0")
(match_operand:HF 2 "general_operand" "m,r")))]
[(set (match_operand:HF 0 "register_operand" "=r,z,r")
(plus:HF (match_operand:HF 1 "register_operand" "%0,0,0")
(match_operand:HF 2 "general_operand" "r,Q,m")))]
""
"@
fa r%0,%2
far r%0,r%2 ")
far r%0,r%2
fab %Q2
fa r%0,%2 ")
(define_insn "addtqf3"
[(set (match_operand:TQF 0 "register_operand" "=r,r")
(plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
(match_operand:TQF 2 "general_operand" "m,r")))]
(match_operand:TQF 2 "general_operand" "r,m")))]
""
"@
efa r%0,%2
efar r%0,r%2 ")
efar r%0,r%2
efa r%0,%2 ")
;; subtract instructions
;; single integer
(define_insn "subqi3"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
(minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
(match_operand:QI 2 "general_operand" "I,i,r,m,I")))]
[(set (match_operand:QI 0 "general_operand" "=r,r,r,t,r,m")
(minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0,0")
(match_operand:QI 2 "general_operand" "I,i,r,Q,m,I")))]
""
"@
sisp r%0,%2
sim r%0,%2
sr r%0,r%2
sbb %Q2
s r%0,%2
decm %2,%0 ")
......@@ -566,12 +568,13 @@
ds r%0,%2 ")
(define_insn "subhf3"
[(set (match_operand:HF 0 "register_operand" "=r,r")
(minus:HF (match_operand:HF 1 "register_operand" "0,0")
(match_operand:HF 2 "general_operand" "r,m")))]
[(set (match_operand:HF 0 "register_operand" "=r,z,r")
(minus:HF (match_operand:HF 1 "register_operand" "0,0,0")
(match_operand:HF 2 "general_operand" "r,Q,m")))]
""
"@
fsr r%0,r%2
fsb %Q2
fs r%0,%2 ")
(define_insn "subtqf3"
......@@ -601,13 +604,14 @@
; 32-bit product
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
(mult:HI (match_operand:QI 1 "register_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "M,r,m")))]
[(set (match_operand:HI 0 "register_operand" "=r,r,t,r")
(mult:HI (match_operand:QI 1 "register_operand" "%0,0,0,0")
(match_operand:QI 2 "general_operand" "M,r,Q,m")))]
""
"@
mim r%0,%1
mr r%0,r%2
mb %Q2
m r%0,%2 ")
(define_insn "mulhi3"
......@@ -622,12 +626,13 @@
; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
(define_insn "mulhf3"
[(set (match_operand:HF 0 "register_operand" "=r,r")
(mult:HF (match_operand:HF 1 "register_operand" "%0,0")
(match_operand:HF 2 "general_operand" "r,m")))]
[(set (match_operand:HF 0 "register_operand" "=r,z,r")
(mult:HF (match_operand:HF 1 "register_operand" "%0,0,0")
(match_operand:HF 2 "general_operand" "r,Q,m")))]
""
"@
fmr r%0,r%2
fmb %Q2
fm r%0,%2 ")
(define_insn "multqf3"
......@@ -694,12 +699,13 @@
dd r%0,%2 ")
(define_insn "divhf3"
[(set (match_operand:HF 0 "register_operand" "=r,r")
(div:HF (match_operand:HF 1 "register_operand" "0,0")
(match_operand:HF 2 "general_operand" "r,m")))]
[(set (match_operand:HF 0 "register_operand" "=r,z,r")
(div:HF (match_operand:HF 1 "register_operand" "0,0,0")
(match_operand:HF 2 "general_operand" "r,Q,m")))]
""
"@
fdr r%0,r%2
fdb %Q2
fd r%0,%2 ")
(define_insn "divtqf3"
......@@ -773,13 +779,14 @@
;; AND
(define_insn "andqi3"
[(set (match_operand:QI 0 "general_operand" "=r,r,r")
(and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "M,r,m")))]
[(set (match_operand:QI 0 "general_operand" "=r,r,t,r")
(and:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
(match_operand:QI 2 "general_operand" "M,r,Q,m")))]
""
"@
andm r%0,%2
andr r%0,r%2
andb %Q2
and r%0,%2 ")
; This sets incorrect condition codes. See notice_update_cc()
......@@ -793,13 +800,14 @@
;; OR
(define_insn "iorqi3"
[(set (match_operand:QI 0 "general_operand" "=r,r,r")
(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "M,r,m")))]
[(set (match_operand:QI 0 "general_operand" "=r,r,t,r")
(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
(match_operand:QI 2 "general_operand" "M,r,Q,m")))]
""
"@
orim r%0,%2
orr r%0,r%2
orb %Q2
or r%0,%2 ")
; This sets incorrect condition codes. See notice_update_cc()
......@@ -870,12 +878,11 @@
; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
(define_insn "ashlqi3"
[(set (match_operand:QI 0 "register_operand" "=r,r,r")
(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0")
(match_operand:QI 2 "general_operand" "O,I,r")))]
[(set (match_operand:QI 0 "register_operand" "=r,r")
(ashift:QI (match_operand:QI 1 "register_operand" "0,0")
(match_operand:QI 2 "general_operand" "I,r")))]
""
"@
; optimized away an SLL r%0,0
sll r%0,%2
slr r%0,r%2 ")
......@@ -888,41 +895,113 @@
dsll r%0,%2
dslr r%0,r%2 ")
(define_insn "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
(match_operand:QI 2 "general_operand" "I,r")))]
;; Right shift by a variable shiftcount works by negating the shift count,
;; then emitting a right shift with the shift count negated. This means
;; that all actual shift counts in the RTL will be positive. This
;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
;; which isn't valid.
(define_expand "lshrqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
"@
srl r%0,%2
neg r%2,r%2\;slr r%0,r%2 ")
"
{
if (GET_CODE (operands[2]) != CONST_INT)
operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
}")
(define_insn "lshrhi3"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
(match_operand:QI 2 "general_operand" "L,r")))]
"" ; the 'L' constraint is a slight imprecise...
"@
dsrl r%0,%2
neg r%2,r%2\;dslr r%0,r%2 ")
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "immediate_operand" "I")))]
""
"srl r%0,%1")
(define_insn "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
(match_operand:QI 2 "general_operand" "I,r")))]
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
(neg:QI (match_operand:QI 2 "register_operand" "r"))))]
""
"@
sra r%0,%2
neg r%2,r%2\;sar r%0,r%2 ")
"slr r%0,r%2 ")
(define_insn "ashrhi3"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
(match_operand:QI 2 "general_operand" "I,r")))]
;; Same thing for HImode.
(define_expand "lshrhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
"@
dsra r%0,%2
neg r%2,r%2\;dsar r%0,r%2 ")
"
{
if (GET_CODE (operands[2]) != CONST_INT)
operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
}")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "immediate_operand" "L")))]
""
"dsrl r%0,%1")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
(neg:QI (match_operand:QI 2 "register_operand" "r"))))]
""
"dslr r%0,r%2 ")
;; Same applies for arithmetic shift right.
(define_expand "ashrqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
"
{
if (GET_CODE (operands[2]) != CONST_INT)
operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
}")
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "immediate_operand" "I")))]
""
"sra r%0,%1")
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
(neg:QI (match_operand:QI 2 "register_operand" "r"))))]
""
"sar r%0,r%2 ")
;; HImode arithmetic shift right.
(define_expand "ashrhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
"
{
if (GET_CODE (operands[2]) != CONST_INT)
operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
}")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "immediate_operand" "L")))]
""
"dsra r%0,%1")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
(neg:QI (match_operand:QI 2 "register_operand" "r"))))]
""
"dsar r%0,r%2 ")
;; rotate instructions
......@@ -969,7 +1048,7 @@
;********************
;; Bit field instructions, general cases.
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; "o,d" constraint causes a nonoffsetable memref to match the "o"
;; so that its address is reloaded.
;; (define_insn "extv" ...
......@@ -1275,63 +1354,15 @@
"INTVAL(operands[2]) == -1"
"soj r%0,%3")
;; Load Base
;; Combine a Load Register with subsequent increment/decrement into a LIM
(define_peephole
[(set (match_operand:QI 0 "register_operand" "=r")
(mem:QI (plus:QI (match_operand:QI 1 "register_operand" "x")
(match_operand:QI 2 "immediate_operand" "L"))))
]
"REGNO(operands[0]) == 2 && REGNO(operands[1]) >= 12
&& INTVAL(operands[2]) <= 255"
"lb r%1,%2")
;; Double Load Base
(define_peephole
[(set (match_operand:HI 0 "register_operand" "=r")
(mem:HI (plus:QI (match_operand:QI 1 "register_operand" "x")
(match_operand:QI 2 "immediate_operand" "L"))))
]
"REGNO(operands[0]) == 0 && REGNO(operands[1]) >= 12
&& INTVAL(operands[2]) <= 255"
"dlb r%1,%2")
(define_peephole
[(set (match_operand:HF 0 "register_operand" "=r")
(mem:HF (plus:QI (match_operand:QI 1 "register_operand" "x")
(match_operand:QI 2 "immediate_operand" "L"))))
]
"REGNO(operands[0]) == 0 && REGNO(operands[1]) >= 12
&& INTVAL(operands[2]) <= 255"
"dlb r%1,%2")
;; Store Base
(define_peephole
[(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "x")
(match_operand:QI 1 "immediate_operand" "L")))
(match_operand:QI 2 "register_operand" "r"))
]
"REGNO(operands[2]) == 2 && REGNO(operands[0]) >= 12
&& INTVAL(operands[1]) <= 255"
"stb r%0,%1")
;; Double Store Base
(define_peephole
[(set (mem:HI (plus:QI (match_operand:QI 0 "register_operand" "x")
(match_operand:QI 1 "immediate_operand" "L")))
(match_operand:HI 2 "register_operand" "r"))
]
"REGNO(operands[2]) == 0 && REGNO(operands[0]) >= 12
&& INTVAL(operands[1]) <= 255"
"dstb r%0,%1")
(define_peephole
[(set (mem:HF (plus:QI (match_operand:QI 0 "register_operand" "x")
(match_operand:QI 1 "immediate_operand" "L")))
(match_operand:HF 2 "register_operand" "r"))
]
"REGNO(operands[2]) == 0 && REGNO(operands[0]) >= 12
&& INTVAL(operands[1]) <= 255"
"dstb r%0,%1")
(match_operand:QI 1 "register_operand" "b"))
(set (match_dup 0)
(plus:QI (match_dup 0)
(match_operand:QI 2 "immediate_operand" "i")))]
"REGNO(operands[1]) > 0"
"lim r%0,%2,r%1 ; LR,inc/dec peephole")
;; Eliminate the redundant load in a store/load sequence
(define_peephole
......@@ -1339,13 +1370,10 @@
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:QI 2 "register_operand" "r"))
(set (match_operand:QI 3 "register_operand" "=r")
(mem:QI (plus:QI (match_operand:QI 4 "register_operand" "r")
(match_operand:QI 5 "immediate_operand" "i"))))
(mem:QI (plus:QI (match_dup 0)
(match_dup 1))))
]
"REGNO(operands[2]) == REGNO(operands[3]) &&
REGNO(operands[0]) == REGNO(operands[4]) &&
INTVAL(operands[1]) == INTVAL(operands[5])"
"REGNO(operands[2]) == REGNO(operands[3])"
"st r%2,%1,r%0 ; eliminated previous redundant load")
;;;End.
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