Commit 8608bd56 by Richard Henderson Committed by Richard Henderson

alpha.md (movhi and movqi patterns): Correct predicate for !BWX.

        * alpha.md (movhi and movqi patterns): Correct predicate for !BWX.
        Remove fp reg alternatives.

From-SVN: r28576
parent 80d25530
Sat Aug 7 00:21:20 1999 Richard Henderson <rth@cygnus.com>
* alpha.md (movhi and movqi patterns): Correct predicate for !BWX.
Remove fp reg alternatives.
Sat Aug 7 00:06:54 1999 Jeffrey A Law (law@cygnus.com) Sat Aug 7 00:06:54 1999 Jeffrey A Law (law@cygnus.com)
* gcc.texi: Update bug reporting text. * gcc.texi: Update bug reporting text.
......
...@@ -4156,20 +4156,19 @@ ...@@ -4156,20 +4156,19 @@
[(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")]) [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,f") [(set (match_operand:HI 0 "register_operand" "=r,r")
(match_operand:HI 1 "input_operand" "rJ,n,fJ"))] (match_operand:HI 1 "input_operand" "rJ,n"))]
"! TARGET_BWX "! TARGET_BWX
&& (register_operand (operands[0], HImode) && (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))" || register_operand (operands[1], HImode))"
"@ "@
mov %r1,%0 mov %r1,%0
lda %0,%L1 lda %0,%L1"
fmov %R1,%0" [(set_attr "type" "ilog,iadd")])
[(set_attr "type" "ilog,iadd,fcpys")])
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,f") [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
(match_operand:HI 1 "input_operand" "rJ,n,m,rJ,fJ"))] (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
"TARGET_BWX "TARGET_BWX
&& (register_operand (operands[0], HImode) && (register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))" || reg_or_0_operand (operands[1], HImode))"
...@@ -4177,25 +4176,23 @@ ...@@ -4177,25 +4176,23 @@
mov %r1,%0 mov %r1,%0
lda %0,%L1 lda %0,%L1
ldwu %0,%1 ldwu %0,%1
stw %r1,%0 stw %r1,%0"
fmov %R1,%0" [(set_attr "type" "ilog,iadd,ild,ist")])
[(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,f") [(set (match_operand:QI 0 "register_operand" "=r,r")
(match_operand:QI 1 "input_operand" "rJ,n,fJ"))] (match_operand:QI 1 "input_operand" "rJ,n"))]
"! TARGET_BWX "! TARGET_BWX
&& (register_operand (operands[0], QImode) && (register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))" || register_operand (operands[1], QImode))"
"@ "@
mov %r1,%0 mov %r1,%0
lda %0,%L1 lda %0,%L1"
fmov %R1,%0" [(set_attr "type" "ilog,iadd")])
[(set_attr "type" "ilog,iadd,fcpys")])
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,f") [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
(match_operand:QI 1 "input_operand" "rJ,n,m,rJ,fJ"))] (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
"TARGET_BWX "TARGET_BWX
&& (register_operand (operands[0], QImode) && (register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))" || reg_or_0_operand (operands[1], QImode))"
...@@ -4203,9 +4200,8 @@ ...@@ -4203,9 +4200,8 @@
mov %r1,%0 mov %r1,%0
lda %0,%L1 lda %0,%L1
ldbu %0,%1 ldbu %0,%1
stb %r1,%0 stb %r1,%0"
fmov %R1,%0" [(set_attr "type" "ilog,iadd,ild,ist")])
[(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
;; We do two major things here: handle mem->mem and construct long ;; We do two major things here: handle mem->mem and construct long
;; constants. ;; constants.
......
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