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riscv-gcc-1
Commit 83d58961 by Uros Bizjak
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re PR target/41484 (Please add memory forms of pmovzx* (SSE4.1)) 

	PR target/41484
	* config/i386/sse.md (sse4_1_extendv8qiv8hi2): Also accept memory
	operands for operand 1.
	(sse4_1_extendv4qiv4si2): Ditto.
	(sse4_1_extendv2qiv2di2): Ditto.
	(sse4_1_extendv4hiv4si2): Ditto.
	(sse4_1_extendv2hiv2di2): Ditto.
	(sse4_1_extendv2siv2di2): Ditto.
	(sse4_1_zero_extendv8qiv8hi2): Ditto.
	(sse4_1_zero_extendv4qiv4si2): Ditto.
	(sse4_1_zero_extendv2qiv2di2): Ditto.
	(sse4_1_zero_extendv4hiv4si2): Ditto.
	(sse4_1_zero_extendv2hiv2di2): Ditto.
	(sse4_1_zero_extendv2siv2di2): Ditto.
	(*sse4_1_extendv8qiv8hi2): Remove insn pattern.
	(*sse4_1_extendv4qiv4si2): Ditto.
	(*sse4_1_extendv2qiv2di2): Ditto.
	(*sse4_1_extendv4hiv4si2): Ditto.
	(*sse4_1_extendv2hiv2di2): Ditto.
	(*sse4_1_extendv2siv2di2): Ditto.
	(*sse4_1_zero_extendv8qiv8hi2): Ditto.
	(*sse4_1_zero_extendv4qiv4si2): Ditto.
	(*sse4_1_zero_extendv2qiv2di2): Ditto.
	(*sse4_1_zero_extendv4hiv4si2): Ditto.
	(*sse4_1_zero_extendv2hiv2di2): Ditto.
	(*sse4_1_zero_extendv2siv2di2): Ditto.

From-SVN: r163591
parent 757fc8ed
Showing with 53 additions and 227 deletions
gcc/ChangeLog
2010-08-27 Uros Bizjak <ubizjak@gmail.com>
PR target/41484
* config/i386/sse.md (sse4_1_extendv8qiv8hi2): Also accept memory
operands for operand 1.
(sse4_1_extendv4qiv4si2): Ditto.
(sse4_1_extendv2qiv2di2): Ditto.
(sse4_1_extendv4hiv4si2): Ditto.
(sse4_1_extendv2hiv2di2): Ditto.
(sse4_1_extendv2siv2di2): Ditto.
(sse4_1_zero_extendv8qiv8hi2): Ditto.
(sse4_1_zero_extendv4qiv4si2): Ditto.
(sse4_1_zero_extendv2qiv2di2): Ditto.
(sse4_1_zero_extendv4hiv4si2): Ditto.
(sse4_1_zero_extendv2hiv2di2): Ditto.
(sse4_1_zero_extendv2siv2di2): Ditto.
(*sse4_1_extendv8qiv8hi2): Remove insn pattern.
(*sse4_1_extendv4qiv4si2): Ditto.
(*sse4_1_extendv2qiv2di2): Ditto.
(*sse4_1_extendv4hiv4si2): Ditto.
(*sse4_1_extendv2hiv2di2): Ditto.
(*sse4_1_extendv2siv2di2): Ditto.
(*sse4_1_zero_extendv8qiv8hi2): Ditto.
(*sse4_1_zero_extendv4qiv4si2): Ditto.
(*sse4_1_zero_extendv2qiv2di2): Ditto.
(*sse4_1_zero_extendv4hiv4si2): Ditto.
(*sse4_1_zero_extendv2hiv2di2): Ditto.
(*sse4_1_zero_extendv2siv2di2): Ditto.
2010-08-27 Nathan Froyd <froydnj@codesourcery.com> 2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
* config/mips/mips-protos.h (mips_function_arg_advance): Delete * config/mips/mips-protos.h (mips_function_arg_advance): Delete
...@@ -23,8 +52,7 @@ ...@@ -23,8 +52,7 @@
(rs6000_parm_start): Likewise. (rs6000_parm_start): Likewise.
(rs6000_arg_size): Likewise. (rs6000_arg_size): Likewise.
(rs6000_darwin64_record_arg_advance_recurse): Likewise. (rs6000_darwin64_record_arg_advance_recurse): Likewise.
(rs6000_darwin64_record_arg): Likewise. Take a bool instead of (rs6000_darwin64_record_arg): Likewise. Take a bool instead of an int.
an int.
(rs6000_mixed_function_arg): Likewise. (rs6000_mixed_function_arg): Likewise.
(function_arg): Rename to... (function_arg): Rename to...
(rs6000_function_arg): ...this. (rs6000_function_arg): ...this.
...@@ -62,8 +90,8 @@ ...@@ -62,8 +90,8 @@
2010-08-26 Richard Guenther <rguenther@suse.de> 2010-08-26 Richard Guenther <rguenther@suse.de>
PR tree-optimization/45255 PR tree-optimization/45255
* tree.c (decl_address_invariant_p): DECL_DLLIMPORT_P * tree.c (decl_address_invariant_p): DECL_DLLIMPORT_P statics
statics and externals are also invariant. and externals are also invariant.
2010-08-25 Jakub Jelinek <jakub@redhat.com> 2010-08-25 Jakub Jelinek <jakub@redhat.com>
...@@ -85,8 +113,7 @@ ...@@ -85,8 +113,7 @@
2010-08-25 Richard Guenther <rguenther@suse.de> 2010-08-25 Richard Guenther <rguenther@suse.de>
* alias.c (get_alias_set): Assign a single alias-set to * alias.c (get_alias_set): Assign a single alias-set to all pointers.
all pointers.
* gimple.c (gimple_get_alias_set): Remove special handling * gimple.c (gimple_get_alias_set): Remove special handling
for pointers. for pointers.
...@@ -136,8 +163,7 @@ ...@@ -136,8 +163,7 @@
* config/arm/iterators.md (VU, SE, V_widen_l): New. * config/arm/iterators.md (VU, SE, V_widen_l): New.
(V_unpack, US): New. (V_unpack, US): New.
* config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for vmovl.
vmovl.
(vec_unpack<US>_lo_<mode>): Likewise. (vec_unpack<US>_lo_<mode>): Likewise.
(neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl. (neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl.
(neon_vec_unpack<US>_lo_<mode>): Likewise. (neon_vec_unpack<US>_lo_<mode>): Likewise.
...@@ -239,8 +265,7 @@ ...@@ -239,8 +265,7 @@
TARGET_MEM_REF more properly. TARGET_MEM_REF more properly.
(indirect_ref_may_alias_decl_p): Likewise. (indirect_ref_may_alias_decl_p): Likewise.
* emit-rtl.c (set_mem_attributes_minus_bitpos): Keep TARGET_MEM_REFs. * emit-rtl.c (set_mem_attributes_minus_bitpos): Keep TARGET_MEM_REFs.
* alias.c (ao_ref_from_mem): Handle TARGET_MEM_REF more * alias.c (ao_ref_from_mem): Handle TARGET_MEM_REF more properly.
properly.
2010-08-23 Anatoly Sokolov <aesok@post.ru> 2010-08-23 Anatoly Sokolov <aesok@post.ru>
...@@ -268,10 +293,10 @@ ...@@ -268,10 +293,10 @@
* tree-flow.h (may_be_nonaddressable_p): New definition. Make the * tree-flow.h (may_be_nonaddressable_p): New definition. Make the
existing static function global. existing static function global.
*tree-ssa-loop-ivopts.c (may_be_nonaddressable_p): This function * tree-ssa-loop-ivopts.c (may_be_nonaddressable_p): This function
is changed to global. is changed to global.
*tree-ssa-loop-prefetch.c (gather_memory_references_ref): Call * tree-ssa-loop-prefetch.c (gather_memory_references_ref): Call
may_be_nonaddressable_p on base, and don't collect this reference may_be_nonaddressable_p on base, and don't collect this reference
if the address of the base could not be taken. if the address of the base could not be taken.
...@@ -377,7 +402,7 @@ ...@@ -377,7 +402,7 @@
priority. priority.
(compare_ctor, compare_dtor): Move to ipa.c; use DECL_UID to stabilize (compare_ctor, compare_dtor): Move to ipa.c; use DECL_UID to stabilize
sort; reverse order of constructors. sort; reverse order of constructors.
(cgraph_build_cdtor_fns):Move to ipa.c; rename to build_cdtor_fns. (cgraph_build_cdtor_fns): Move to ipa.c; rename to build_cdtor_fns.
(cgraph_finalize_function): Do not call record_cdtor_fn. (cgraph_finalize_function): Do not call record_cdtor_fn.
(cgraph_finalize_compilation_unit): Do not call cgraph_build_cdtor_fns. (cgraph_finalize_compilation_unit): Do not call cgraph_build_cdtor_fns.
(cgraph_build_static_cdtor): Move to ipa.c. (cgraph_build_static_cdtor): Move to ipa.c.
...@@ -407,7 +432,8 @@ ...@@ -407,7 +432,8 @@
* lto-cgraph.c (lto_output_edge): Use gimple_has_body_p instead of * lto-cgraph.c (lto_output_edge): Use gimple_has_body_p instead of
flag_wpa. flag_wpa.
* lto-streamer-out.c (lto_output): Likewise. * lto-streamer-out.c (lto_output): Likewise.
* passes.c (ipa_write_optimization_summaries): Initialize statement uids. * passes.c (ipa_write_optimization_summaries): Initialize statement
uids.
2010-08-20 Olivier Hainque <hainque@adacore.com> 2010-08-20 Olivier Hainque <hainque@adacore.com>
...@@ -462,7 +488,7 @@ ...@@ -462,7 +488,7 @@
2010-08-20 Uros Bizjak <ubizjak@gmail.com> 2010-08-20 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (ashift RSP splitter): Remove splitter. * config/i386/i386.md (ashift %rsp splitter): Remove splitter.
(pro_epilogue_adjust_stack_di_2): Use "l" constraint for (pro_epilogue_adjust_stack_di_2): Use "l" constraint for
alternative 1 of operand 2. alternative 1 of operand 2.
......
gcc/config/i386/sse.md
...@@ -9596,28 +9596,7 @@ ...@@ -9596,28 +9596,7 @@
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(sign_extend:V8HI (sign_extend:V8HI
(vec_select:V8QI (vec_select:V8QI
(match_operand:V16QI 1 "register_operand" "x") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 3)
(const_int 4)
(const_int 5)
(const_int 6)
(const_int 7)]))))]
"TARGET_SSE4_1"
"%vpmovsxbw\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_extendv8qiv8hi2"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(sign_extend:V8HI
(vec_select:V8QI
(vec_duplicate:V16QI
(match_operand:V8QI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -9637,24 +9616,7 @@ ...@@ -9637,24 +9616,7 @@
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(sign_extend:V4SI (sign_extend:V4SI
(vec_select:V4QI (vec_select:V4QI
(match_operand:V16QI 1 "register_operand" "x") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 3)]))))]
"TARGET_SSE4_1"
"%vpmovsxbd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_extendv4qiv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(sign_extend:V4SI
(vec_select:V4QI
(vec_duplicate:V16QI
(match_operand:V4QI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -9670,22 +9632,7 @@ ...@@ -9670,22 +9632,7 @@
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(sign_extend:V2DI (sign_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_operand:V16QI 1 "register_operand" "x") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmovsxbq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_extendv2qiv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(sign_extend:V2DI
(vec_select:V2QI
(vec_duplicate:V16QI
(match_operand:V2QI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1)]))))] (const_int 1)]))))]
"TARGET_SSE4_1" "TARGET_SSE4_1"
...@@ -9699,24 +9646,7 @@ ...@@ -9699,24 +9646,7 @@
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(sign_extend:V4SI (sign_extend:V4SI
(vec_select:V4HI (vec_select:V4HI
(match_operand:V8HI 1 "register_operand" "x") (match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 3)]))))]
"TARGET_SSE4_1"
"%vpmovsxwd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_extendv4hiv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(sign_extend:V4SI
(vec_select:V4HI
(vec_duplicate:V8HI
(match_operand:V2HI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -9732,22 +9662,7 @@ ...@@ -9732,22 +9662,7 @@
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(sign_extend:V2DI (sign_extend:V2DI
(vec_select:V2HI (vec_select:V2HI
(match_operand:V8HI 1 "register_operand" "x") (match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmovsxwq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_extendv2hiv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(sign_extend:V2DI
(vec_select:V2HI
(vec_duplicate:V8HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1)]))))] (const_int 1)]))))]
"TARGET_SSE4_1" "TARGET_SSE4_1"
...@@ -9761,22 +9676,7 @@ ...@@ -9761,22 +9676,7 @@
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(sign_extend:V2DI (sign_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 1 "register_operand" "x") (match_operand:V4SI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmovsxdq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_extendv2siv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(sign_extend:V2DI
(vec_select:V2SI
(vec_duplicate:V4SI
(match_operand:V2SI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1)]))))] (const_int 1)]))))]
"TARGET_SSE4_1" "TARGET_SSE4_1"
...@@ -9790,28 +9690,7 @@ ...@@ -9790,28 +9690,7 @@
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(zero_extend:V8HI (zero_extend:V8HI
(vec_select:V8QI (vec_select:V8QI
(match_operand:V16QI 1 "register_operand" "x") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 3)
(const_int 4)
(const_int 5)
(const_int 6)
(const_int 7)]))))]
"TARGET_SSE4_1"
"%vpmovzxbw\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_zero_extendv8qiv8hi2"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(zero_extend:V8HI
(vec_select:V8QI
(vec_duplicate:V16QI
(match_operand:V8QI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -9831,24 +9710,7 @@ ...@@ -9831,24 +9710,7 @@
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(zero_extend:V4SI (zero_extend:V4SI
(vec_select:V4QI (vec_select:V4QI
(match_operand:V16QI 1 "register_operand" "x") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 3)]))))]
"TARGET_SSE4_1"
"%vpmovzxbd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_zero_extendv4qiv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(zero_extend:V4SI
(vec_select:V4QI
(vec_duplicate:V16QI
(match_operand:V4QI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -9864,22 +9726,7 @@ ...@@ -9864,22 +9726,7 @@
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(zero_extend:V2DI (zero_extend:V2DI
(vec_select:V2QI (vec_select:V2QI
(match_operand:V16QI 1 "register_operand" "x") (match_operand:V16QI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmovzxbq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_zero_extendv2qiv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(zero_extend:V2DI
(vec_select:V2QI
(vec_duplicate:V16QI
(match_operand:V2QI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1)]))))] (const_int 1)]))))]
"TARGET_SSE4_1" "TARGET_SSE4_1"
...@@ -9893,24 +9740,7 @@ ...@@ -9893,24 +9740,7 @@
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(zero_extend:V4SI (zero_extend:V4SI
(vec_select:V4HI (vec_select:V4HI
(match_operand:V8HI 1 "register_operand" "x") (match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 3)]))))]
"TARGET_SSE4_1"
"%vpmovzxwd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_zero_extendv4hiv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(zero_extend:V4SI
(vec_select:V4HI
(vec_duplicate:V8HI
(match_operand:V4HI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -9926,22 +9756,7 @@ ...@@ -9926,22 +9756,7 @@
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(zero_extend:V2DI (zero_extend:V2DI
(vec_select:V2HI (vec_select:V2HI
(match_operand:V8HI 1 "register_operand" "x") (match_operand:V8HI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmovzxwq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_zero_extendv2hiv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(zero_extend:V2DI
(vec_select:V2HI
(vec_duplicate:V8HI
(match_operand:V2HI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1)]))))] (const_int 1)]))))]
"TARGET_SSE4_1" "TARGET_SSE4_1"
...@@ -9955,22 +9770,7 @@ ...@@ -9955,22 +9770,7 @@
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(zero_extend:V2DI (zero_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 1 "register_operand" "x") (match_operand:V4SI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmovzxdq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_zero_extendv2siv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(zero_extend:V2DI
(vec_select:V2SI
(vec_duplicate:V4SI
(match_operand:V2SI 1 "nonimmediate_operand" "xm"))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1)]))))] (const_int 1)]))))]
"TARGET_SSE4_1" "TARGET_SSE4_1"
......
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