Skip to content

R
riscv-gcc-1
Commit 82955615 by Richard Earnshaw Committed by Richard Earnshaw
Options

fpa.md: New file. 

* fpa.md: New file.  Move all patterns relating to FPA co-processor
to here...
* arm.md: ... from here.
(cirrus.md, fpa.md): Include at end of description.
(divsf3, divdf3, modsf3, movdf3, sqrtsf2, sqrtdf2): New expands.
(pic_load_addr_based): Remove register constraint from expander.
(seq, sne, sgt, sle, slt, sge, sgeu, sleu, sgtu, sltu, sunordered)
(sordered, sungt, sunle, sunge, sunlt): Likewise.
(eh_epilogue, tablejump): Likewise.

From-SVN: r64075
parent 1d719415
Showing with 783 additions and 710 deletions
gcc/ChangeLog
2003-03-10 Richard Earnshaw <rearnsha@arm.com>
* fpa.md: New file. Move all patterns relating to FPA co-processor
to here...
* arm.md: ... from here.
(cirrus.md, fpa.md): Include at end of description.
(divsf3, divdf3, modsf3, movdf3, sqrtsf2, sqrtdf2): New expands.
(pic_load_addr_based): Remove register constraint from expander.
(seq, sne, sgt, sle, slt, sge, sgeu, sleu, sgtu, sltu, sunordered)
(sordered, sungt, sunle, sunge, sunlt): Likewise.
(eh_epilogue, tablejump): Likewise.
2003-03-09 David Edelsohn <edelsohn@gnu.org> 2003-03-09 David Edelsohn <edelsohn@gnu.org>
Mostafa Hagog Mostafa Hagog
......
gcc/config/arm/arm.md
...@@ -241,44 +241,6 @@ ...@@ -241,44 +241,6 @@
;; {ready-delay} {issue-delay} [{conflict-list}]) ;; {ready-delay} {issue-delay} [{conflict-list}])
;;-------------------------------------------------------------------- ;;--------------------------------------------------------------------
;; Floating point unit (FPA)
;;--------------------------------------------------------------------
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fdivx")) 71 69)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fdivd")) 59 57)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fdivs")) 31 29)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fmul")) 9 7)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "ffmul")) 6 4)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "farith")) 4 2)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "ffarith")) 2 2)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "r_2_f")) 5 3)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "f_2_r")) 1 2)
; The fpa10 doesn't really have a memory read unit, but it can start to
; speculatively execute the instruction in the pipeline, provided the data
; is already loaded, so pretend reads have a delay of 2 (and that the
; pipeline is infinite).
(define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "f_load")) 3 1)
;;--------------------------------------------------------------------
;; Write buffer ;; Write buffer
;;-------------------------------------------------------------------- ;;--------------------------------------------------------------------
; Strictly, we should model a 4-deep write buffer for ARM7xx based chips ; Strictly, we should model a 4-deep write buffer for ARM7xx based chips
...@@ -389,8 +351,6 @@ ...@@ -389,8 +351,6 @@
(and (eq_attr "core_cycles" "multi") (and (eq_attr "core_cycles" "multi")
(eq_attr "type" "!mult,load,store1,store2,store3,store4")) 32 32) (eq_attr "type" "!mult,load,store1,store2,store3,store4")) 32 32)
(include "cirrus.md")
;;--------------------------------------------------------------------------- ;;---------------------------------------------------------------------------
;; Insn patterns ;; Insn patterns
;; ;;
...@@ -817,18 +777,6 @@ ...@@ -817,18 +777,6 @@
operands[2] = force_reg (SFmode, operands[2]); operands[2] = force_reg (SFmode, operands[2]);
") ")
(define_insn "*arm_addsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
(match_operand:SF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?s\\t%0, %1, %2
suf%?s\\t%0, %1, #%N2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_expand "adddf3" (define_expand "adddf3"
[(set (match_operand:DF 0 "s_register_operand" "") [(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "") (plus:DF (match_operand:DF 1 "s_register_operand" "")
...@@ -840,54 +788,6 @@ ...@@ -840,54 +788,6 @@
operands[2] = force_reg (DFmode, operands[2]); operands[2] = force_reg (DFmode, operands[2]);
") ")
(define_insn "*arm_adddf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
(match_operand:DF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?d\\t%0, %1, %2
suf%?d\\t%0, %1, #%N2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f,f"))
(match_operand:DF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?d\\t%0, %1, %2
suf%?d\\t%0, %1, #%N2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(plus:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"adf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"adf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_expand "subdi3" (define_expand "subdi3"
[(parallel [(parallel
[(set (match_operand:DI 0 "s_register_operand" "") [(set (match_operand:DI 0 "s_register_operand" "")
...@@ -1105,17 +1005,6 @@ ...@@ -1105,17 +1005,6 @@
} }
") ")
(define_insn "*arm_subsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
(match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?s\\t%0, %1, %2
rsf%?s\\t%0, %2, %1"
[(set_attr "type" "farith")]
)
(define_expand "subdf3" (define_expand "subdf3"
[(set (match_operand:DF 0 "s_register_operand" "") [(set (match_operand:DF 0 "s_register_operand" "")
(minus:DF (match_operand:DF 1 "fpa_rhs_operand" "") (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "")
...@@ -1131,53 +1020,6 @@ ...@@ -1131,53 +1020,6 @@
} }
") ")
(define_insn "*arm_subdf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?d\\t%0, %1, %2
rsf%?d\\t%0, %2, %1"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subdf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"suf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subdf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f,f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?d\\t%0, %1, %2
rsf%?d\\t%0, %2, %1"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subdf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"suf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
;; Multiplication insns ;; Multiplication insns
...@@ -1464,16 +1306,6 @@ ...@@ -1464,16 +1306,6 @@
operands[2] = force_reg (SFmode, operands[2]); operands[2] = force_reg (SFmode, operands[2]);
") ")
(define_insn "*arm_mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(mult:SF (match_operand:SF 1 "s_register_operand" "f")
(match_operand:SF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fml%?s\\t%0, %1, %2"
[(set_attr "type" "ffmul")
(set_attr "predicable" "yes")]
)
(define_expand "muldf3" (define_expand "muldf3"
[(set (match_operand:DF 0 "s_register_operand" "") [(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "") (mult:DF (match_operand:DF 1 "s_register_operand" "")
...@@ -1484,165 +1316,38 @@ ...@@ -1484,165 +1316,38 @@
&& !cirrus_fp_register (operands[2], DFmode)) && !cirrus_fp_register (operands[2], DFmode))
operands[2] = force_reg (DFmode, operands[2]); operands[2] = force_reg (DFmode, operands[2]);
") ")
(define_insn "*arm_muldf3"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f")
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf_esfdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF
(float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
;; Division insns ;; Division insns
(define_insn "divsf3" (define_expand "divsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f") [(set (match_operand:SF 0 "s_register_operand" "")
(div:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G") (div:SF (match_operand:SF 1 "fpa_rhs_operand" "")
(match_operand:SF 2 "fpa_rhs_operand" "fG,f")))] (match_operand:SF 2 "fpa_rhs_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
fdv%?s\\t%0, %1, %2
frd%?s\\t%0, %2, %1"
[(set_attr "type" "fdivs")
(set_attr "predicable" "yes")]
)
(define_insn "divdf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(div:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
dvf%?d\\t%0, %1, %2
rdf%?d\\t%0, %2, %1"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"dvf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (match_operand:DF 1 "fpa_rhs_operand" "fG")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"rdf%?d\\t%0, %2, %1" "")
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf_esfdf_esfdf" (define_expand "divdf3"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:DF 0 "s_register_operand" "")
(div:DF (float_extend:DF (div:DF (match_operand:DF 1 "fpa_rhs_operand" "")
(match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "fpa_rhs_operand" "")))]
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"dvf%?d\\t%0, %1, %2" "")
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
;; Modulo insns ;; Modulo insns
(define_insn "modsf3" (define_expand "modsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "")
(mod:SF (match_operand:SF 1 "s_register_operand" "f") (mod:SF (match_operand:SF 1 "s_register_operand" "")
(match_operand:SF 2 "fpa_rhs_operand" "fG")))] (match_operand:SF 2 "fpa_rhs_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?s\\t%0, %1, %2"
[(set_attr "type" "fdivs")
(set_attr "predicable" "yes")]
)
(define_insn "moddf3"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (match_operand:DF 1 "s_register_operand" "f")
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf_esfdf_df"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2" "")
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf_esfdf_esfdf" (define_expand "moddf3"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:DF 0 "s_register_operand" "")
(mod:DF (float_extend:DF (mod:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "fpa_rhs_operand" "")))]
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2" "")
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
;; Boolean and,ior,xor insns ;; Boolean and,ior,xor insns
...@@ -2871,34 +2576,6 @@ ...@@ -2871,34 +2576,6 @@
"TARGET_ARM && TARGET_ANY_HARD_FLOAT" "TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"") "")
(define_insn "*arm_negsf2"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mnf%?s\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*arm_negdf2"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(neg:DF (match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mnf%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*negdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(neg:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mnf%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
;; abssi2 doesn't really clobber the condition codes if a different register ;; abssi2 doesn't really clobber the condition codes if a different register
;; is being set. To keep things simple, assume during rtl manipulations that ;; is being set. To keep things simple, assume during rtl manipulations that
;; it does, but tell the final scan operator the truth. Similarly for ;; it does, but tell the final scan operator the truth. Similarly for
...@@ -2946,67 +2623,23 @@ ...@@ -2946,67 +2623,23 @@
"TARGET_ARM && TARGET_ANY_HARD_FLOAT" "TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"") "")
(define_insn "*arm_abssf2"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"abs%?s\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_expand "absdf2" (define_expand "absdf2"
[(set (match_operand:DF 0 "s_register_operand" "") [(set (match_operand:DF 0 "s_register_operand" "")
(abs:DF (match_operand:DF 1 "s_register_operand" "")))] (abs:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT" "TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"") "")
(define_insn "*arm_absdf2" (define_expand "sqrtsf2"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:SF 0 "s_register_operand" "")
(abs:DF (match_operand:DF 1 "s_register_operand" "f")))] (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"abs%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*absdf_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(abs:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"abs%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"sqt%?s\\t%0, %1"
[(set_attr "type" "float_em")
(set_attr "predicable" "yes")]
)
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"sqt%?d\\t%0, %1" "")
[(set_attr "type" "float_em")
(set_attr "predicable" "yes")]
)
(define_insn "*sqrtdf_esfdf" (define_expand "sqrtdf2"
[(set (match_operand:DF 0 "s_register_operand" "=f") [(set (match_operand:DF 0 "s_register_operand" "")
(sqrt:DF (float_extend:DF (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))]
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"sqt%?d\\t%0, %1" "")
[(set_attr "type" "float_em")
(set_attr "predicable" "yes")]
)
(define_insn_and_split "one_cmpldi2" (define_insn_and_split "one_cmpldi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r") [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
...@@ -3085,15 +2718,6 @@ ...@@ -3085,15 +2718,6 @@
} }
") ")
(define_insn "*arm_floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"flt%?s\\t%0, %1"
[(set_attr "type" "r_2_f")
(set_attr "predicable" "yes")]
)
(define_expand "floatsidf2" (define_expand "floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "") [(set (match_operand:DF 0 "s_register_operand" "")
(float:DF (match_operand:SI 1 "s_register_operand" "")))] (float:DF (match_operand:SI 1 "s_register_operand" "")))]
...@@ -3106,15 +2730,6 @@ ...@@ -3106,15 +2730,6 @@
} }
") ")
(define_insn "*arm_floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(float:DF (match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"flt%?d\\t%0, %1"
[(set_attr "type" "r_2_f")
(set_attr "predicable" "yes")]
)
(define_expand "fix_truncsfsi2" (define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
...@@ -3131,15 +2746,6 @@ ...@@ -3131,15 +2746,6 @@
} }
") ")
(define_insn "*arm_fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fix%?z\\t%0, %1"
[(set_attr "type" "f_2_r")
(set_attr "predicable" "yes")]
)
(define_expand "fix_truncdfsi2" (define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
...@@ -3154,15 +2760,6 @@ ...@@ -3154,15 +2760,6 @@
} }
") ")
(define_insn "*arm_fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fix%?z\\t%0, %1"
[(set_attr "type" "f_2_r")
(set_attr "predicable" "yes")]
)
;; Truncation insns ;; Truncation insns
(define_expand "truncdfsf2" (define_expand "truncdfsf2"
...@@ -3172,16 +2769,6 @@ ...@@ -3172,16 +2769,6 @@
"TARGET_ARM && TARGET_ANY_HARD_FLOAT" "TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"" ""
) )
(define_insn "*arm_truncdfsf2"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(float_truncate:SF
(match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mvf%?s\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
;; Zero and sign extension instructions. ;; Zero and sign extension instructions.
...@@ -3911,15 +3498,6 @@ ...@@ -3911,15 +3498,6 @@
"TARGET_ARM && TARGET_ANY_HARD_FLOAT" "TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"" ""
) )
(define_insn "*arm_extendsfdf2"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mvf%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
;; Move insns (including loads and stores) ;; Move insns (including loads and stores)
...@@ -4214,7 +3792,7 @@ ...@@ -4214,7 +3792,7 @@
;; This variant is used for AOF assembly, since it needs to mention the ;; This variant is used for AOF assembly, since it needs to mention the
;; pic register in the rtl. ;; pic register in the rtl.
(define_expand "pic_load_addr_based" (define_expand "pic_load_addr_based"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(unspec:SI [(match_operand 1 "" "") (match_dup 2)] UNSPEC_PIC_SYM))] (unspec:SI [(match_operand 1 "" "") (match_dup 2)] UNSPEC_PIC_SYM))]
"TARGET_ARM && flag_pic" "TARGET_ARM && flag_pic"
"operands[2] = pic_offset_table_rtx;" "operands[2] = pic_offset_table_rtx;"
...@@ -4995,35 +4573,6 @@ ...@@ -4995,35 +4573,6 @@
" "
) )
(define_insn "*arm_movsf_hard_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m")
(match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))]
"TARGET_ARM
&& TARGET_HARD_FLOAT
&& (GET_CODE (operands[0]) != MEM
|| register_operand (operands[1], SFmode))"
"@
mvf%?s\\t%0, %1
mnf%?s\\t%0, #%N1
ldf%?s\\t%0, %1
stf%?s\\t%1, %0
str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4
stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4
mov%?\\t%0, %1
ldr%?\\t%0, %1\\t%@ float
str%?\\t%1, %0\\t%@ float"
[(set_attr "length" "4,4,4,4,8,8,4,4,4")
(set_attr "predicable" "yes")
(set_attr "type"
"ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1")
(set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
(set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
)
;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg
;; when -msoft-float.
(define_insn "*arm_movsf_soft_insn" (define_insn "*arm_movsf_soft_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
(match_operand:SF 1 "general_operand" "r,mE,r"))] (match_operand:SF 1 "general_operand" "r,mE,r"))]
...@@ -5127,44 +4676,6 @@ ...@@ -5127,44 +4676,6 @@
}" }"
) )
(define_insn "*movdf_hard_insn"
[(set (match_operand:DF 0 "nonimmediate_operand"
"=r,Q,r,m,r, f, f,f, m,!f,!r")
(match_operand:DF 1 "general_operand"
"Q, r,r,r,mF,fG,H,mF,f,r, f"))]
"TARGET_ARM
&& TARGET_HARD_FLOAT
&& (GET_CODE (operands[0]) != MEM
|| register_operand (operands[1], DFmode))"
"*
{
switch (which_alternative)
{
default:
case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
case 2: case 3: case 4: return output_move_double (operands);
case 5: return \"mvf%?d\\t%0, %1\";
case 6: return \"mnf%?d\\t%0, #%N1\";
case 7: return \"ldf%?d\\t%0, %1\";
case 8: return \"stf%?d\\t%1, %0\";
case 9: return output_mov_double_fpa_from_arm (operands);
case 10: return output_mov_double_arm_from_fpa (operands);
}
}
"
[(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
(set_attr "predicable" "yes")
(set_attr "type"
"load,store2,*,store2,load,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
(set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
)
;; Software floating point version. This is essentially the same as movdi.
;; Do not use `f' as a constraint to prevent reload from ever trying to use
;; an `f' reg.
(define_insn "*movdf_soft_insn" (define_insn "*movdf_soft_insn"
[(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,m") [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,m")
(match_operand:DF 1 "soft_df_operand" "r,mF,r"))] (match_operand:DF 1 "soft_df_operand" "r,mF,r"))]
...@@ -5217,36 +4728,6 @@ ...@@ -5217,36 +4728,6 @@
(set_attr "type" "*,load,store2,load,store2,*") (set_attr "type" "*,load,store2,load,store2,*")
(set_attr "pool_range" "*,*,*,1020,*,*")] (set_attr "pool_range" "*,*,*,1020,*,*")]
) )
;; Saving and restoring the floating point registers in the prologue should
;; be done in XFmode, even though we don't support that for anything else
;; (Well, strictly it's 'internal representation', but that's effectively
;; XFmode).
(define_insn "*movxf_hard_insn"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r")
(match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
"TARGET_ARM && TARGET_HARD_FLOAT && reload_completed"
"*
switch (which_alternative)
{
default:
case 0: return \"mvf%?e\\t%0, %1\";
case 1: return \"mnf%?e\\t%0, #%N1\";
case 2: return \"ldf%?e\\t%0, %1\";
case 3: return \"stf%?e\\t%1, %0\";
case 4: return output_mov_long_double_fpa_from_arm (operands);
case 5: return output_mov_long_double_arm_from_fpa (operands);
case 6: return output_mov_long_double_arm_from_arm (operands);
}
"
[(set_attr "length" "4,4,4,4,8,8,12")
(set_attr "predicable" "yes")
(set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")
(set_attr "pool_range" "*,*,1024,*,*,*,*")
(set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
)
;; load- and store-multiple insns ;; load- and store-multiple insns
...@@ -5750,54 +5231,6 @@ ...@@ -5750,54 +5231,6 @@
] ]
) )
(define_insn "*cmpsf_insn"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
cnf%?\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpdf_insn"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
cnf%?\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpesfdf_df"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
cnf%?\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpdf_esfdf"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"cmf%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
;; Cirrus SF compare instruction ;; Cirrus SF compare instruction
(define_insn "*cirrus_cmpsf" (define_insn "*cirrus_cmpsf"
[(set (reg:CCFP CC_REGNUM) [(set (reg:CCFP CC_REGNUM)
...@@ -5841,54 +5274,6 @@ ...@@ -5841,54 +5274,6 @@
(set_attr "cirrus" "compare")] (set_attr "cirrus" "compare")]
) )
(define_insn "*cmpsf_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpdf_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmp_esfdf_df_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmp_df_esfdf_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"cmf%?e\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
; This insn allows redundant compares to be removed by cse, nothing should ; This insn allows redundant compares to be removed by cse, nothing should
; ever appear in the output file since (set (reg x) (reg x)) is a no-op that ; ever appear in the output file since (set (reg x) (reg x)) is a no-op that
; is deleted later on. The match_dup will match the mode here, so that ; is deleted later on. The match_dup will match the mode here, so that
...@@ -6185,77 +5570,77 @@ ...@@ -6185,77 +5570,77 @@
; scc insns ; scc insns
(define_expand "seq" (define_expand "seq"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(eq:SI (match_dup 1) (const_int 0)))] (eq:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sne" (define_expand "sne"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(ne:SI (match_dup 1) (const_int 0)))] (ne:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sgt" (define_expand "sgt"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(gt:SI (match_dup 1) (const_int 0)))] (gt:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sle" (define_expand "sle"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(le:SI (match_dup 1) (const_int 0)))] (le:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sge" (define_expand "sge"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(ge:SI (match_dup 1) (const_int 0)))] (ge:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "slt" (define_expand "slt"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(lt:SI (match_dup 1) (const_int 0)))] (lt:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sgtu" (define_expand "sgtu"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(gtu:SI (match_dup 1) (const_int 0)))] (gtu:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sleu" (define_expand "sleu"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(leu:SI (match_dup 1) (const_int 0)))] (leu:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sgeu" (define_expand "sgeu"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(geu:SI (match_dup 1) (const_int 0)))] (geu:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sltu" (define_expand "sltu"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(ltu:SI (match_dup 1) (const_int 0)))] (ltu:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM" "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);"
) )
(define_expand "sunordered" (define_expand "sunordered"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(unordered:SI (match_dup 1) (const_int 0)))] (unordered:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
...@@ -6263,7 +5648,7 @@ ...@@ -6263,7 +5648,7 @@
) )
(define_expand "sordered" (define_expand "sordered"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(ordered:SI (match_dup 1) (const_int 0)))] (ordered:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
...@@ -6271,7 +5656,7 @@ ...@@ -6271,7 +5656,7 @@
) )
(define_expand "sungt" (define_expand "sungt"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(ungt:SI (match_dup 1) (const_int 0)))] (ungt:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
...@@ -6279,7 +5664,7 @@ ...@@ -6279,7 +5664,7 @@
) )
(define_expand "sunge" (define_expand "sunge"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(unge:SI (match_dup 1) (const_int 0)))] (unge:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
...@@ -6287,7 +5672,7 @@ ...@@ -6287,7 +5672,7 @@
) )
(define_expand "sunlt" (define_expand "sunlt"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(unlt:SI (match_dup 1) (const_int 0)))] (unlt:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
...@@ -6295,7 +5680,7 @@ ...@@ -6295,7 +5680,7 @@
) )
(define_expand "sunle" (define_expand "sunle"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "")
(unle:SI (match_dup 1) (const_int 0)))] (unle:SI (match_dup 1) (const_int 0)))]
"TARGET_ARM && TARGET_HARD_FLOAT" "TARGET_ARM && TARGET_HARD_FLOAT"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
...@@ -6306,14 +5691,14 @@ ...@@ -6306,14 +5691,14 @@
;;; simple ARM instructions. ;;; simple ARM instructions.
; ;
; (define_expand "suneq" ; (define_expand "suneq"
; [(set (match_operand:SI 0 "s_register_operand" "=r") ; [(set (match_operand:SI 0 "s_register_operand" "")
; (uneq:SI (match_dup 1) (const_int 0)))] ; (uneq:SI (match_dup 1) (const_int 0)))]
; "TARGET_ARM && TARGET_HARD_FLOAT" ; "TARGET_ARM && TARGET_HARD_FLOAT"
; "abort ();" ; "abort ();"
; ) ; )
; ;
; (define_expand "sltgt" ; (define_expand "sltgt"
; [(set (match_operand:SI 0 "s_register_operand" "=r") ; [(set (match_operand:SI 0 "s_register_operand" "")
; (ltgt:SI (match_dup 1) (const_int 0)))] ; (ltgt:SI (match_dup 1) (const_int 0)))]
; "TARGET_ARM && TARGET_HARD_FLOAT" ; "TARGET_ARM && TARGET_HARD_FLOAT"
; "abort ();" ; "abort ();"
...@@ -6436,28 +5821,6 @@ ...@@ -6436,28 +5821,6 @@
(set_attr "conds" "use")] (set_attr "conds" "use")]
) )
(define_insn "*movsfcc_hard_insn"
[(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
(if_then_else:SF
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:SF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
(match_operand:SF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
mvf%D3s\\t%0, %2
mnf%D3s\\t%0, #%N2
mvf%d3s\\t%0, %1
mnf%d3s\\t%0, #%N1
mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2
mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2
mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
[(set_attr "length" "4,4,4,4,8,8,8,8")
(set_attr "type" "ffarith")
(set_attr "conds" "use")]
)
(define_insn "*movsfcc_soft_insn" (define_insn "*movsfcc_soft_insn"
[(set (match_operand:SF 0 "s_register_operand" "=r,r") [(set (match_operand:SF 0 "s_register_operand" "=r,r")
(if_then_else:SF (match_operator 3 "arm_comparison_operator" (if_then_else:SF (match_operator 3 "arm_comparison_operator"
...@@ -6471,28 +5834,6 @@ ...@@ -6471,28 +5834,6 @@
[(set_attr "conds" "use")] [(set_attr "conds" "use")]
) )
(define_insn "*movdfcc_insn"
[(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
(if_then_else:DF
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:DF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
(match_operand:DF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
mvf%D3d\\t%0, %2
mnf%D3d\\t%0, #%N2
mvf%d3d\\t%0, %1
mnf%d3d\\t%0, #%N1
mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2
mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2
mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
[(set_attr "length" "4,4,4,4,8,8,8,8")
(set_attr "type" "ffarith")
(set_attr "conds" "use")]
)
;; Jump and linkage insns ;; Jump and linkage insns
...@@ -8782,9 +8123,9 @@ ...@@ -8782,9 +8123,9 @@
) )
(define_expand "eh_epilogue" (define_expand "eh_epilogue"
[(use (match_operand:SI 0 "register_operand" "r")) [(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" "r")) (use (match_operand:SI 1 "register_operand" ""))
(use (match_operand:SI 2 "register_operand" "r"))] (use (match_operand:SI 2 "register_operand" ""))]
"TARGET_EITHER" "TARGET_EITHER"
" "
{ {
...@@ -9135,7 +8476,7 @@ ...@@ -9135,7 +8476,7 @@
;; Miscellaneous Thumb patterns ;; Miscellaneous Thumb patterns
(define_expand "tablejump" (define_expand "tablejump"
[(parallel [(set (pc) (match_operand:SI 0 "register_operand" "l*r")) [(parallel [(set (pc) (match_operand:SI 0 "register_operand" ""))
(use (label_ref (match_operand 1 "" "")))])] (use (label_ref (match_operand 1 "" "")))])]
"TARGET_THUMB" "TARGET_THUMB"
" "
...@@ -9231,3 +8572,8 @@ ...@@ -9231,3 +8572,8 @@
"" ""
"%@ %0 needed for prologue" "%@ %0 needed for prologue"
) )
;; Load the FPA co-processor patterns
(include "fpa.md")
;; Load the Maverick co-processor patterns
(include "cirrus.md")
gcc/config/arm/fpa.md 0 → 100644
;;- Machine description for FPA co-processor for ARM cpus.
;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,
;; 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
;; and Martin Simmons (@harleqn.co.uk).
;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 2, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
;;--------------------------------------------------------------------
;; Floating point unit (FPA)
;;--------------------------------------------------------------------
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fdivx")) 71 69)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fdivd")) 59 57)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fdivs")) 31 29)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "fmul")) 9 7)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "ffmul")) 6 4)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "farith")) 4 2)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "ffarith")) 2 2)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "r_2_f")) 5 3)
(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "f_2_r")) 1 2)
; The fpa10 doesn't really have a memory read unit, but it can start to
; speculatively execute the instruction in the pipeline, provided the data
; is already loaded, so pretend reads have a delay of 2 (and that the
; pipeline is infinite).
(define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa")
(eq_attr "type" "f_load")) 3 1)
(define_insn "*addsf3_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
(match_operand:SF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?s\\t%0, %1, %2
suf%?s\\t%0, %1, #%N2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf3_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
(match_operand:DF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?d\\t%0, %1, %2
suf%?d\\t%0, %1, #%N2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf_esfdf_df_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f,f"))
(match_operand:DF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?d\\t%0, %1, %2
suf%?d\\t%0, %1, #%N2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf_df_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(plus:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"adf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*adddf_esfdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"adf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subsf3_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
(match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?s\\t%0, %1, %2
rsf%?s\\t%0, %2, %1"
[(set_attr "type" "farith")]
)
(define_insn "*subdf3_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?d\\t%0, %1, %2
rsf%?d\\t%0, %2, %1"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subdf_esfdf_df_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"suf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subdf_df_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f,f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?d\\t%0, %1, %2
rsf%?d\\t%0, %2, %1"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*subdf_esfdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"suf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
(define_insn "*mulsf3_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(mult:SF (match_operand:SF 1 "s_register_operand" "f")
(match_operand:SF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fml%?s\\t%0, %1, %2"
[(set_attr "type" "ffmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf3_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f")
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf_esfdf_df_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf_df_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
(define_insn "*muldf_esfdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF
(float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
;; Division insns
(define_insn "*divsf3_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
(div:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
(match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
fdv%?s\\t%0, %1, %2
frd%?s\\t%0, %2, %1"
[(set_attr "type" "fdivs")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf3_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(div:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
dvf%?d\\t%0, %1, %2
rdf%?d\\t%0, %2, %1"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf_esfdf_df_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"dvf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf_df_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (match_operand:DF 1 "fpa_rhs_operand" "fG")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rdf%?d\\t%0, %2, %1"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*divdf_esfdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"dvf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*modsf3_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(mod:SF (match_operand:SF 1 "s_register_operand" "f")
(match_operand:SF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?s\\t%0, %1, %2"
[(set_attr "type" "fdivs")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf3_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (match_operand:DF 1 "s_register_operand" "f")
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf_esfdf_df_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf_df_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (match_operand:DF 1 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*moddf_esfdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
(define_insn "*negsf2_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mnf%?s\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*negdf2_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(neg:DF (match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mnf%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*negdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(neg:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mnf%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*abssf2_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"abs%?s\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*absdf2_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(abs:DF (match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"abs%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*absdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(abs:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"abs%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*sqrtsf2_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"sqt%?s\\t%0, %1"
[(set_attr "type" "float_em")
(set_attr "predicable" "yes")]
)
(define_insn "*sqrtdf2_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"sqt%?d\\t%0, %1"
[(set_attr "type" "float_em")
(set_attr "predicable" "yes")]
)
(define_insn "*sqrtdf_esfdf_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"sqt%?d\\t%0, %1"
[(set_attr "type" "float_em")
(set_attr "predicable" "yes")]
)
(define_insn "*floatsisf2_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"flt%?s\\t%0, %1"
[(set_attr "type" "r_2_f")
(set_attr "predicable" "yes")]
)
(define_insn "*floatsidf2_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(float:DF (match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"flt%?d\\t%0, %1"
[(set_attr "type" "r_2_f")
(set_attr "predicable" "yes")]
)
(define_insn "*fix_truncsfsi2_fpa"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fix%?z\\t%0, %1"
[(set_attr "type" "f_2_r")
(set_attr "predicable" "yes")]
)
(define_insn "*fix_truncdfsi2_fpa"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fix%?z\\t%0, %1"
[(set_attr "type" "f_2_r")
(set_attr "predicable" "yes")]
)
(define_insn "*truncdfsf2_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(float_truncate:SF
(match_operand:DF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mvf%?s\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*extendsfdf2_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"mvf%?d\\t%0, %1"
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
(define_insn "*movsf_fpa"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m")
(match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))]
"TARGET_ARM
&& TARGET_HARD_FLOAT
&& (GET_CODE (operands[0]) != MEM
|| register_operand (operands[1], SFmode))"
"@
mvf%?s\\t%0, %1
mnf%?s\\t%0, #%N1
ldf%?s\\t%0, %1
stf%?s\\t%1, %0
str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4
stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4
mov%?\\t%0, %1
ldr%?\\t%0, %1\\t%@ float
str%?\\t%1, %0\\t%@ float"
[(set_attr "length" "4,4,4,4,8,8,4,4,4")
(set_attr "predicable" "yes")
(set_attr "type"
"ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1")
(set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
(set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
)
(define_insn "*movdf_fpa"
[(set (match_operand:DF 0 "nonimmediate_operand"
"=r,Q,r,m,r, f, f,f, m,!f,!r")
(match_operand:DF 1 "general_operand"
"Q, r,r,r,mF,fG,H,mF,f,r, f"))]
"TARGET_ARM
&& TARGET_HARD_FLOAT
&& (GET_CODE (operands[0]) != MEM
|| register_operand (operands[1], DFmode))"
"*
{
switch (which_alternative)
{
default:
case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
case 2: case 3: case 4: return output_move_double (operands);
case 5: return \"mvf%?d\\t%0, %1\";
case 6: return \"mnf%?d\\t%0, #%N1\";
case 7: return \"ldf%?d\\t%0, %1\";
case 8: return \"stf%?d\\t%1, %0\";
case 9: return output_mov_double_fpa_from_arm (operands);
case 10: return output_mov_double_arm_from_fpa (operands);
}
}
"
[(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
(set_attr "predicable" "yes")
(set_attr "type"
"load,store2,*,store2,load,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
(set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
)
;; Saving and restoring the floating point registers in the prologue should
;; be done in XFmode, even though we don't support that for anything else
;; (Well, strictly it's 'internal representation', but that's effectively
;; XFmode).
(define_insn "*movxf_fpa"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r")
(match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
"TARGET_ARM && TARGET_HARD_FLOAT && reload_completed"
"*
switch (which_alternative)
{
default:
case 0: return \"mvf%?e\\t%0, %1\";
case 1: return \"mnf%?e\\t%0, #%N1\";
case 2: return \"ldf%?e\\t%0, %1\";
case 3: return \"stf%?e\\t%1, %0\";
case 4: return output_mov_long_double_fpa_from_arm (operands);
case 5: return output_mov_long_double_arm_from_fpa (operands);
case 6: return output_mov_long_double_arm_from_arm (operands);
}
"
[(set_attr "length" "4,4,4,4,8,8,12")
(set_attr "predicable" "yes")
(set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")
(set_attr "pool_range" "*,*,1024,*,*,*,*")
(set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
)
(define_insn "*cmpsf_fpa"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
cnf%?\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpdf_fpa"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
cnf%?\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpesfdf_df_fpa"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
cnf%?\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpdf_esfdf_fpa"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"cmf%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpsf_trap_fpa"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
(match_operand:SF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmpdf_trap_fpa"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmp_esfdf_df_trap_fpa"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
(match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*cmp_df_esfdf_trap_fpa"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
(float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"cmf%?e\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
(define_insn "*movsfcc_fpa"
[(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
(if_then_else:SF
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:SF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
(match_operand:SF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
mvf%D3s\\t%0, %2
mnf%D3s\\t%0, #%N2
mvf%d3s\\t%0, %1
mnf%d3s\\t%0, #%N1
mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2
mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2
mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
[(set_attr "length" "4,4,4,4,8,8,8,8")
(set_attr "type" "ffarith")
(set_attr "conds" "use")]
)
(define_insn "*movdfcc_fpa"
[(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
(if_then_else:DF
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:DF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
(match_operand:DF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
mvf%D3d\\t%0, %2
mnf%D3d\\t%0, #%N2
mvf%d3d\\t%0, %1
mnf%d3d\\t%0, #%N1
mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2
mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2
mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
[(set_attr "length" "4,4,4,4,8,8,8,8")
(set_attr "type" "ffarith")
(set_attr "conds" "use")]
)
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment