[PR73350][PR80862] Improve subst for RC-capable insns.

PR target/73350,80862
gcc/
	* config/i386/subst.md (round): Fix round pattern.
	* config/i386/i386.c (ix86_erase_embedded_rounding):
	Fix erasing rounding for the fixed pattern.

gcc/testsuite/
	* gcc.target/i386/pr73350.c: New test.

From-SVN: r249009

gcc/ChangeLog

+2017-08-08  Julia Koval  <julia.koval@intel.com>
+
+	PR target/73350,80862
+	* config/i386/subst.md (round): Fix round pattern.
+	* config/i386/i386.c (ix86_erase_embedded_rounding):
+	Fix erasing rounding for the fixed pattern.
+
 2017-06-08  Jan Hubicka  <hubicka@ucw.cz>
 
 	* cfgbuild.c (find_many_sub_basic_blocks): Fix thinko.

gcc/config/i386/i386.c

@@ -36460,17 +36460,15 @@ ix86_erase_embedded_rounding (rtx pat)
   if (GET_CODE (pat) == INSN)
     pat = PATTERN (pat);
 
-  gcc_assert (GET_CODE (pat) == PARALLEL);
-
+  if (GET_CODE (pat) == PARALLEL)
+  {
     if (XVECLEN (pat, 0) == 2)
       {
 	rtx p0 = XVECEXP (pat, 0, 0);
 	rtx p1 = XVECEXP (pat, 0, 1);
-
 	gcc_assert (GET_CODE (p0) == SET
 		    && GET_CODE (p1) == UNSPEC
 		    && XINT (p1, 1) == UNSPEC_EMBEDDED_ROUNDING);
-
 	return p0;
       }
     else
@@ -36484,7 +36482,7 @@ ix86_erase_embedded_rounding (rtx pat)
 	    rtx elem = XVECEXP (pat, 0, i);
 	    if (GET_CODE (elem) != UNSPEC
 		|| XINT (elem, 1) != UNSPEC_EMBEDDED_ROUNDING)
-	    res [j++] = elem;
+	      res[j++] = elem;
 	  }
 
 	/*  No more than 1 occurence was removed.  */
@@ -36492,6 +36490,18 @@ ix86_erase_embedded_rounding (rtx pat)
 
 	return gen_rtx_PARALLEL (GET_MODE (pat), gen_rtvec_v (j, res));
     }
+  }
+  else
+  {
+    gcc_assert (GET_CODE (pat) == SET);
+    rtx src = SET_SRC (pat);
+    gcc_assert (XVECLEN (src, 0) == 2);
+    rtx p0 = XVECEXP (src, 0, 0);
+    gcc_assert (GET_CODE (src) == UNSPEC
+		&& XINT (src, 1) == UNSPEC_EMBEDDED_ROUNDING);
+    rtx res = gen_rtx_SET (SET_DEST (pat), p0);
+    return res;
+  }
 }
 
 /* Subroutine of ix86_expand_round_builtin to take care of comi insns

gcc/config/i386/subst.md

@@ -139,10 +139,11 @@
   [(set (match_operand:SUBST_A 0)
 	(match_operand:SUBST_A 1))]
   "TARGET_AVX512F"
-  [(parallel[
-     (set (match_dup 0)
-          (match_dup 1))
-     (unspec [(match_operand:SI 2 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])])
+  [(set (match_dup 0)
+	(unspec:SUBST_A [(match_dup 1)
+	  (match_operand:SI 2 "const_4_or_8_to_11_operand")]
+	  UNSPEC_EMBEDDED_ROUNDING))
+])
 
 (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
 (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")

gcc/testsuite/ChangeLog

+2017-08-08  Julia Koval  <julia.koval@intel.com>
+
+	PR target/73350,80862
+	* gcc.target/i386/pr73350.c: New test.
+
 2017-06-08  Tamar Christina  <tamar.christina@arm.com>
 
 	* gcc.target/aarch64/builtin-fpclassify.c: New codegen test.

gcc/testsuite/gcc.target/i386/pr73350.c

+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+#include <math.h>
+#define AVX512F
+#include "avx512f-helper.h"
+
+void
+TEST (void)
+{
+  __m512 a = _mm512_set1_ps ((float) M_PI);
+  __m512 b = _mm512_set1_ps ((float) 1.f);
+
+  __m512 result1 = _mm512_add_round_ps (a, b, (_MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC));
+  __m512 result2 = _mm512_add_round_ps (a, b, (_MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC));
+   
+  if (result1[0] == result2[0])
+    abort ();
+}